| /netbsd/src/sys/dev/ic/ |
| D | athn.c | 495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff); in athn_rx_start() 496 AR_WRITE(sc, AR_BSSMSKU, 0xffff); in athn_rx_start() 501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff); in athn_rx_start() 502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff); in athn_rx_start() 504 AR_WRITE(sc, AR_FILT_OFDM, 0); in athn_rx_start() 505 AR_WRITE(sc, AR_FILT_CCK, 0); in athn_rx_start() 506 AR_WRITE(sc, AR_MIBC, 0); in athn_rx_start() 507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING); in athn_rx_start() 508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING); in athn_rx_start() 511 AR_WRITE(sc, AR_PHY_ERR_1, 0); in athn_rx_start() [all …]
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| D | arn9280.c | 180 AR_WRITE(sc, AR_PHY(637), 0x00000000); in ar9280_set_synth() 181 AR_WRITE(sc, AR_PHY(638), 0xefff0301); in ar9280_set_synth() 182 AR_WRITE(sc, AR_PHY(639), 0xca9228ee); in ar9280_set_synth() 185 AR_WRITE(sc, AR_PHY(637), 0x00fffeff); in ar9280_set_synth() 186 AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff); in ar9280_set_synth() 187 AR_WRITE(sc, AR_PHY(639), 0xb79f6427); in ar9280_set_synth() 196 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); in ar9280_set_synth() 222 AR_WRITE(sc, AR_AN_SYNTH9, reg); in ar9280_set_synth() 227 AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy); in ar9280_set_synth() 245 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); in ar9280_init_from_rom() [all …]
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| D | arn5416.c | 188 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg); in ar5416_set_synth() 218 AR_WRITE(sc, AR_PHY(0x37), phy); in ar5416_set_synth() 235 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); in ar5416_init_from_rom() 244 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, in ar5416_init_from_rom() 252 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); in ar5416_init_from_rom() 263 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); in ar5416_init_from_rom() 271 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); in ar5416_init_from_rom() 276 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); in ar5416_init_from_rom() 280 AR_WRITE(sc, AR_PHY_SETTLING, reg); in ar5416_init_from_rom() 285 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); in ar5416_init_from_rom() [all …]
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| D | arn9285.c | 191 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); in ar9285_init_from_rom() 192 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain); in ar9285_init_from_rom() 197 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg); in ar9285_init_from_rom() 209 AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg); in ar9285_init_from_rom() 221 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); in ar9285_init_from_rom() 230 AR_WRITE(sc, AR_PHY_RXGAIN, reg); in ar9285_init_from_rom() 236 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); in ar9285_init_from_rom() 252 AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg); in ar9285_init_from_rom() 260 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg); in ar9285_init_from_rom() 318 AR_WRITE(sc, AR9285_AN_RF2G3, reg); in ar9285_init_from_rom() [all …]
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| D | arn9287.c | 167 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon); in ar9287_init_from_rom() 172 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset, in ar9287_init_from_rom() 180 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg); in ar9287_init_from_rom() 187 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg); in ar9287_init_from_rom() 194 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg); in ar9287_init_from_rom() 204 AR_WRITE(sc, AR_PHY_SETTLING, reg); in ar9287_init_from_rom() 208 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg); in ar9287_init_from_rom() 214 AR_WRITE(sc, AR_PHY_RF_CTL4, reg); in ar9287_init_from_rom() 218 AR_WRITE(sc, AR_PHY_RF_CTL3, reg); in ar9287_init_from_rom() 222 AR_WRITE(sc, AR_PHY_CCA(0), reg); in ar9287_init_from_rom() [all …]
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| D | arn5008.c | 390 AR_WRITE(sc, AR7010_GPIO_OUT, reg); in ar5008_gpio_write() 398 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); in ar5008_gpio_write() 416 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); in ar5008_gpio_config_input() 441 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); in ar5008_gpio_config_output() 446 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); in ar5008_gpio_config_output() 459 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); in ar5008_rfsilent_init() 718 AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr); in ar5008_rx_enable() 719 AR_WRITE(sc, AR_CR, AR_CR_RXE); in ar5008_rx_enable() 822 AR_WRITE(sc, AR_RXDP, nbf->bf_daddr); in ar5008_rx_process() 949 AR_WRITE(sc, AR_RXDP, bf->bf_daddr); in ar5008_rx_process() [all …]
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| D | arn9380.c | 275 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE); in ar9380_set_synth() 280 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0); in ar9380_set_synth() 291 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy); in ar9380_set_synth() 294 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH); in ar9380_set_synth() 319 AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg); in ar9380_init_from_rom() 325 AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg); in ar9380_init_from_rom() 330 AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg); in ar9380_init_from_rom() 336 AR_WRITE(sc, AR_PHY_SWITCH_COM, reg); in ar9380_init_from_rom() 339 AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg); in ar9380_init_from_rom() 345 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg); in ar9380_init_from_rom() [all …]
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| D | arn9003.c | 543 AR_WRITE(sc, AR_GPIO_IN_OUT, reg); in ar9003_gpio_write() 555 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); in ar9003_gpio_config_input() 571 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg); in ar9003_gpio_config_output() 576 AR_WRITE(sc, AR_GPIO_OE_OUT, reg); in ar9003_gpio_config_output() 589 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg); in ar9003_rfsilent_init() 827 AR_WRITE(sc, AR_Q_STATUS_RING_START, in ar9003_reset_txsring() 829 AR_WRITE(sc, AR_Q_STATUS_RING_END, in ar9003_reset_txsring() 846 AR_WRITE(sc, AR_RXBP_THRESH, reg); in ar9003_rx_enable() 849 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds)); in ar9003_rx_enable() 862 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr); in ar9003_rx_enable() [all …]
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| D | athnreg.h | 1462 #define AR_WRITE(sc, reg, val) \ macro 1469 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask)) 1472 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
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| /netbsd/src/sys/dev/usb/ |
| D | if_athn_usb.c | 1508 AR_WRITE(sc, AR_RX_FILTER, reg); in athn_usb_newstate_cb() 1733 AR_WRITE(sc, AR_CR, AR_CR_RXE); in athn_usb_rx_enable()
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