1 /* $NetBSD: arn9285.c,v 1.5 2022/09/25 18:43:32 thorpej Exp $ */
2 /* $OpenBSD: ar9285.c,v 1.19 2012/06/10 21:23:36 kettenis Exp $ */
3
4 /*-
5 * Copyright (c) 2009-2010 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2008-2010 Atheros Communications Inc.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for Atheros 802.11a/g/n chipsets.
23 * Routines for AR9285 and AR9271 chipsets.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: arn9285.c,v 1.5 2022/09/25 18:43:32 thorpej Exp $");
28
29 #ifndef _MODULE
30 #include "athn_usb.h"
31 #endif
32
33 #include <sys/param.h>
34 #include <sys/sockio.h>
35 #include <sys/mbuf.h>
36 #include <sys/kernel.h>
37 #include <sys/socket.h>
38 #include <sys/systm.h>
39 #include <sys/queue.h>
40 #include <sys/callout.h>
41 #include <sys/conf.h>
42 #include <sys/device.h>
43
44 #include <sys/bus.h>
45 #include <sys/endian.h>
46 #include <sys/intr.h>
47
48 #include <net/bpf.h>
49 #include <net/if.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_ether.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55
56 #include <netinet/in.h>
57 #include <netinet/in_systm.h>
58 #include <netinet/in_var.h>
59 #include <netinet/ip.h>
60
61 #include <net80211/ieee80211_var.h>
62 #include <net80211/ieee80211_amrr.h>
63 #include <net80211/ieee80211_radiotap.h>
64
65 #include <dev/ic/athnreg.h>
66 #include <dev/ic/athnvar.h>
67 #include <dev/ic/arn9285.h>
68
69 #include <dev/ic/arn5008reg.h>
70 #include <dev/ic/arn9280reg.h>
71 #include <dev/ic/arn9285reg.h>
72
73 #include <dev/ic/arn5008.h>
74 #include <dev/ic/arn9280.h>
75 #include <dev/ic/arn9285.h>
76
77 #define Static static
78
79 Static int ar9285_cl_cal(struct athn_softc *, struct ieee80211_channel *,
80 struct ieee80211_channel *);
81 Static void ar9285_get_pdadcs(struct athn_softc *,
82 struct ieee80211_channel *, int, uint8_t, uint8_t *,
83 uint8_t *);
84 Static const struct ar_spur_chan *
85 ar9285_get_spur_chans(struct athn_softc *, int);
86 Static void ar9285_init_from_rom(struct athn_softc *,
87 struct ieee80211_channel *, struct ieee80211_channel *);
88 Static void ar9285_set_power_calib(struct athn_softc *,
89 struct ieee80211_channel *);
90 Static void ar9285_set_txpower(struct athn_softc *,
91 struct ieee80211_channel *, struct ieee80211_channel *);
92 Static void ar9285_setup(struct athn_softc *);
93 Static void ar9285_swap_rom(struct athn_softc *);
94
95 PUBLIC int
ar9285_attach(struct athn_softc * sc)96 ar9285_attach(struct athn_softc *sc)
97 {
98
99 sc->sc_eep_base = AR9285_EEP_START_LOC;
100 sc->sc_eep_size = sizeof(struct ar9285_eeprom);
101 sc->sc_def_nf = AR9285_PHY_CCA_MAX_GOOD_VALUE;
102 sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 12;
103 sc->sc_led_pin = (sc->sc_flags & ATHN_FLAG_USB) ? 15 : 1;
104 sc->sc_workaround = AR9285_WA_DEFAULT;
105 sc->sc_ops.setup = ar9285_setup;
106 sc->sc_ops.swap_rom = ar9285_swap_rom;
107 sc->sc_ops.init_from_rom = ar9285_init_from_rom;
108 sc->sc_ops.set_txpower = ar9285_set_txpower;
109 sc->sc_ops.set_synth = ar9280_set_synth;
110 sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
111 sc->sc_ops.get_spur_chans = ar9285_get_spur_chans;
112 #if NATHN_USB > 0
113 if (AR_SREV_9271(sc))
114 sc->sc_ini = &ar9271_ini;
115 else
116 #endif
117 sc->sc_ini = &ar9285_1_2_ini;
118 sc->sc_serdes = &ar9280_2_0_serdes;
119
120 return ar5008_attach(sc);
121 }
122
123 Static void
ar9285_setup(struct athn_softc * sc)124 ar9285_setup(struct athn_softc *sc)
125 {
126 const struct ar9285_eeprom *eep = sc->sc_eep;
127 uint8_t type;
128
129 /* Select initialization values based on ROM. */
130 type = eep->baseEepHeader.txGainType;
131 DPRINTFN(DBG_TX, sc, "Tx gain type=0x%x\n", type);
132 #if NATHN_USB > 0
133 if (AR_SREV_9271(sc)) {
134 if (type == AR_EEP_TXGAIN_HIGH_POWER)
135 sc->sc_tx_gain = &ar9271_tx_gain_high_power;
136 else
137 sc->sc_tx_gain = &ar9271_tx_gain;
138 }
139 else
140 #endif /* NATHN_USB */
141 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) { /* XE rev. */
142 if (type == AR_EEP_TXGAIN_HIGH_POWER)
143 sc->sc_tx_gain = &ar9285_2_0_tx_gain_high_power;
144 else
145 sc->sc_tx_gain = &ar9285_2_0_tx_gain;
146 }
147 else {
148 if (type == AR_EEP_TXGAIN_HIGH_POWER)
149 sc->sc_tx_gain = &ar9285_1_2_tx_gain_high_power;
150 else
151 sc->sc_tx_gain = &ar9285_1_2_tx_gain;
152 }
153 }
154
155 Static void
ar9285_swap_rom(struct athn_softc * sc)156 ar9285_swap_rom(struct athn_softc *sc)
157 {
158 struct ar9285_eeprom *eep = sc->sc_eep;
159 int i;
160
161 eep->modalHeader.antCtrlCommon =
162 bswap32(eep->modalHeader.antCtrlCommon);
163 eep->modalHeader.antCtrlChain =
164 bswap32(eep->modalHeader.antCtrlChain);
165
166 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
167 eep->modalHeader.spurChans[i].spurChan =
168 bswap16(eep->modalHeader.spurChans[i].spurChan);
169 }
170 }
171
172 Static const struct ar_spur_chan *
ar9285_get_spur_chans(struct athn_softc * sc,int is2ghz)173 ar9285_get_spur_chans(struct athn_softc *sc, int is2ghz)
174 {
175 const struct ar9285_eeprom *eep = sc->sc_eep;
176
177 KASSERT(is2ghz);
178 return eep->modalHeader.spurChans;
179 }
180
181 Static void
ar9285_init_from_rom(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)182 ar9285_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
183 struct ieee80211_channel *extc)
184 {
185 const struct ar9285_eeprom *eep = sc->sc_eep;
186 const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
187 uint32_t reg, offset = 0x1000;
188 uint8_t ob[5], db1[5], db2[5];
189 uint8_t txRxAtten;
190
191 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
192 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
193
194 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0);
195 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, modal->iqCalI);
196 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, modal->iqCalQ);
197 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
198
199 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
200 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ);
201 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
202 modal->bswMargin);
203 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
204 modal->bswAtten);
205 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
206 modal->xatten2Margin);
207 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
208 modal->xatten2Db);
209 AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
210
211 /* Duplicate values of chain 0 for chain 1. */
212 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
213 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
214 modal->bswMargin);
215 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
216 modal->bswAtten);
217 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
218 modal->xatten2Margin);
219 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
220 modal->xatten2Db);
221 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
222 }
223 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
224 txRxAtten = modal->txRxAtten;
225 else /* Workaround for ROM versions < 14.3. */
226 txRxAtten = 23;
227 reg = AR_READ(sc, AR_PHY_RXGAIN);
228 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
229 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
230 AR_WRITE(sc, AR_PHY_RXGAIN, reg);
231
232 /* Duplicate values of chain 0 for chain 1. */
233 reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
234 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
235 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN, modal->rxTxMargin);
236 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
237
238 if (modal->version >= 3) {
239 /* Setup antenna diversity from ROM. */
240 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL);
241 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL_ALL, 0);
242 reg = RW(reg, AR9285_PHY_ANT_DIV_CTL,
243 (modal->ob_234 >> 12) & 0x1);
244 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_LNACONF,
245 (modal->db1_234 >> 12) & 0x3);
246 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_LNACONF,
247 (modal->db1_234 >> 14) & 0x3);
248 reg = RW(reg, AR9285_PHY_ANT_DIV_ALT_GAINTB,
249 (modal->ob_234 >> 13) & 0x1);
250 reg = RW(reg, AR9285_PHY_ANT_DIV_MAIN_GAINTB,
251 (modal->ob_234 >> 14) & 0x1);
252 AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
253 reg = AR_READ(sc, AR_PHY_MULTICHAIN_GAIN_CTL); /* Flush. */
254
255 reg = AR_READ(sc, AR_PHY_CCK_DETECT);
256 if (modal->ob_234 & (1 << 15))
257 reg |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
258 else
259 reg &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
260 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
261 reg = AR_READ(sc, AR_PHY_CCK_DETECT); /* Flush. */
262 }
263 if (modal->version >= 2) {
264 ob [0] = (modal->ob_01 >> 0) & 0xf;
265 ob [1] = (modal->ob_01 >> 4) & 0xf;
266 ob [2] = (modal->ob_234 >> 0) & 0xf;
267 ob [3] = (modal->ob_234 >> 4) & 0xf;
268 ob [4] = (modal->ob_234 >> 8) & 0xf;
269
270 db1[0] = (modal->db1_01 >> 0) & 0xf;
271 db1[1] = (modal->db1_01 >> 4) & 0xf;
272 db1[2] = (modal->db1_234 >> 0) & 0xf;
273 db1[3] = (modal->db1_234 >> 4) & 0xf;
274 db1[4] = (modal->db1_234 >> 8) & 0xf;
275
276 db2[0] = (modal->db2_01 >> 0) & 0xf;
277 db2[1] = (modal->db2_01 >> 4) & 0xf;
278 db2[2] = (modal->db2_234 >> 0) & 0xf;
279 db2[3] = (modal->db2_234 >> 4) & 0xf;
280 db2[4] = (modal->db2_234 >> 8) & 0xf;
281
282 }
283 else if (modal->version == 1) {
284 ob [0] = (modal->ob_01 >> 0) & 0xf;
285 ob [1] = (modal->ob_01 >> 4) & 0xf;
286 /* Field ob_234 does not exist, use ob_01. */
287 ob [2] = ob [3] = ob [4] = ob [1];
288
289 db1[0] = (modal->db1_01 >> 0) & 0xf;
290 db1[1] = (modal->db1_01 >> 4) & 0xf;
291 /* Field db1_234 does not exist, use db1_01. */
292 db1[2] = db1[3] = db1[4] = db1[1];
293
294 db2[0] = (modal->db2_01 >> 0) & 0xf;
295 db2[1] = (modal->db2_01 >> 4) & 0xf;
296 /* Field db2_234 does not exist, use db2_01. */
297 db2[2] = db2[3] = db2[4] = db2[1];
298
299 }
300 else {
301 ob [0] = modal->ob_01;
302 ob [1] = ob [2] = ob [3] = ob [4] = ob [0];
303
304 db1[0] = modal->db1_01;
305 db1[1] = db1[2] = db1[3] = db1[4] = db1[0];
306
307 /* Field db2_01 does not exist, use db1_01. */
308 db2[0] = modal->db1_01;
309 db2[1] = db2[2] = db2[3] = db2[4] = db2[0];
310 }
311 #if NATHN_USB > 0
312 if (AR_SREV_9271(sc)) {
313 reg = AR_READ(sc, AR9285_AN_RF2G3);
314 reg = RW(reg, AR9271_AN_RF2G3_OB_CCK, ob [0]);
315 reg = RW(reg, AR9271_AN_RF2G3_OB_PSK, ob [1]);
316 reg = RW(reg, AR9271_AN_RF2G3_OB_QAM, ob [2]);
317 reg = RW(reg, AR9271_AN_RF2G3_DB1, db1[0]);
318 AR_WRITE(sc, AR9285_AN_RF2G3, reg);
319 AR_WRITE_BARRIER(sc);
320 DELAY(100);
321 reg = AR_READ(sc, AR9285_AN_RF2G4);
322 reg = RW(reg, AR9271_AN_RF2G4_DB2, (uint32_t)db2[0]);
323 AR_WRITE(sc, AR9285_AN_RF2G4, reg);
324 AR_WRITE_BARRIER(sc);
325 DELAY(100);
326 }
327 else
328 #endif /* ATHN_USB */
329 {
330 reg = AR_READ(sc, AR9285_AN_RF2G3);
331 reg = RW(reg, AR9285_AN_RF2G3_OB_0, ob [0]);
332 reg = RW(reg, AR9285_AN_RF2G3_OB_1, ob [1]);
333 reg = RW(reg, AR9285_AN_RF2G3_OB_2, ob [2]);
334 reg = RW(reg, AR9285_AN_RF2G3_OB_3, ob [3]);
335 reg = RW(reg, AR9285_AN_RF2G3_OB_4, ob [4]);
336 reg = RW(reg, AR9285_AN_RF2G3_DB1_0, db1[0]);
337 reg = RW(reg, AR9285_AN_RF2G3_DB1_1, db1[1]);
338 reg = RW(reg, AR9285_AN_RF2G3_DB1_2, db1[2]);
339 AR_WRITE(sc, AR9285_AN_RF2G3, reg);
340 AR_WRITE_BARRIER(sc);
341 DELAY(100);
342 reg = AR_READ(sc, AR9285_AN_RF2G4);
343 reg = RW(reg, AR9285_AN_RF2G4_DB1_3, db1[3]);
344 reg = RW(reg, AR9285_AN_RF2G4_DB1_4, db1[4]);
345 reg = RW(reg, AR9285_AN_RF2G4_DB2_0, db2[0]);
346 reg = RW(reg, AR9285_AN_RF2G4_DB2_1, db2[1]);
347 reg = RW(reg, AR9285_AN_RF2G4_DB2_2, db2[2]);
348 reg = RW(reg, AR9285_AN_RF2G4_DB2_3, db2[3]);
349 reg = RW(reg, AR9285_AN_RF2G4_DB2_4, db2[4]);
350 AR_WRITE(sc, AR9285_AN_RF2G4, reg);
351 AR_WRITE_BARRIER(sc);
352 DELAY(100);
353 }
354
355 reg = AR_READ(sc, AR_PHY_SETTLING);
356 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
357 AR_WRITE(sc, AR_PHY_SETTLING, reg);
358
359 reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
360 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
361 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
362
363 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
364 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
365 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
366 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
367 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
368
369 reg = AR_READ(sc, AR_PHY_RF_CTL3);
370 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
371 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
372
373 reg = AR_READ(sc, AR_PHY_CCA(0));
374 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
375 AR_WRITE(sc, AR_PHY_CCA(0), reg);
376
377 reg = AR_READ(sc, AR_PHY_EXT_CCA0);
378 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
379 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
380
381 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
382 reg = AR_READ(sc, AR_PHY_RF_CTL2);
383 reg = RW(reg, AR_PHY_TX_END_PA_ON,
384 modal->txFrameToPaOn);
385 reg = RW(reg, AR_PHY_TX_END_DATA_START,
386 modal->txFrameToDataStart);
387 AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
388 }
389 #ifndef IEEE80211_NO_HT
390 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
391 reg = AR_READ(sc, AR_PHY_SETTLING);
392 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
393 AR_WRITE(sc, AR_PHY_SETTLING, reg);
394 }
395 #endif
396 AR_WRITE_BARRIER(sc);
397 }
398
399 PUBLIC void
ar9285_pa_calib(struct athn_softc * sc)400 ar9285_pa_calib(struct athn_softc *sc)
401 {
402 /* List of registers that need to be saved/restored. */
403 static const uint16_t regs[] = {
404 AR9285_AN_TOP3,
405 AR9285_AN_RXTXBB1,
406 AR9285_AN_RF2G1,
407 AR9285_AN_RF2G2,
408 AR9285_AN_TOP2,
409 AR9285_AN_RF2G8,
410 AR9285_AN_RF2G7
411 };
412 uint32_t svg[7], reg, ccomp_svg;
413 size_t i;
414
415 /* No PA calibration needed for high power solutions. */
416 if (AR_SREV_9285(sc) &&
417 ((struct ar9285_base_eep_header *)sc->sc_eep)->txGainType ==
418 AR_EEP_TXGAIN_HIGH_POWER) /* XXX AR9287? */
419 return;
420
421 /* Save registers. */
422 for (i = 0; i < __arraycount(regs); i++)
423 svg[i] = AR_READ(sc, regs[i]);
424
425 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1);
426 AR_SETBITS(sc, AR_PHY(2), 1 << 27);
427
428 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
429 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
430 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
431 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
432 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
433 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
434 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
435 /* Power down PA drivers. */
436 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
437 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
438 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
439
440 reg = AR_READ(sc, AR9285_AN_RF2G8);
441 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
442 AR_WRITE(sc, AR9285_AN_RF2G8, reg);
443
444 reg = AR_READ(sc, AR9285_AN_RF2G7);
445 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
446 AR_WRITE(sc, AR9285_AN_RF2G7, reg);
447
448 reg = AR_READ(sc, AR9285_AN_RF2G6);
449 /* Save compensation capacitor value. */
450 ccomp_svg = MS(reg, AR9285_AN_RF2G6_CCOMP);
451 /* Program compensation capacitor for dynamic PA. */
452 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, 0xf);
453 AR_WRITE(sc, AR9285_AN_RF2G6, reg);
454
455 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
456 AR_WRITE_BARRIER(sc);
457 DELAY(30);
458
459 /* Clear offsets 6-1. */
460 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS_6_1);
461 /* Clear offset 0. */
462 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
463 /* Set offsets 6-1. */
464 for (i = 6; i >= 1; i--) {
465 AR_SETBITS(sc, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS(i));
466 AR_WRITE_BARRIER(sc);
467 DELAY(1);
468 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9) {
469 AR_SETBITS(sc, AR9285_AN_RF2G6,
470 AR9285_AN_RF2G6_OFFS(i));
471 }
472 else {
473 AR_CLRBITS(sc, AR9285_AN_RF2G6,
474 AR9285_AN_RF2G6_OFFS(i));
475 }
476 }
477 /* Set offset 0. */
478 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
479 AR_WRITE_BARRIER(sc);
480 DELAY(1);
481 if (AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9)
482 AR_SETBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
483 else
484 AR_CLRBITS(sc, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP);
485
486 AR_WRITE_BARRIER(sc);
487
488 AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
489 AR_CLRBITS(sc, AR_PHY(2), 1 << 27);
490
491 /* Restore registers. */
492 for (i = 0; i < __arraycount(regs); i++)
493 AR_WRITE(sc, regs[i], svg[i]);
494
495 /* Restore compensation capacitor value. */
496 reg = AR_READ(sc, AR9285_AN_RF2G6);
497 reg = RW(reg, AR9285_AN_RF2G6_CCOMP, ccomp_svg);
498 AR_WRITE(sc, AR9285_AN_RF2G6, reg);
499 AR_WRITE_BARRIER(sc);
500 }
501
502 PUBLIC void
ar9271_pa_calib(struct athn_softc * sc)503 ar9271_pa_calib(struct athn_softc *sc)
504 {
505 #if NATHN_USB > 0
506 /* List of registers that need to be saved/restored. */
507 static const uint16_t regs[] = {
508 AR9285_AN_TOP3,
509 AR9285_AN_RXTXBB1,
510 AR9285_AN_RF2G1,
511 AR9285_AN_RF2G2,
512 AR9285_AN_TOP2,
513 AR9285_AN_RF2G8,
514 AR9285_AN_RF2G7
515 };
516 uint32_t svg[7], reg, rf2g3_svg;
517 size_t i;
518
519 /* Save registers. */
520 for (i = 0; i < __arraycount(regs); i++)
521 svg[i] = AR_READ(sc, regs[i]);
522
523 AR_CLRBITS(sc, AR9285_AN_RF2G6, 1);
524 AR_SETBITS(sc, AR_PHY(2), 1 << 27);
525
526 AR_SETBITS(sc, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC);
527 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1);
528 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I);
529 AR_SETBITS(sc, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF);
530 AR_CLRBITS(sc, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL);
531 AR_CLRBITS(sc, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB);
532 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL);
533 /* Power down PA drivers. */
534 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1);
535 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2);
536 AR_CLRBITS(sc, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT);
537
538 reg = AR_READ(sc, AR9285_AN_RF2G8);
539 reg = RW(reg, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
540 AR_WRITE(sc, AR9285_AN_RF2G8, reg);
541
542 reg = AR_READ(sc, AR9285_AN_RF2G7);
543 reg = RW(reg, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
544 AR_WRITE(sc, AR9285_AN_RF2G7, reg);
545
546 /* Save compensation capacitor value. */
547 reg = rf2g3_svg = AR_READ(sc, AR9285_AN_RF2G3);
548 /* Program compensation capacitor for dynamic PA. */
549 reg = RW(reg, AR9271_AN_RF2G3_CCOMP, 0xfff);
550 AR_WRITE(sc, AR9285_AN_RF2G3, reg);
551
552 AR_WRITE(sc, AR9285_AN_TOP2, AR9285_AN_TOP2_DEFAULT);
553 AR_WRITE_BARRIER(sc);
554 DELAY(30);
555
556 /* Clear offsets 6-0. */
557 AR_CLRBITS(sc, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS_6_0);
558 /* Set offsets 6-1. */
559 for (i = 6; i >= 1; i--) {
560 reg = AR_READ(sc, AR9285_AN_RF2G6);
561 reg |= AR9271_AN_RF2G6_OFFS(i);
562 AR_WRITE(sc, AR9285_AN_RF2G6, reg);
563 AR_WRITE_BARRIER(sc);
564 DELAY(1);
565 if (!(AR_READ(sc, AR9285_AN_RF2G9) & AR9285_AN_RXTXBB1_SPARE9))
566 reg &= ~AR9271_AN_RF2G6_OFFS(i);
567 AR_WRITE(sc, AR9285_AN_RF2G6, reg);
568 }
569 AR_WRITE_BARRIER(sc);
570
571 AR_SETBITS(sc, AR9285_AN_RF2G6, 1);
572 AR_CLRBITS(sc, AR_PHY(2), 1 << 27);
573
574 /* Restore registers. */
575 for (i = 0; i < __arraycount(regs); i++)
576 AR_WRITE(sc, regs[i], svg[i]);
577
578 /* Restore compensation capacitor value. */
579 AR_WRITE(sc, AR9285_AN_RF2G3, rf2g3_svg);
580 AR_WRITE_BARRIER(sc);
581 #endif /* NATHN_USB */
582 }
583
584 /*
585 * Carrier Leakage Calibration.
586 */
587 int
ar9285_cl_cal(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)588 ar9285_cl_cal(struct athn_softc *sc, struct ieee80211_channel *c,
589 struct ieee80211_channel *extc)
590 {
591 int ntries;
592
593 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
594 #ifndef IEEE80211_NO_HT
595 if (0 && extc == NULL) { /* XXX IS_CHAN_HT20!! */
596 AR_SETBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
597 AR_SETBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
598 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
599 AR_PHY_AGC_CONTROL_FLTR_CAL);
600 AR_CLRBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
601 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
602 for (ntries = 0; ntries < 10000; ntries++) {
603 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
604 AR_PHY_AGC_CONTROL_CAL))
605 break;
606 DELAY(10);
607 }
608 if (ntries == 10000)
609 return ETIMEDOUT;
610 AR_CLRBITS(sc, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
611 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
612 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
613 }
614 #endif
615 AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
616 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
617 AR_SETBITS(sc, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
618 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
619 for (ntries = 0; ntries < 10000; ntries++) {
620 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
621 AR_PHY_AGC_CONTROL_CAL))
622 break;
623 DELAY(10);
624 }
625 if (ntries == 10000)
626 return ETIMEDOUT;
627 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
628 AR_CLRBITS(sc, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
629 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
630 AR_WRITE_BARRIER(sc);
631 return 0;
632 }
633
634 PUBLIC void
ar9271_load_ani(struct athn_softc * sc)635 ar9271_load_ani(struct athn_softc *sc)
636 {
637
638 #if NATHN_USB > 0
639 /* Write ANI registers. */
640 AR_WRITE(sc, AR_PHY_DESIRED_SZ, 0x6d4000e2);
641 AR_WRITE(sc, AR_PHY_AGC_CTL1, 0x3139605e);
642 AR_WRITE(sc, AR_PHY_FIND_SIG, 0x7ec84d2e);
643 AR_WRITE(sc, AR_PHY_SFCORR_LOW, 0x06903881);
644 AR_WRITE(sc, AR_PHY_SFCORR, 0x5ac640d0);
645 AR_WRITE(sc, AR_PHY_CCK_DETECT, 0x803e68c8);
646 AR_WRITE(sc, AR_PHY_TIMING5, 0xd00a8007);
647 AR_WRITE(sc, AR_PHY_SFCORR_EXT, 0x05eea6d4);
648 AR_WRITE_BARRIER(sc);
649 #endif /* NATHN_USB */
650 }
651
652 int
ar9285_init_calib(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)653 ar9285_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
654 struct ieee80211_channel *extc)
655 {
656 uint32_t reg, mask, clcgain, rf2g5_svg;
657 int i, maxgain, nclcs, thresh, error;
658
659 /* Do carrier leakage calibration. */
660 if ((error = ar9285_cl_cal(sc, c, extc)) != 0)
661 return error;
662
663 /* Workaround for high temperature is not applicable on AR9271. */
664 if (AR_SREV_9271(sc))
665 return 0;
666
667 mask = 0;
668 nclcs = 0;
669 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
670 maxgain = MS(reg, AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
671 for (i = 0; i <= maxgain; i++) {
672 reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
673 clcgain = MS(reg, AR_PHY_TX_GAIN_CLC);
674 /* NB: clcgain <= 0xf. */
675 if (!(mask & (1 << clcgain))) {
676 mask |= 1 << clcgain;
677 nclcs++;
678 }
679 }
680 thresh = 0;
681 for (i = 0; i < nclcs; i++) {
682 reg = AR_READ(sc, AR_PHY_CLC_TBL(i));
683 if (MS(reg, AR_PHY_CLC_I0) == 0)
684 thresh++;
685 if (MS(reg, AR_PHY_CLC_Q0) == 0)
686 thresh++;
687 }
688 if (thresh <= AR9285_CL_CAL_REDO_THRESH)
689 return 0; /* No need to redo. */
690
691 /* Threshold reached, redo carrier leakage calibration. */
692 DPRINTFN(DBG_INIT, sc, "CLC threshold=%d\n", thresh);
693 rf2g5_svg = reg = AR_READ(sc, AR9285_AN_RF2G5);
694 if ((AR_READ(sc, AR_AN_SYNTH9) & 0x7) == 0x1) /* XE rev. */
695 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x5);
696 else
697 reg = RW(reg, AR9285_AN_RF2G5_IC50TX, 0x4);
698 AR_WRITE(sc, AR9285_AN_RF2G5, reg);
699 AR_WRITE_BARRIER(sc);
700 error = ar9285_cl_cal(sc, c, extc);
701 AR_WRITE(sc, AR9285_AN_RF2G5, rf2g5_svg);
702 AR_WRITE_BARRIER(sc);
703 return error;
704 }
705
706 Static void
ar9285_get_pdadcs(struct athn_softc * sc,struct ieee80211_channel * c,int nxpdgains,uint8_t overlap,uint8_t * boundaries,uint8_t * pdadcs)707 ar9285_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
708 int nxpdgains, uint8_t overlap, uint8_t *boundaries, uint8_t *pdadcs)
709 {
710 const struct ar9285_eeprom *eep = sc->sc_eep;
711 const struct ar9285_cal_data_per_freq *pierdata;
712 const uint8_t *pierfreq;
713 struct athn_pier lopier, hipier;
714 uint8_t fbin;
715 int i, lo, hi, npiers;
716
717 pierfreq = eep->calFreqPier2G;
718 pierdata = eep->calPierData2G;
719 npiers = AR9285_NUM_2G_CAL_PIERS;
720
721 /* Find channel in ROM pier table. */
722 fbin = athn_chan2fbin(c);
723 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
724
725 lopier.fbin = pierfreq[lo];
726 hipier.fbin = pierfreq[hi];
727 for (i = 0; i < nxpdgains; i++) {
728 lopier.pwr[i] = pierdata[lo].pwrPdg[i];
729 lopier.vpd[i] = pierdata[lo].vpdPdg[i];
730 hipier.pwr[i] = pierdata[lo].pwrPdg[i];
731 hipier.vpd[i] = pierdata[lo].vpdPdg[i];
732 }
733 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
734 AR9285_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
735 }
736
737 Static void
ar9285_set_power_calib(struct athn_softc * sc,struct ieee80211_channel * c)738 ar9285_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
739 {
740 const struct ar9285_eeprom *eep = sc->sc_eep;
741 uint8_t boundaries[AR_PD_GAINS_IN_MASK];
742 uint8_t pdadcs[AR_NUM_PDADC_VALUES];
743 uint8_t xpdgains[AR9285_NUM_PD_GAINS];
744 uint8_t overlap;
745 uint32_t reg;
746 int i, nxpdgains;
747
748 if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
749 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
750 AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
751 }
752 else
753 overlap = eep->modalHeader.pdGainOverlap;
754
755 nxpdgains = 0;
756 memset(xpdgains, 0, sizeof(xpdgains));
757 for (i = AR9285_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
758 if (nxpdgains >= AR9285_NUM_PD_GAINS)
759 break;
760 if (eep->modalHeader.xpdGain & (1 << i))
761 xpdgains[nxpdgains++] = i;
762 }
763 reg = AR_READ(sc, AR_PHY_TPCRG1);
764 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
765 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
766 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
767 AR_WRITE(sc, AR_PHY_TPCRG1, reg);
768
769 /* NB: No open loop power control for AR9285. */
770 ar9285_get_pdadcs(sc, c, nxpdgains, overlap, boundaries, pdadcs);
771
772 /* Write boundaries. */
773 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP, overlap);
774 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1, boundaries[0]);
775 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2, boundaries[1]);
776 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3, boundaries[2]);
777 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4, boundaries[3]);
778 AR_WRITE(sc, AR_PHY_TPCRG5, reg);
779
780 /* Write PDADC values. */
781 for (i = 0; i < AR_NUM_PDADC_VALUES; i += 4) {
782 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + i,
783 pdadcs[i + 0] << 0 |
784 pdadcs[i + 1] << 8 |
785 pdadcs[i + 2] << 16 |
786 (uint32_t)pdadcs[i + 3] << 24);
787 }
788 AR_WRITE_BARRIER(sc);
789 }
790
791 Static void
ar9285_set_txpower(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)792 ar9285_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
793 struct ieee80211_channel *extc)
794 {
795 const struct ar9285_eeprom *eep = sc->sc_eep;
796 #ifdef notyet
797 const struct ar9285_modal_eep_header *modal = &eep->modalHeader;
798 #endif
799 uint8_t tpow_cck[4], tpow_ofdm[4];
800 #ifndef IEEE80211_NO_HT
801 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
802 uint8_t tpow_ht20[8], tpow_ht40[8];
803 uint8_t ht40inc;
804 #endif
805 int16_t power[ATHN_POWER_COUNT];
806 int i;
807
808 ar9285_set_power_calib(sc, c);
809
810 #ifdef notyet
811 /* Compute transmit power reduction due to antenna gain. */
812 uint16_t max_ant_gain = modal->antennaGain;
813 /* XXX */
814 #endif
815
816 /* Get CCK target powers. */
817 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
818 AR9285_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
819
820 /* Get OFDM target powers. */
821 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
822 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
823
824 #ifndef IEEE80211_NO_HT
825 /* Get HT-20 target powers. */
826 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
827 AR9285_NUM_2G_20_TARGET_POWERS, tpow_ht20);
828
829 if (extc != NULL) {
830 /* Get HT-40 target powers. */
831 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
832 eep->calTargetPower2GHT40, AR9285_NUM_2G_40_TARGET_POWERS,
833 tpow_ht40);
834
835 /* Get secondary channel CCK target powers. */
836 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
837 eep->calTargetPowerCck, AR9285_NUM_2G_CCK_TARGET_POWERS,
838 tpow_cck_ext);
839
840 /* Get secondary channel OFDM target powers. */
841 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
842 eep->calTargetPower2G, AR9285_NUM_2G_20_TARGET_POWERS,
843 tpow_ofdm_ext);
844 }
845 #endif
846
847 memset(power, 0, sizeof(power));
848 /* Shuffle target powers accross transmit rates. */
849 power[ATHN_POWER_OFDM6 ] =
850 power[ATHN_POWER_OFDM9 ] =
851 power[ATHN_POWER_OFDM12 ] =
852 power[ATHN_POWER_OFDM18 ] =
853 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0];
854 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1];
855 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2];
856 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3];
857 power[ATHN_POWER_XR ] = tpow_ofdm[0];
858 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];
859 power[ATHN_POWER_CCK2_LP ] =
860 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];
861 power[ATHN_POWER_CCK55_LP] =
862 power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
863 power[ATHN_POWER_CCK11_LP] =
864 power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
865 #ifndef IEEE80211_NO_HT
866 for (i = 0; i < __arraycount(tpow_ht20); i++)
867 power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
868 if (extc != NULL) {
869 /* Correct PAR difference between HT40 and HT20/Legacy. */
870 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
871 ht40inc = modal->ht40PowerIncForPdadc;
872 else
873 ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
874 for (i = 0; i < __arraycount(tpow_ht40); i++)
875 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
876 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
877 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];
878 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
879 power[ATHN_POWER_CCK_EXT ] = tpow_cck_ext[0];
880 }
881 #endif
882
883 for (i = 0; i < ATHN_POWER_COUNT; i++) {
884 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */
885 if (power[i] > AR_MAX_RATE_POWER)
886 power[i] = AR_MAX_RATE_POWER;
887 }
888
889 /* Commit transmit power values to hardware. */
890 ar5008_write_txpower(sc, power);
891 }
892