1 /* $NetBSD: arn9287.c,v 1.4 2022/09/25 18:43:32 thorpej Exp $ */
2 /* $OpenBSD: ar9287.c,v 1.17 2012/06/10 21:23:36 kettenis Exp $ */
3
4 /*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2008-2009 Atheros Communications Inc.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for Atheros 802.11a/g/n chipsets.
23 * Routines for AR9227 and AR9287 chipsets.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: arn9287.c,v 1.4 2022/09/25 18:43:32 thorpej Exp $");
28
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/mbuf.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/queue.h>
36 #include <sys/callout.h>
37 #include <sys/conf.h>
38 #include <sys/device.h>
39
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/intr.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_arp.h>
47 #include <net/if_dl.h>
48 #include <net/if_ether.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51
52 #include <netinet/in.h>
53 #include <netinet/in_systm.h>
54 #include <netinet/in_var.h>
55 #include <netinet/ip.h>
56
57 #include <net80211/ieee80211_var.h>
58 #include <net80211/ieee80211_amrr.h>
59 #include <net80211/ieee80211_radiotap.h>
60
61 #include <dev/ic/athnreg.h>
62 #include <dev/ic/athnvar.h>
63
64 #include <dev/ic/arn5008reg.h>
65 #include <dev/ic/arn9280reg.h>
66 #include <dev/ic/arn9287reg.h>
67
68 #include <dev/ic/arn5008.h>
69 #include <dev/ic/arn9280.h>
70 #include <dev/ic/arn9287.h>
71
72 #define Static static
73
74 Static void ar9287_get_pdadcs(struct athn_softc *,
75 struct ieee80211_channel *, int, int, uint8_t, uint8_t *,
76 uint8_t *);
77 Static const struct ar_spur_chan *
78 ar9287_get_spur_chans(struct athn_softc *, int);
79 Static void ar9287_init_from_rom(struct athn_softc *,
80 struct ieee80211_channel *, struct ieee80211_channel *);
81 Static void ar9287_olpc_get_pdgain(struct athn_softc *,
82 struct ieee80211_channel *, int, int8_t *);
83 Static void ar9287_olpc_init(struct athn_softc *);
84 Static void ar9287_olpc_temp_compensation(struct athn_softc *);
85 Static void ar9287_set_power_calib(struct athn_softc *,
86 struct ieee80211_channel *);
87 Static void ar9287_set_txpower(struct athn_softc *,
88 struct ieee80211_channel *, struct ieee80211_channel *);
89 Static void ar9287_setup(struct athn_softc *);
90 Static void ar9287_swap_rom(struct athn_softc *);
91
92 PUBLIC int
ar9287_attach(struct athn_softc * sc)93 ar9287_attach(struct athn_softc *sc)
94 {
95
96 sc->sc_eep_base = AR9287_EEP_START_LOC;
97 sc->sc_eep_size = sizeof(struct ar9287_eeprom);
98 sc->sc_def_nf = AR9287_PHY_CCA_MAX_GOOD_VALUE;
99 sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 11;
100 sc->sc_led_pin = 8;
101 sc->sc_workaround = AR9285_WA_DEFAULT;
102 sc->sc_ops.setup = ar9287_setup;
103 sc->sc_ops.swap_rom = ar9287_swap_rom;
104 sc->sc_ops.init_from_rom = ar9287_init_from_rom;
105 sc->sc_ops.set_txpower = ar9287_set_txpower;
106 sc->sc_ops.set_synth = ar9280_set_synth;
107 sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
108 sc->sc_ops.get_spur_chans = ar9287_get_spur_chans;
109 sc->sc_ops.olpc_init = ar9287_olpc_init;
110 sc->sc_ops.olpc_temp_compensation = ar9287_olpc_temp_compensation;
111 sc->sc_ini = &ar9287_1_1_ini;
112 sc->sc_serdes = &ar9280_2_0_serdes;
113
114 return ar5008_attach(sc);
115 }
116
117 Static void
ar9287_setup(struct athn_softc * sc)118 ar9287_setup(struct athn_softc *sc)
119 {
120 const struct ar9287_eeprom *eep = sc->sc_eep;
121
122 /* Determine if open loop power control should be used. */
123 if (eep->baseEepHeader.openLoopPwrCntl)
124 sc->sc_flags |= ATHN_FLAG_OLPC;
125
126 sc->sc_rx_gain = &ar9287_1_1_rx_gain;
127 sc->sc_tx_gain = &ar9287_1_1_tx_gain;
128 }
129
130 Static void
ar9287_swap_rom(struct athn_softc * sc)131 ar9287_swap_rom(struct athn_softc *sc)
132 {
133 struct ar9287_eeprom *eep = sc->sc_eep;
134 int i;
135
136 eep->modalHeader.antCtrlCommon =
137 bswap32(eep->modalHeader.antCtrlCommon);
138
139 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
140 eep->modalHeader.antCtrlChain[i] =
141 bswap32(eep->modalHeader.antCtrlChain[i]);
142 }
143 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
144 eep->modalHeader.spurChans[i].spurChan =
145 bswap16(eep->modalHeader.spurChans[i].spurChan);
146 }
147 }
148
149 Static const struct ar_spur_chan *
ar9287_get_spur_chans(struct athn_softc * sc,int is2ghz)150 ar9287_get_spur_chans(struct athn_softc *sc, int is2ghz)
151 {
152 const struct ar9287_eeprom *eep = sc->sc_eep;
153
154 KASSERT(is2ghz);
155 return eep->modalHeader.spurChans;
156 }
157
158 Static void
ar9287_init_from_rom(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)159 ar9287_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
160 struct ieee80211_channel *extc)
161 {
162 const struct ar9287_eeprom *eep = sc->sc_eep;
163 const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
164 uint32_t reg, offset;
165 int i;
166
167 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
168
169 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
170 offset = i * 0x1000;
171
172 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
173 modal->antCtrlChain[i]);
174
175 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
176 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
177 modal->iqCalICh[i]);
178 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
179 modal->iqCalQCh[i]);
180 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
181
182 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
183 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
184 modal->bswMargin[i]);
185 reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
186 modal->bswAtten[i]);
187 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
188
189 reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
190 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
191 modal->rxTxMarginCh[i]);
192 reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
193 modal->txRxAttenCh[i]);
194 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
195 }
196
197 reg = AR_READ(sc, AR_PHY_SETTLING);
198 #ifndef IEEE80211_NO_HT
199 if (extc != NULL)
200 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
201 else
202 #endif
203 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
204 AR_WRITE(sc, AR_PHY_SETTLING, reg);
205
206 reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
207 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
208 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
209
210 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
211 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
212 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
213 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
214 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
215
216 reg = AR_READ(sc, AR_PHY_RF_CTL3);
217 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
218 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
219
220 reg = AR_READ(sc, AR_PHY_CCA(0));
221 reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
222 AR_WRITE(sc, AR_PHY_CCA(0), reg);
223
224 reg = AR_READ(sc, AR_PHY_EXT_CCA0);
225 reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
226 AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
227
228 reg = AR_READ(sc, AR9287_AN_RF2G3_CH0);
229 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
230 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
231 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
232 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
233 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
234 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
235 AR_WRITE(sc, AR9287_AN_RF2G3_CH0, reg);
236 AR_WRITE_BARRIER(sc);
237 DELAY(100);
238
239 reg = AR_READ(sc, AR9287_AN_RF2G3_CH1);
240 reg = RW(reg, AR9287_AN_RF2G3_DB1, modal->db1);
241 reg = RW(reg, AR9287_AN_RF2G3_DB2, modal->db2);
242 reg = RW(reg, AR9287_AN_RF2G3_OB_CCK, modal->ob_cck);
243 reg = RW(reg, AR9287_AN_RF2G3_OB_PSK, modal->ob_psk);
244 reg = RW(reg, AR9287_AN_RF2G3_OB_QAM, modal->ob_qam);
245 reg = RW(reg, AR9287_AN_RF2G3_OB_PAL_OFF, modal->ob_pal_off);
246 AR_WRITE(sc, AR9287_AN_RF2G3_CH1, reg);
247 AR_WRITE_BARRIER(sc);
248 DELAY(100);
249
250 reg = AR_READ(sc, AR_PHY_RF_CTL2);
251 reg = RW(reg, AR_PHY_TX_END_DATA_START, modal->txFrameToDataStart);
252 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
253 AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
254
255 reg = AR_READ(sc, AR9287_AN_TOP2);
256 reg = RW(reg, AR9287_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
257 AR_WRITE(sc, AR9287_AN_TOP2, reg);
258 AR_WRITE_BARRIER(sc);
259 DELAY(100);
260 }
261
262 Static void
ar9287_get_pdadcs(struct athn_softc * sc,struct ieee80211_channel * c,int chain,int nxpdgains,uint8_t overlap,uint8_t * boundaries,uint8_t * pdadcs)263 ar9287_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
264 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries,
265 uint8_t *pdadcs)
266 {
267 const struct ar9287_eeprom *eep = sc->sc_eep;
268 const struct ar9287_cal_data_per_freq *pierdata;
269 const uint8_t *pierfreq;
270 struct athn_pier lopier, hipier;
271 int16_t delta;
272 uint8_t fbin;
273 int i, lo, hi, npiers;
274
275 pierfreq = eep->calFreqPier2G;
276 pierdata = (const struct ar9287_cal_data_per_freq *)
277 eep->calPierData2G[chain];
278 npiers = AR9287_NUM_2G_CAL_PIERS;
279
280 /* Find channel in ROM pier table. */
281 fbin = athn_chan2fbin(c);
282 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
283
284 lopier.fbin = pierfreq[lo];
285 hipier.fbin = pierfreq[hi];
286 for (i = 0; i < nxpdgains; i++) {
287 lopier.pwr[i] = pierdata[lo].pwrPdg[i];
288 lopier.vpd[i] = pierdata[lo].vpdPdg[i];
289 hipier.pwr[i] = pierdata[lo].pwrPdg[i];
290 hipier.vpd[i] = pierdata[lo].vpdPdg[i];
291 }
292 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
293 AR9287_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
294
295 delta = (eep->baseEepHeader.pwrTableOffset -
296 AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */
297 if (delta != 0) {
298 /* Shift the PDADC table to start at the new offset. */
299 /* XXX Our padding value differs from Linux. */
300 for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
301 pdadcs[i] = pdadcs[MIN(i + delta,
302 AR_NUM_PDADC_VALUES - 1)];
303 }
304 }
305
306 Static void
ar9287_olpc_get_pdgain(struct athn_softc * sc,struct ieee80211_channel * c,int chain,int8_t * pwr)307 ar9287_olpc_get_pdgain(struct athn_softc *sc, struct ieee80211_channel *c,
308 int chain, int8_t *pwr)
309 {
310 const struct ar9287_eeprom *eep = sc->sc_eep;
311 const struct ar_cal_data_per_freq_olpc *pierdata;
312 const uint8_t *pierfreq;
313 uint8_t fbin;
314 int lo, hi, npiers;
315
316 pierfreq = eep->calFreqPier2G;
317 pierdata = (const struct ar_cal_data_per_freq_olpc *)
318 eep->calPierData2G[chain];
319 npiers = AR9287_NUM_2G_CAL_PIERS;
320
321 /* Find channel in ROM pier table. */
322 fbin = athn_chan2fbin(c);
323 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
324 #if 0
325 *pwr = athn_interpolate(fbin,
326 pierfreq[lo], pierdata[lo].pwrPdg[0][0],
327 pierfreq[hi], pierdata[hi].pwrPdg[0][0]);
328 #else
329 *pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
330 #endif
331 }
332
333 Static void
ar9287_set_power_calib(struct athn_softc * sc,struct ieee80211_channel * c)334 ar9287_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
335 {
336 const struct ar9287_eeprom *eep = sc->sc_eep;
337 uint8_t boundaries[AR_PD_GAINS_IN_MASK];
338 uint8_t pdadcs[AR_NUM_PDADC_VALUES];
339 uint8_t xpdgains[AR9287_NUM_PD_GAINS];
340 int8_t txpower;
341 uint8_t overlap;
342 uint32_t reg, offset;
343 int i, j, nxpdgains;
344
345 if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
346 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
347 AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
348 }
349 else
350 overlap = eep->modalHeader.pdGainOverlap;
351
352 if (sc->sc_flags & ATHN_FLAG_OLPC) {
353 /* XXX not here. */
354 sc->sc_pdadc =
355 ((const struct ar_cal_data_per_freq_olpc *)
356 eep->calPierData2G[0])->vpdPdg[0][0];
357 }
358
359 nxpdgains = 0;
360 memset(xpdgains, 0, sizeof(xpdgains));
361 for (i = AR9287_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
362 if (nxpdgains >= AR9287_NUM_PD_GAINS)
363 break; /* Can't happen. */
364 if (eep->modalHeader.xpdGain & (1 << i))
365 xpdgains[nxpdgains++] = i;
366 }
367 reg = AR_READ(sc, AR_PHY_TPCRG1);
368 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
369 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
370 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
371 AR_WRITE(sc, AR_PHY_TPCRG1, reg);
372 AR_WRITE_BARRIER(sc);
373
374 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
375 if (!(sc->sc_txchainmask & (1 << i)))
376 continue;
377
378 offset = i * 0x1000;
379
380 if (sc->sc_flags & ATHN_FLAG_OLPC) {
381 ar9287_olpc_get_pdgain(sc, c, i, &txpower);
382
383 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
384 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
385 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
386
387 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
388 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
389 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
390
391 /* NB: txpower is in half dB. */
392 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset);
393 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_PWR, txpower);
394 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11 + offset, reg);
395
396 AR_WRITE_BARRIER(sc);
397 continue; /* That's it for open loop mode. */
398 }
399
400 /* Closed loop power control. */
401 ar9287_get_pdadcs(sc, c, i, nxpdgains, overlap,
402 boundaries, pdadcs);
403
404 /* Write boundaries. */
405 if (i == 0) {
406 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
407 overlap);
408 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
409 boundaries[0]);
410 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
411 boundaries[1]);
412 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
413 boundaries[2]);
414 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
415 boundaries[3]);
416 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
417 }
418 /* Write PDADC values. */
419 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
420 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
421 pdadcs[j + 0] << 0 |
422 pdadcs[j + 1] << 8 |
423 pdadcs[j + 2] << 16 |
424 pdadcs[j + 3] << 24);
425 }
426 AR_WRITE_BARRIER(sc);
427 }
428 }
429
430 Static void
ar9287_set_txpower(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)431 ar9287_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
432 struct ieee80211_channel *extc)
433 {
434 const struct ar9287_eeprom *eep = sc->sc_eep;
435 #ifdef notyet
436 const struct ar9287_modal_eep_header *modal = &eep->modalHeader;
437 #endif
438 uint8_t tpow_cck[4], tpow_ofdm[4];
439 #ifndef IEEE80211_NO_HT
440 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
441 uint8_t tpow_ht20[8], tpow_ht40[8];
442 uint8_t ht40inc;
443 #endif
444 int16_t pwr = 0, power[ATHN_POWER_COUNT];
445 int i;
446
447 ar9287_set_power_calib(sc, c);
448
449 #ifdef notyet
450 /* Compute transmit power reduction due to antenna gain. */
451 uint16_t max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);
452 /* XXX */
453 #endif
454
455 /*
456 * Reduce scaled power by number of active chains to get per-chain
457 * transmit power level.
458 */
459 if (sc->sc_ntxchains == 2)
460 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;
461 if (pwr < 0)
462 pwr = 0;
463
464 /* Get CCK target powers. */
465 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
466 AR9287_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
467
468 /* Get OFDM target powers. */
469 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
470 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
471
472 #ifndef IEEE80211_NO_HT
473 /* Get HT-20 target powers. */
474 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20, eep->calTargetPower2GHT20,
475 AR9287_NUM_2G_20_TARGET_POWERS, tpow_ht20);
476
477 if (extc != NULL) {
478 /* Get HT-40 target powers. */
479 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
480 eep->calTargetPower2GHT40, AR9287_NUM_2G_40_TARGET_POWERS,
481 tpow_ht40);
482
483 /* Get secondary channel CCK target powers. */
484 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
485 eep->calTargetPowerCck, AR9287_NUM_2G_CCK_TARGET_POWERS,
486 tpow_cck_ext);
487
488 /* Get secondary channel OFDM target powers. */
489 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
490 eep->calTargetPower2G, AR9287_NUM_2G_20_TARGET_POWERS,
491 tpow_ofdm_ext);
492 }
493 #endif
494
495 memset(power, 0, sizeof(power));
496 /* Shuffle target powers accross transmit rates. */
497 power[ATHN_POWER_OFDM6 ] =
498 power[ATHN_POWER_OFDM9 ] =
499 power[ATHN_POWER_OFDM12 ] =
500 power[ATHN_POWER_OFDM18 ] =
501 power[ATHN_POWER_OFDM24 ] = tpow_ofdm[0];
502 power[ATHN_POWER_OFDM36 ] = tpow_ofdm[1];
503 power[ATHN_POWER_OFDM48 ] = tpow_ofdm[2];
504 power[ATHN_POWER_OFDM54 ] = tpow_ofdm[3];
505 power[ATHN_POWER_XR ] = tpow_ofdm[0];
506 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0];
507 power[ATHN_POWER_CCK2_LP ] =
508 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1];
509 power[ATHN_POWER_CCK55_LP] =
510 power[ATHN_POWER_CCK55_SP] = tpow_cck[2];
511 power[ATHN_POWER_CCK11_LP] =
512 power[ATHN_POWER_CCK11_SP] = tpow_cck[3];
513 #ifndef IEEE80211_NO_HT
514 for (i = 0; i < nitems(tpow_ht20); i++)
515 power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
516 if (extc != NULL) {
517 /* Correct PAR difference between HT40 and HT20/Legacy. */
518 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
519 ht40inc = modal->ht40PowerIncForPdadc;
520 else
521 ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
522 for (i = 0; i < nitems(tpow_ht40); i++)
523 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
524 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
525 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0];
526 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
527 if (IEEE80211_IS_CHAN_2GHZ(c))
528 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0];
529 }
530 #endif
531
532 for (i = 0; i < ATHN_POWER_COUNT; i++) {
533 power[i] -= AR_PWR_TABLE_OFFSET_DB * 2; /* In half dB. */
534 if (power[i] > AR_MAX_RATE_POWER)
535 power[i] = AR_MAX_RATE_POWER;
536 }
537 /* Commit transmit power values to hardware. */
538 ar5008_write_txpower(sc, power);
539 }
540
541 Static void
ar9287_olpc_init(struct athn_softc * sc)542 ar9287_olpc_init(struct athn_softc *sc)
543 {
544 uint32_t reg;
545
546 AR_SETBITS(sc, AR_PHY_TX_PWRCTRL9, AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
547
548 reg = AR_READ(sc, AR9287_AN_TXPC0);
549 reg = RW(reg, AR9287_AN_TXPC0_TXPCMODE,
550 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
551 AR_WRITE(sc, AR9287_AN_TXPC0, reg);
552 AR_WRITE_BARRIER(sc);
553 DELAY(100);
554 }
555
556 Static void
ar9287_olpc_temp_compensation(struct athn_softc * sc)557 ar9287_olpc_temp_compensation(struct athn_softc *sc)
558 {
559 const struct ar9287_eeprom *eep = sc->sc_eep;
560 int8_t pdadc, slope, tcomp;
561 uint32_t reg;
562
563 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
564 pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
565 DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
566
567 if (sc->sc_pdadc == 0 || pdadc == 0)
568 return; /* No frames transmitted yet. */
569
570 /* Compute Tx gain temperature compensation. */
571 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
572 slope = eep->baseEepHeader.tempSensSlope;
573 else
574 slope = 0;
575 if (slope != 0) /* Prevents division by zero. */
576 tcomp = ((pdadc - sc->sc_pdadc) * 4) / slope;
577 else
578 tcomp = 0;
579 DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
580
581 /* Write compensation value for both Tx chains. */
582 reg = AR_READ(sc, AR_PHY_CH0_TX_PWRCTRL11);
583 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
584 AR_WRITE(sc, AR_PHY_CH0_TX_PWRCTRL11, reg);
585
586 reg = AR_READ(sc, AR_PHY_CH1_TX_PWRCTRL11);
587 reg = RW(reg, AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, tcomp);
588 AR_WRITE(sc, AR_PHY_CH1_TX_PWRCTRL11, reg);
589 AR_WRITE_BARRIER(sc);
590 }
591
592 PUBLIC void
ar9287_1_3_enable_async_fifo(struct athn_softc * sc)593 ar9287_1_3_enable_async_fifo(struct athn_softc *sc)
594 {
595
596 /* Enable ASYNC FIFO. */
597 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
598 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
599 AR_SETBITS(sc, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
600 AR_CLRBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
601 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
602 AR_SETBITS(sc, AR_MAC_PCU_ASYNC_FIFO_REG3,
603 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
604 AR_WRITE_BARRIER(sc);
605 }
606
607 PUBLIC void
ar9287_1_3_setup_async_fifo(struct athn_softc * sc)608 ar9287_1_3_setup_async_fifo(struct athn_softc *sc)
609 {
610 uint32_t reg;
611
612 /*
613 * MAC runs at 117MHz (instead of 88/44MHz) when ASYNC FIFO is
614 * enabled, so the following counters have to be changed.
615 */
616 AR_WRITE(sc, AR_D_GBL_IFS_SIFS, AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
617 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
618 AR_WRITE(sc, AR_D_GBL_IFS_EIFS, AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
619
620 AR_WRITE(sc, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
621 AR_WRITE(sc, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
622
623 AR_SETBITS(sc, AR_MAC_PCU_LOGIC_ANALYZER,
624 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
625
626 reg = AR_READ(sc, AR_AHB_MODE);
627 reg = RW(reg, AR_AHB_CUSTOM_BURST, AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
628 AR_WRITE(sc, AR_AHB_MODE, reg);
629
630 AR_SETBITS(sc, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
631 AR_WRITE_BARRIER(sc);
632 }
633