1 /* $NetBSD: arn5416.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $ */
2 /* $OpenBSD: ar5416.c,v 1.12 2012/06/10 21:23:36 kettenis Exp $ */
3
4 /*-
5 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6 * Copyright (c) 2008-2009 Atheros Communications Inc.
7 *
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21 /*
22 * Driver for Atheros 802.11a/g/n chipsets.
23 * Routines for AR5416, AR5418 and AR9160 chipsets.
24 */
25
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: arn5416.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $");
28
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/mbuf.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/queue.h>
36 #include <sys/callout.h>
37 #include <sys/conf.h>
38 #include <sys/device.h>
39
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/intr.h>
43
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_arp.h>
47 #include <net/if_dl.h>
48 #include <net/if_ether.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51
52 #include <netinet/in.h>
53 #include <netinet/in_systm.h>
54 #include <netinet/in_var.h>
55 #include <netinet/ip.h>
56
57 #include <net80211/ieee80211_var.h>
58 #include <net80211/ieee80211_amrr.h>
59 #include <net80211/ieee80211_radiotap.h>
60
61 #include <dev/ic/athnreg.h>
62 #include <dev/ic/athnvar.h>
63
64 #include <dev/ic/arn5008reg.h>
65 #include <dev/ic/arn5008.h>
66 #include <dev/ic/arn5416reg.h>
67 #include <dev/ic/arn5416.h>
68 #include <dev/ic/arn9280.h>
69
70 #define Static static
71
72 Static void ar5416_force_bias(struct athn_softc *,
73 struct ieee80211_channel *);
74 Static void ar5416_get_pdadcs(struct athn_softc *,
75 struct ieee80211_channel *, int, int, uint8_t, uint8_t *,
76 uint8_t *);
77 Static void ar5416_init_from_rom(struct athn_softc *,
78 struct ieee80211_channel *, struct ieee80211_channel *);
79 Static uint8_t ar5416_reverse_bits(uint8_t, int);
80 Static void ar5416_rw_bank6tpc(struct athn_softc *,
81 struct ieee80211_channel *, uint32_t *);
82 Static void ar5416_rw_rfbits(uint32_t *, int, int, uint32_t, int);
83 Static void ar5416_set_power_calib(struct athn_softc *,
84 struct ieee80211_channel *);
85 Static int ar5416_set_synth(struct athn_softc *,
86 struct ieee80211_channel *, struct ieee80211_channel *);
87 Static void ar5416_setup(struct athn_softc *);
88 Static void ar5416_spur_mitigate(struct athn_softc *,
89 struct ieee80211_channel *, struct ieee80211_channel *);
90 Static void ar9160_rw_addac(struct athn_softc *,
91 struct ieee80211_channel *, uint32_t *);
92
93 PUBLIC int
ar5416_attach(struct athn_softc * sc)94 ar5416_attach(struct athn_softc *sc)
95 {
96 sc->sc_eep_base = AR5416_EEP_START_LOC;
97 sc->sc_eep_size = sizeof(struct ar5416_eeprom);
98 sc->sc_def_nf = AR5416_PHY_CCA_MAX_GOOD_VALUE;
99 sc->sc_ngpiopins = 14;
100 sc->sc_led_pin = 1;
101 sc->sc_workaround = AR5416_WA_DEFAULT;
102 sc->sc_ops.setup = ar5416_setup;
103 sc->sc_ops.swap_rom = ar5416_swap_rom;
104 sc->sc_ops.init_from_rom = ar5416_init_from_rom;
105 sc->sc_ops.set_txpower = ar5416_set_txpower;
106 sc->sc_ops.set_synth = ar5416_set_synth;
107 sc->sc_ops.spur_mitigate = ar5416_spur_mitigate;
108 sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
109 if (AR_SREV_9160_10_OR_LATER(sc))
110 sc->sc_ini = &ar9160_ini;
111 else
112 sc->sc_ini = &ar5416_ini;
113 sc->sc_serdes = &ar5416_serdes;
114
115 return ar5008_attach(sc);
116 }
117
118 Static void
ar5416_setup(struct athn_softc * sc)119 ar5416_setup(struct athn_softc *sc)
120 {
121 /* Select ADDAC programming. */
122 if (AR_SREV_9160_11(sc))
123 sc->sc_addac = &ar9160_1_1_addac;
124 else if (AR_SREV_9160_10_OR_LATER(sc))
125 sc->sc_addac = &ar9160_1_0_addac;
126 else if (AR_SREV_5416_22_OR_LATER(sc))
127 sc->sc_addac = &ar5416_2_2_addac;
128 else
129 sc->sc_addac = &ar5416_2_1_addac;
130 }
131
132 PUBLIC void
ar5416_swap_rom(struct athn_softc * sc)133 ar5416_swap_rom(struct athn_softc *sc)
134 {
135 struct ar5416_eeprom *eep = sc->sc_eep;
136 struct ar5416_modal_eep_header *modal;
137 int i, j;
138
139 for (i = 0; i < 2; i++) { /* Dual-band. */
140 modal = &eep->modalHeader[i];
141
142 modal->antCtrlCommon = bswap32(modal->antCtrlCommon);
143 for (j = 0; j < AR5416_MAX_CHAINS; j++) {
144 modal->antCtrlChain[j] =
145 bswap32(modal->antCtrlChain[j]);
146 }
147 for (j = 0; j < AR_EEPROM_MODAL_SPURS; j++) {
148 modal->spurChans[j].spurChan =
149 bswap16(modal->spurChans[j].spurChan);
150 }
151 }
152 }
153
154 PUBLIC const struct ar_spur_chan *
ar5416_get_spur_chans(struct athn_softc * sc,int is2ghz)155 ar5416_get_spur_chans(struct athn_softc *sc, int is2ghz)
156 {
157 const struct ar5416_eeprom *eep = sc->sc_eep;
158
159 return eep->modalHeader[is2ghz].spurChans;
160 }
161
162 Static int
ar5416_set_synth(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)163 ar5416_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
164 struct ieee80211_channel *extc)
165 {
166 uint32_t phy, reg;
167 uint32_t freq = c->ic_freq;
168 uint8_t chansel;
169
170 phy = 0;
171 if (IEEE80211_IS_CHAN_2GHZ(c)) {
172 if (((freq - 2192) % 5) == 0) {
173 chansel = ((freq - 672) * 2 - 3040) / 10;
174 }
175 else if (((freq - 2224) % 5) == 0) {
176 chansel = ((freq - 704) * 2 - 3040) / 10;
177 phy |= AR5416_BMODE_SYNTH;
178 }
179 else
180 return EINVAL;
181 chansel <<= 2;
182
183 reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
184 if (freq == 2484) /* Channel 14. */
185 reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
186 else
187 reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
188 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
189
190 /* Fix for orientation sensitivity issue. */
191 if (AR_SREV_5416(sc))
192 ar5416_force_bias(sc, c);
193 }
194 else {
195 if (freq >= 5120 && (freq % 20) == 0) {
196 chansel = (freq - 4800) / 20;
197 chansel <<= 2;
198 phy |= SM(AR5416_AMODE_REFSEL, 2);
199 }
200 else if ((freq % 10) == 0) {
201 chansel = (freq - 4800) / 10;
202 chansel <<= 1;
203 if (AR_SREV_9160_10_OR_LATER(sc))
204 phy |= SM(AR5416_AMODE_REFSEL, 1);
205 else
206 phy |= SM(AR5416_AMODE_REFSEL, 2);
207 }
208 else if ((freq % 5) == 0) {
209 chansel = (freq - 4800) / 5;
210 phy |= SM(AR5416_AMODE_REFSEL, 2);
211 }
212 else
213 return EINVAL;
214 }
215 chansel = ar5416_reverse_bits(chansel, 8);
216 phy |= chansel << 8 | 1 << 5 | 1;
217 DPRINTFN(DBG_RF, sc, "AR_PHY(0x37)=0x%08x\n", phy);
218 AR_WRITE(sc, AR_PHY(0x37), phy);
219 return 0;
220 }
221
222 Static void
ar5416_init_from_rom(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)223 ar5416_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
224 struct ieee80211_channel *extc)
225 {
226 static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
227 const struct ar5416_eeprom *eep = sc->sc_eep;
228 const struct ar5416_modal_eep_header *modal;
229 uint32_t reg, offset;
230 uint8_t txRxAtten;
231 int i;
232
233 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
234
235 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
236
237 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
238 if (AR_SREV_5416_20_OR_LATER(sc) &&
239 (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5))
240 offset = chainoffset[i];
241 else
242 offset = i * 0x1000;
243
244 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
245 modal->antCtrlChain[i]);
246
247 reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
248 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
249 modal->iqCalICh[i]);
250 reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
251 modal->iqCalQCh[i]);
252 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
253
254 if (i > 0 && !AR_SREV_5416_20_OR_LATER(sc))
255 continue;
256
257 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
258 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
259 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_MARGIN,
260 modal->bswMargin[i]);
261 reg = RW(reg, AR_PHY_GAIN_2GHZ_BSW_ATTEN,
262 modal->bswAtten[i]);
263 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
264 }
265 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
266 txRxAtten = modal->txRxAttenCh[i];
267 else /* Workaround for ROM versions < 14.3. */
268 txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
269 reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
270 reg = RW(reg, AR_PHY_RXGAIN_TXRX_ATTEN, txRxAtten);
271 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
272
273 reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
274 reg = RW(reg, AR_PHY_GAIN_2GHZ_RXTX_MARGIN,
275 modal->rxTxMarginCh[i]);
276 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
277 }
278 reg = AR_READ(sc, AR_PHY_SETTLING);
279 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
280 AR_WRITE(sc, AR_PHY_SETTLING, reg);
281
282 reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
283 reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
284 reg = RW(reg, AR_PHY_DESIRED_SZ_PGA, modal->pgaDesiredSize);
285 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
286
287 reg = SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
288 reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
289 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
290 reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
291 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
292
293 reg = AR_READ(sc, AR_PHY_RF_CTL3);
294 reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
295 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
296
297 reg = AR_READ(sc, AR_PHY_CCA(0));
298 reg = RW(reg, AR_PHY_CCA_THRESH62, modal->thresh62);
299 AR_WRITE(sc, AR_PHY_CCA(0), reg);
300
301 reg = AR_READ(sc, AR_PHY_EXT_CCA(0));
302 reg = RW(reg, AR_PHY_EXT_CCA_THRESH62, modal->thresh62);
303 AR_WRITE(sc, AR_PHY_EXT_CCA(0), reg);
304
305 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
306 reg = AR_READ(sc, AR_PHY_RF_CTL2);
307 reg = RW(reg, AR_PHY_TX_END_DATA_START,
308 modal->txFrameToDataStart);
309 reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
310 AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
311 }
312 #ifndef IEEE80211_NO_HT
313 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
314 /* Overwrite switch settling with HT-40 value. */
315 reg = AR_READ(sc, AR_PHY_SETTLING);
316 reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
317 AR_WRITE(sc, AR_PHY_SETTLING, reg);
318 }
319 #endif
320 }
321
322 PUBLIC int
ar5416_init_calib(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)323 ar5416_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
324 struct ieee80211_channel *extc)
325 {
326 int ntries;
327
328 if (AR_SREV_9280_10_OR_LATER(sc)) {
329 /* XXX Linux tests AR9287?! */
330 AR_CLRBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
331 AR_SETBITS(sc, AR_PHY_AGC_CONTROL,
332 AR_PHY_AGC_CONTROL_FLTR_CAL);
333 }
334 /* Calibrate the AGC. */
335 AR_SETBITS(sc, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
336 /* Poll for offset calibration completion. */
337 for (ntries = 0; ntries < 10000; ntries++) {
338 if (!(AR_READ(sc, AR_PHY_AGC_CONTROL) &
339 AR_PHY_AGC_CONTROL_CAL))
340 break;
341 DELAY(10);
342 }
343 if (ntries == 10000)
344 return ETIMEDOUT;
345 if (AR_SREV_9280_10_OR_LATER(sc)) {
346 AR_SETBITS(sc, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
347 AR_CLRBITS(sc, AR_PHY_AGC_CONTROL,
348 AR_PHY_AGC_CONTROL_FLTR_CAL);
349 }
350 return 0;
351 }
352
353 Static void
ar5416_get_pdadcs(struct athn_softc * sc,struct ieee80211_channel * c,int chain,int nxpdgains,uint8_t overlap,uint8_t * boundaries,uint8_t * pdadcs)354 ar5416_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
355 int chain, int nxpdgains, uint8_t overlap, uint8_t *boundaries,
356 uint8_t *pdadcs)
357 {
358 const struct ar5416_eeprom *eep = sc->sc_eep;
359 const struct ar5416_cal_data_per_freq *pierdata;
360 const uint8_t *pierfreq;
361 struct athn_pier lopier, hipier;
362 int16_t delta;
363 uint8_t fbin, pwroff;
364 int i, lo, hi, npiers;
365
366 if (IEEE80211_IS_CHAN_2GHZ(c)) {
367 pierfreq = eep->calFreqPier2G;
368 pierdata = eep->calPierData2G[chain];
369 npiers = AR5416_NUM_2G_CAL_PIERS;
370 }
371 else {
372 pierfreq = eep->calFreqPier5G;
373 pierdata = eep->calPierData5G[chain];
374 npiers = AR5416_NUM_5G_CAL_PIERS;
375 }
376 /* Find channel in ROM pier table. */
377 fbin = athn_chan2fbin(c);
378 athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
379
380 lopier.fbin = pierfreq[lo];
381 hipier.fbin = pierfreq[hi];
382 for (i = 0; i < nxpdgains; i++) {
383 lopier.pwr[i] = pierdata[lo].pwrPdg[i];
384 lopier.vpd[i] = pierdata[lo].vpdPdg[i];
385 hipier.pwr[i] = pierdata[lo].pwrPdg[i];
386 hipier.vpd[i] = pierdata[lo].vpdPdg[i];
387 }
388 ar5008_get_pdadcs(sc, fbin, &lopier, &hipier, nxpdgains,
389 AR5416_PD_GAIN_ICEPTS, overlap, boundaries, pdadcs);
390
391 if (!AR_SREV_9280_20_OR_LATER(sc))
392 return;
393
394 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_21)
395 pwroff = eep->baseEepHeader.pwrTableOffset;
396 else
397 pwroff = AR_PWR_TABLE_OFFSET_DB;
398 delta = (pwroff - AR_PWR_TABLE_OFFSET_DB) * 2; /* In half dB. */
399
400 /* Change the original gain boundaries setting. */
401 for (i = 0; i < nxpdgains; i++) {
402 /* XXX Possible overflows? */
403 boundaries[i] -= delta;
404 if (boundaries[i] > AR_MAX_RATE_POWER - overlap)
405 boundaries[i] = AR_MAX_RATE_POWER - overlap;
406 }
407 if (delta != 0) {
408 /* Shift the PDADC table to start at the new offset. */
409 for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
410 pdadcs[i] = pdadcs[MIN(i + delta,
411 AR_NUM_PDADC_VALUES - 1)];
412 }
413 }
414
415 Static void
ar5416_set_power_calib(struct athn_softc * sc,struct ieee80211_channel * c)416 ar5416_set_power_calib(struct athn_softc *sc, struct ieee80211_channel *c)
417 {
418 static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
419 const struct ar5416_eeprom *eep = sc->sc_eep;
420 const struct ar5416_modal_eep_header *modal;
421 uint8_t boundaries[AR_PD_GAINS_IN_MASK];
422 uint8_t pdadcs[AR_NUM_PDADC_VALUES];
423 uint8_t xpdgains[AR5416_NUM_PD_GAINS];
424 uint8_t overlap, txgain;
425 uint32_t reg, offset;
426 int i, j, nxpdgains;
427
428 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
429
430 if (sc->sc_eep_rev < AR_EEP_MINOR_VER_2) {
431 overlap = MS(AR_READ(sc, AR_PHY_TPCRG5),
432 AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
433 }
434 else
435 overlap = modal->pdGainOverlap;
436
437 if ((sc->sc_flags & ATHN_FLAG_OLPC) && IEEE80211_IS_CHAN_2GHZ(c)) {
438 /* XXX not here. */
439 sc->sc_pdadc =
440 ((const struct ar_cal_data_per_freq_olpc *)
441 eep->calPierData2G[0])->vpdPdg[0][0];
442 }
443
444 nxpdgains = 0;
445 memset(xpdgains, 0, sizeof(xpdgains));
446 for (i = AR5416_PD_GAINS_IN_MASK - 1; i >= 0; i--) {
447 if (nxpdgains >= AR5416_NUM_PD_GAINS)
448 break; /* Can't happen. */
449 if (modal->xpdGain & (1 << i))
450 xpdgains[nxpdgains++] = i;
451 }
452 reg = AR_READ(sc, AR_PHY_TPCRG1);
453 reg = RW(reg, AR_PHY_TPCRG1_NUM_PD_GAIN, nxpdgains - 1);
454 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_1, xpdgains[0]);
455 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_2, xpdgains[1]);
456 reg = RW(reg, AR_PHY_TPCRG1_PD_GAIN_3, xpdgains[2]);
457 AR_WRITE(sc, AR_PHY_TPCRG1, reg);
458
459 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
460 if (!(sc->sc_txchainmask & (1 << i)))
461 continue;
462
463 if (AR_SREV_5416_20_OR_LATER(sc) &&
464 (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5))
465 offset = chainoffset[i];
466 else
467 offset = i * 0x1000;
468
469 if (sc->sc_flags & ATHN_FLAG_OLPC) {
470 ar9280_olpc_get_pdadcs(sc, c, i, boundaries,
471 pdadcs, &txgain);
472
473 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_0);
474 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
475 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_0, reg);
476
477 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL6_1);
478 reg = RW(reg, AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
479 AR_WRITE(sc, AR_PHY_TX_PWRCTRL6_1, reg);
480
481 reg = AR_READ(sc, AR_PHY_TX_PWRCTRL7);
482 reg = RW(reg, AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, txgain);
483 AR_WRITE(sc, AR_PHY_TX_PWRCTRL7, reg);
484
485 overlap = 6;
486 }
487 else {
488 ar5416_get_pdadcs(sc, c, i, nxpdgains, overlap,
489 boundaries, pdadcs);
490 }
491 /* Write boundaries. */
492 if (i == 0 || AR_SREV_5416_20_OR_LATER(sc)) {
493 reg = SM(AR_PHY_TPCRG5_PD_GAIN_OVERLAP,
494 overlap);
495 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1,
496 boundaries[0]);
497 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2,
498 boundaries[1]);
499 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3,
500 boundaries[2]);
501 reg |= SM(AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4,
502 boundaries[3]);
503 AR_WRITE(sc, AR_PHY_TPCRG5 + offset, reg);
504 }
505 /* Write PDADC values. */
506 for (j = 0; j < AR_NUM_PDADC_VALUES; j += 4) {
507 AR_WRITE(sc, AR_PHY_PDADC_TBL_BASE + offset + j,
508 pdadcs[j + 0] << 0 |
509 pdadcs[j + 1] << 8 |
510 pdadcs[j + 2] << 16 |
511 pdadcs[j + 3] << 24);
512 }
513 }
514 }
515
516 PUBLIC void
ar5416_set_txpower(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)517 ar5416_set_txpower(struct athn_softc *sc, struct ieee80211_channel *c,
518 struct ieee80211_channel *extc)
519 {
520 const struct ar5416_eeprom *eep = sc->sc_eep;
521 const struct ar5416_modal_eep_header *modal;
522 uint8_t tpow_cck[4], tpow_ofdm[4];
523 #ifndef IEEE80211_NO_HT
524 uint8_t tpow_cck_ext[4], tpow_ofdm_ext[4];
525 uint8_t tpow_ht20[8], tpow_ht40[8];
526 uint8_t ht40inc;
527 #endif
528 int16_t pwr = 0, pwroff, max_ant_gain, power[ATHN_POWER_COUNT];
529 uint8_t cckinc;
530 int i;
531
532 ar5416_set_power_calib(sc, c);
533
534 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
535
536 /* Compute transmit power reduction due to antenna gain. */
537 max_ant_gain = MAX(modal->antennaGainCh[0], modal->antennaGainCh[1]);
538 max_ant_gain = MAX(modal->antennaGainCh[2], max_ant_gain);
539 /* XXX */
540
541 /*
542 * Reduce scaled power by number of active chains to get per-chain
543 * transmit power level.
544 */
545 if (sc->sc_ntxchains == 2)
546 pwr -= AR_PWR_DECREASE_FOR_2_CHAIN;
547 else if (sc->sc_ntxchains == 3)
548 pwr -= AR_PWR_DECREASE_FOR_3_CHAIN;
549 if (pwr < 0)
550 pwr = 0;
551
552 if (IEEE80211_IS_CHAN_2GHZ(c)) {
553 /* Get CCK target powers. */
554 ar5008_get_lg_tpow(sc, c, AR_CTL_11B, eep->calTargetPowerCck,
555 AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck);
556
557 /* Get OFDM target powers. */
558 ar5008_get_lg_tpow(sc, c, AR_CTL_11G, eep->calTargetPower2G,
559 AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm);
560
561 #ifndef IEEE80211_NO_HT
562 /* Get HT-20 target powers. */
563 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT20,
564 eep->calTargetPower2GHT20, AR5416_NUM_2G_20_TARGET_POWERS,
565 tpow_ht20);
566
567 if (extc != NULL) {
568 /* Get HT-40 target powers. */
569 ar5008_get_ht_tpow(sc, c, AR_CTL_2GHT40,
570 eep->calTargetPower2GHT40,
571 AR5416_NUM_2G_40_TARGET_POWERS, tpow_ht40);
572
573 /* Get secondary channel CCK target powers. */
574 ar5008_get_lg_tpow(sc, extc, AR_CTL_11B,
575 eep->calTargetPowerCck,
576 AR5416_NUM_2G_CCK_TARGET_POWERS, tpow_cck_ext);
577
578 /* Get secondary channel OFDM target powers. */
579 ar5008_get_lg_tpow(sc, extc, AR_CTL_11G,
580 eep->calTargetPower2G,
581 AR5416_NUM_2G_20_TARGET_POWERS, tpow_ofdm_ext);
582 }
583 #endif
584 }
585 else {
586 /* Get OFDM target powers. */
587 ar5008_get_lg_tpow(sc, c, AR_CTL_11A, eep->calTargetPower5G,
588 AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm);
589
590 #ifndef IEEE80211_NO_HT
591 /* Get HT-20 target powers. */
592 ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT20,
593 eep->calTargetPower5GHT20, AR5416_NUM_5G_20_TARGET_POWERS,
594 tpow_ht20);
595
596 if (extc != NULL) {
597 /* Get HT-40 target powers. */
598 ar5008_get_ht_tpow(sc, c, AR_CTL_5GHT40,
599 eep->calTargetPower5GHT40,
600 AR5416_NUM_5G_40_TARGET_POWERS, tpow_ht40);
601
602 /* Get secondary channel OFDM target powers. */
603 ar5008_get_lg_tpow(sc, extc, AR_CTL_11A,
604 eep->calTargetPower5G,
605 AR5416_NUM_5G_20_TARGET_POWERS, tpow_ofdm_ext);
606 }
607 #endif
608 }
609
610 /* Compute CCK/OFDM delta. */
611 cckinc = (sc->sc_flags & ATHN_FLAG_OLPC) ? -2 : 0;
612
613 memset(power, 0, sizeof(power));
614 /* Shuffle target powers accross transmit rates. */
615 power[ATHN_POWER_OFDM6 ] =
616 power[ATHN_POWER_OFDM9 ] =
617 power[ATHN_POWER_OFDM12] =
618 power[ATHN_POWER_OFDM18] =
619 power[ATHN_POWER_OFDM24] = tpow_ofdm[0];
620 power[ATHN_POWER_OFDM36] = tpow_ofdm[1];
621 power[ATHN_POWER_OFDM48] = tpow_ofdm[2];
622 power[ATHN_POWER_OFDM54] = tpow_ofdm[3];
623 power[ATHN_POWER_XR ] = tpow_ofdm[0];
624 if (IEEE80211_IS_CHAN_2GHZ(c)) {
625 power[ATHN_POWER_CCK1_LP ] = tpow_cck[0] + cckinc;
626 power[ATHN_POWER_CCK2_LP ] =
627 power[ATHN_POWER_CCK2_SP ] = tpow_cck[1] + cckinc;
628 power[ATHN_POWER_CCK55_LP] =
629 power[ATHN_POWER_CCK55_SP] = tpow_cck[2] + cckinc;
630 power[ATHN_POWER_CCK11_LP] =
631 power[ATHN_POWER_CCK11_SP] = tpow_cck[3] + cckinc;
632 }
633 #ifndef IEEE80211_NO_HT
634 for (i = 0; i < nitems(tpow_ht20); i++)
635 power[ATHN_POWER_HT20(i)] = tpow_ht20[i];
636 if (extc != NULL) {
637 /* Correct PAR difference between HT40 and HT20/Legacy. */
638 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2)
639 ht40inc = modal->ht40PowerIncForPdadc;
640 else
641 ht40inc = AR_HT40_POWER_INC_FOR_PDADC;
642 for (i = 0; i < nitems(tpow_ht40); i++)
643 power[ATHN_POWER_HT40(i)] = tpow_ht40[i] + ht40inc;
644 power[ATHN_POWER_OFDM_DUP] = tpow_ht40[0];
645 power[ATHN_POWER_CCK_DUP ] = tpow_ht40[0] + cckinc;
646 power[ATHN_POWER_OFDM_EXT] = tpow_ofdm_ext[0];
647 if (IEEE80211_IS_CHAN_2GHZ(c))
648 power[ATHN_POWER_CCK_EXT] = tpow_cck_ext[0] + cckinc;
649 }
650 #endif
651
652 if (AR_SREV_9280_10_OR_LATER(sc)) {
653 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_21)
654 pwroff = eep->baseEepHeader.pwrTableOffset;
655 else
656 pwroff = AR_PWR_TABLE_OFFSET_DB;
657 for (i = 0; i < ATHN_POWER_COUNT; i++)
658 power[i] -= pwroff * 2; /* In half dB. */
659 }
660 for (i = 0; i < ATHN_POWER_COUNT; i++) {
661 if (power[i] > AR_MAX_RATE_POWER)
662 power[i] = AR_MAX_RATE_POWER;
663 }
664
665 /* Write transmit power values to hardware. */
666 ar5008_write_txpower(sc, power);
667
668 /*
669 * Write transmit power substraction for dynamic chain changing
670 * and per-packet transmit power.
671 */
672 AR_WRITE(sc, AR_PHY_POWER_TX_SUB,
673 (modal->pwrDecreaseFor3Chain & 0x3f) << 6 |
674 (modal->pwrDecreaseFor2Chain & 0x3f));
675 }
676
677 Static void
ar5416_spur_mitigate(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)678 ar5416_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
679 struct ieee80211_channel *extc)
680 {
681 const struct ar_spur_chan *spurchans;
682 int i, spur, bin, spur_delta_phase, spur_freq_sd;
683
684 spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
685 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
686 spur = spurchans[i].spurChan;
687 if (spur == AR_NO_SPUR)
688 return; /* XXX disable if it was enabled! */
689 spur -= c->ic_freq * 10;
690 /* Verify range +/-9.5MHz */
691 if (abs(spur) < 95)
692 break;
693 }
694 if (i == AR_EEPROM_MODAL_SPURS)
695 return; /* XXX disable if it was enabled! */
696 DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
697
698 AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
699 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
700 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
701 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
702 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
703
704 AR_WRITE(sc, AR_PHY_SPUR_REG,
705 AR_PHY_SPUR_REG_MASK_RATE_CNTL |
706 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
707 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
708 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
709 SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
710
711 spur_delta_phase = (spur * 524288) / 100;
712 if (IEEE80211_IS_CHAN_2GHZ(c))
713 spur_freq_sd = (spur * 2048) / 440;
714 else
715 spur_freq_sd = (spur * 2048) / 400;
716
717 AR_WRITE(sc, AR_PHY_TIMING11,
718 AR_PHY_TIMING11_USE_SPUR_IN_AGC |
719 SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
720 SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
721
722 bin = spur * 32;
723 ar5008_set_viterbi_mask(sc, bin);
724 }
725
726 Static uint8_t
ar5416_reverse_bits(uint8_t v,int nbits)727 ar5416_reverse_bits(uint8_t v, int nbits)
728 {
729 KASSERT(nbits <= 8);
730 v = ((v >> 1) & 0x55) | ((v & 0x55) << 1);
731 v = ((v >> 2) & 0x33) | ((v & 0x33) << 2);
732 v = ((v >> 4) & 0x0f) | ((v & 0x0f) << 4);
733 return v >> (8 - nbits);
734 }
735
736 PUBLIC uint8_t
ar5416_get_rf_rev(struct athn_softc * sc)737 ar5416_get_rf_rev(struct athn_softc *sc)
738 {
739 uint8_t rev, reg;
740 int i;
741
742 /* Allow access to analog chips. */
743 AR_WRITE(sc, AR_PHY(0), 0x00000007);
744
745 AR_WRITE(sc, AR_PHY(0x36), 0x00007058);
746 for (i = 0; i < 8; i++)
747 AR_WRITE(sc, AR_PHY(0x20), 0x00010000);
748 reg = (AR_READ(sc, AR_PHY(256)) >> 24) & 0xff;
749 reg = (reg & 0xf0) >> 4 | (reg & 0x0f) << 4;
750
751 rev = ar5416_reverse_bits(reg, 8);
752 if ((rev & AR_RADIO_SREV_MAJOR) == 0)
753 rev = AR_RAD5133_SREV_MAJOR;
754 return rev;
755 }
756
757 /*
758 * Replace bits "off" to "off+nbits-1" in column "col" with the specified
759 * value.
760 */
761 Static void
ar5416_rw_rfbits(uint32_t * buf,int col,int off,uint32_t val,int nbits)762 ar5416_rw_rfbits(uint32_t *buf, int col, int off, uint32_t val, int nbits)
763 {
764 int idx, bit;
765
766 KASSERT(off >= 1 && col < 4 && nbits <= 32);
767
768 off--; /* Starts at 1. */
769 while (nbits-- > 0) {
770 idx = off / 8;
771 bit = off % 8;
772 buf[idx] &= ~(1 << (bit + col * 8));
773 buf[idx] |= ((val >> nbits) & 1) << (bit + col * 8);
774 off++;
775 }
776 }
777
778 /*
779 * Overwrite db and ob based on ROM settings.
780 */
781 Static void
ar5416_rw_bank6tpc(struct athn_softc * sc,struct ieee80211_channel * c,uint32_t * rwbank6tpc)782 ar5416_rw_bank6tpc(struct athn_softc *sc, struct ieee80211_channel *c,
783 uint32_t *rwbank6tpc)
784 {
785 const struct ar5416_eeprom *eep = sc->sc_eep;
786 const struct ar5416_modal_eep_header *modal;
787
788 if (IEEE80211_IS_CHAN_5GHZ(c)) {
789 modal = &eep->modalHeader[0];
790 /* 5GHz db in column 0, bits [200-202]. */
791 ar5416_rw_rfbits(rwbank6tpc, 0, 200, modal->db, 3);
792 /* 5GHz ob in column 0, bits [203-205]. */
793 ar5416_rw_rfbits(rwbank6tpc, 0, 203, modal->ob, 3);
794 }
795 else {
796 modal = &eep->modalHeader[1];
797 /* 2GHz db in column 0, bits [194-196]. */
798 ar5416_rw_rfbits(rwbank6tpc, 0, 194, modal->db, 3);
799 /* 2GHz ob in column 0, bits [197-199]. */
800 ar5416_rw_rfbits(rwbank6tpc, 0, 197, modal->ob, 3);
801 }
802 }
803
804 /*
805 * Program analog RF.
806 */
807 PUBLIC void
ar5416_rf_reset(struct athn_softc * sc,struct ieee80211_channel * c)808 ar5416_rf_reset(struct athn_softc *sc, struct ieee80211_channel *c)
809 {
810 const uint32_t *bank6tpc;
811 int i;
812
813 /* Bank 0. */
814 AR_WRITE(sc, 0x98b0, 0x1e5795e5);
815 AR_WRITE(sc, 0x98e0, 0x02008020);
816
817 /* Bank 1. */
818 AR_WRITE(sc, 0x98b0, 0x02108421);
819 AR_WRITE(sc, 0x98ec, 0x00000008);
820
821 /* Bank 2. */
822 AR_WRITE(sc, 0x98b0, 0x0e73ff17);
823 AR_WRITE(sc, 0x98e0, 0x00000420);
824
825 /* Bank 3. */
826 if (IEEE80211_IS_CHAN_5GHZ(c))
827 AR_WRITE(sc, 0x98f0, 0x01400018);
828 else
829 AR_WRITE(sc, 0x98f0, 0x01c00018);
830
831 /* Select the Bank 6 TPC values to use. */
832 if (AR_SREV_9160_10_OR_LATER(sc))
833 bank6tpc = ar9160_bank6tpc_vals;
834 else
835 bank6tpc = ar5416_bank6tpc_vals;
836 if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
837 uint32_t *rwbank6tpc = sc->sc_rwbuf;
838
839 /* Copy values from .rodata to writable buffer. */
840 memcpy(rwbank6tpc, bank6tpc, 32 * sizeof(uint32_t));
841 ar5416_rw_bank6tpc(sc, c, rwbank6tpc);
842 bank6tpc = rwbank6tpc;
843 }
844 /* Bank 6 TPC. */
845 for (i = 0; i < 32; i++)
846 AR_WRITE(sc, 0x989c, bank6tpc[i]);
847 if (IEEE80211_IS_CHAN_5GHZ(c))
848 AR_WRITE(sc, 0x98d0, 0x0000000f);
849 else
850 AR_WRITE(sc, 0x98d0, 0x0010000f);
851
852 /* Bank 7. */
853 AR_WRITE(sc, 0x989c, 0x00000500);
854 AR_WRITE(sc, 0x989c, 0x00000800);
855 AR_WRITE(sc, 0x98cc, 0x0000000e);
856 }
857
858 PUBLIC void
ar5416_reset_bb_gain(struct athn_softc * sc,struct ieee80211_channel * c)859 ar5416_reset_bb_gain(struct athn_softc *sc, struct ieee80211_channel *c)
860 {
861 const uint32_t *pvals;
862 int i;
863
864 if (IEEE80211_IS_CHAN_2GHZ(c))
865 pvals = ar5416_bb_rfgain_vals_2g;
866 else
867 pvals = ar5416_bb_rfgain_vals_5g;
868 for (i = 0; i < 64; i++)
869 AR_WRITE(sc, AR_PHY_BB_RFGAIN(i), pvals[i]);
870 }
871
872 /*
873 * Fix orientation sensitivity issue on AR5416/2GHz by increasing
874 * rf_pwd_icsyndiv.
875 */
876 Static void
ar5416_force_bias(struct athn_softc * sc,struct ieee80211_channel * c)877 ar5416_force_bias(struct athn_softc *sc, struct ieee80211_channel *c)
878 {
879 uint32_t *rwbank6 = sc->sc_rwbuf;
880 uint8_t bias;
881 int i;
882
883 KASSERT(IEEE80211_IS_CHAN_2GHZ(c));
884
885 /* Copy values from .rodata to writable buffer. */
886 memcpy(rwbank6, ar5416_bank6_vals, sizeof(ar5416_bank6_vals));
887
888 if (c->ic_freq < 2412)
889 bias = 0;
890 else if (c->ic_freq < 2422)
891 bias = 1;
892 else
893 bias = 2;
894 ar5416_reverse_bits(bias, 3);
895
896 /* Overwrite "rf_pwd_icsyndiv" (column 3, bits [181-183].) */
897 ar5416_rw_rfbits(rwbank6, 3, 181, bias, 3);
898
899 /* Write Bank 6. */
900 for (i = 0; i < 32; i++)
901 AR_WRITE(sc, 0x989c, rwbank6[i]);
902 AR_WRITE(sc, 0x98d0, 0x0010000f);
903 }
904
905 /*
906 * Overwrite XPA bias level based on ROM setting.
907 */
908 Static void
ar9160_rw_addac(struct athn_softc * sc,struct ieee80211_channel * c,uint32_t * addac)909 ar9160_rw_addac(struct athn_softc *sc, struct ieee80211_channel *c,
910 uint32_t *addac)
911 {
912 struct ar5416_eeprom *eep = sc->sc_eep;
913 struct ar5416_modal_eep_header *modal;
914 uint8_t fbin, bias;
915 int i;
916
917 /* XXX xpaBiasLvlFreq values have not been endian-swapped? */
918
919 /* Get the XPA bias level to use for the specified channel. */
920 modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
921 if (modal->xpaBiasLvl == 0xff) {
922 bias = modal->xpaBiasLvlFreq[0] >> 14;
923 fbin = athn_chan2fbin(c);
924 for (i = 1; i < 3; i++) {
925 if (modal->xpaBiasLvlFreq[i] == 0)
926 break;
927 if ((modal->xpaBiasLvlFreq[i] & 0xff) < fbin)
928 break;
929 bias = modal->xpaBiasLvlFreq[i] >> 14;
930 }
931 }
932 else
933 bias = modal->xpaBiasLvl & 0x3;
934
935 bias = ar5416_reverse_bits(bias, 2); /* Put in host bit-order. */
936 DPRINTFN(DBG_RF, sc, "bias level=%d\n", bias);
937 if (IEEE80211_IS_CHAN_2GHZ(c))
938 ar5416_rw_rfbits(addac, 0, 60, bias, 2);
939 else
940 ar5416_rw_rfbits(addac, 0, 55, bias, 2);
941 }
942
943 PUBLIC void
ar5416_reset_addac(struct athn_softc * sc,struct ieee80211_channel * c)944 ar5416_reset_addac(struct athn_softc *sc, struct ieee80211_channel *c)
945 {
946 const struct athn_addac *addac = sc->sc_addac;
947 const uint32_t *pvals;
948 int i;
949
950 if (AR_SREV_9160(sc) && sc->sc_eep_rev >= AR_EEP_MINOR_VER_7) {
951 uint32_t *rwaddac = sc->sc_rwbuf;
952
953 /* Copy values from .rodata to writable buffer. */
954 memcpy(rwaddac, addac->vals, addac->nvals * sizeof(uint32_t));
955 ar9160_rw_addac(sc, c, rwaddac);
956 pvals = rwaddac;
957 }
958 else
959 pvals = addac->vals;
960 for (i = 0; i < addac->nvals; i++)
961 AR_WRITE(sc, 0x989c, pvals[i]);
962 AR_WRITE(sc, 0x98cc, 0); /* Finalize. */
963 }
964