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Searched refs:ISD (Results 1 – 25 of 193) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp62 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
80 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
82 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
83 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
84 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
85 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
86 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
87 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
88 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
89 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
[all …]
HDLegalizeVectorOps.cpp258 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
260 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
261 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
289 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
335 case ISD::MERGE_VALUES: in LegalizeOp()
343 case ISD::STRICT_##DAGN: in LegalizeOp()
346 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP || in LegalizeOp()
347 Op.getOpcode() == ISD::STRICT_UINT_TO_FP) in LegalizeOp()
366 case ISD::ADD: in LegalizeOp()
367 case ISD::SUB: in LegalizeOp()
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HDLegalizeDAG.cpp319 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
334 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, in ExpandConstantFP()
406 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, in ExpandINSERT_VECTOR_ELT()
424 if (!ISD::isNormalStore(ST)) in OptimizeFloatStore()
477 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); in OptimizeFloatStore()
503 switch (TLI.getOperationAction(ISD::STORE, VT)) { in LegalizeStoreOps()
527 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT); in LegalizeStoreOps()
530 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
584 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
596 ISD::SRL, dl, Value.getValueType(), Value, in LegalizeStoreOps()
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HDLegalizeIntegerTypes.cpp55 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
56 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
57 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
58 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
59 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
60 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
61 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
62 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
63 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
64 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
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HDLegalizeVectorTypes.cpp50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
52 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
55 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
56 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
57 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
58 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break; in ScalarizeVectorResult()
59 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
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HDTargetLowering.cpp94 if (Value->getOpcode() != ISD::CopyFromReg) in parametersInCSRMatch()
236 if (isOperationLegalOrCustom(ISD::STORE, NewVT) && in findOptimalMemOpLowering()
240 isOperationLegalOrCustom(ISD::STORE, MVT::f64) && in findOptimalMemOpLowering()
285 ISD::CondCode &CCCode, in softenSetCCOperands()
295 ISD::CondCode &CCCode, in softenSetCCOperands()
311 case ISD::SETEQ: in softenSetCCOperands()
312 case ISD::SETOEQ: in softenSetCCOperands()
317 case ISD::SETNE: in softenSetCCOperands()
318 case ISD::SETUNE: in softenSetCCOperands()
323 case ISD::SETGE: in softenSetCCOperands()
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HDDAGCombiner.cpp247 assert(N->getOpcode() != ISD::DELETED_NODE && in AddToWorklist()
252 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
509 SDValue N2, SDValue N3, ISD::CondCode CC,
513 ISD::CondCode CC);
515 SDValue N2, SDValue N3, ISD::CondCode CC);
520 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
625 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
719 ISD::NodeType ExtType);
818 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
825 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
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HDLegalizeFloatTypes.cpp61 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
62 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
63 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
64 case ISD::ConstantFP: R = SoftenFloatRes_ConstantFP(N); break; in SoftenFloatResult()
65 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
67 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
68 case ISD::STRICT_FMINNUM: in SoftenFloatResult()
69 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
70 case ISD::STRICT_FMAXNUM: in SoftenFloatResult()
71 case ISD::FMAXNUM: R = SoftenFloatRes_FMAXNUM(N); break; in SoftenFloatResult()
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HDSelectionDAG.cpp139 bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) { in isConstantSplatVector()
156 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
158 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllOnes()
161 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
200 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
202 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllZeros()
205 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
237 bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) { in isBuildVectorOfConstantSDNodes()
238 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantSDNodes()
250 bool ISD::isBuildVectorOfConstantFPSDNodes(const SDNode *N) { in isBuildVectorOfConstantFPSDNodes()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
HDX86TargetTransformInfo.cpp182 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
183 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
186 { ISD::FDIV, MVT::f32, 18 }, // divss in getArithmeticInstrCost()
187 { ISD::FDIV, MVT::v4f32, 35 }, // divps in getArithmeticInstrCost()
188 { ISD::FDIV, MVT::f64, 33 }, // divsd in getArithmeticInstrCost()
189 { ISD::FDIV, MVT::v2f64, 65 }, // divpd in getArithmeticInstrCost()
193 if (const auto *Entry = CostTableLookup(GLMCostTable, ISD, in getArithmeticInstrCost()
198 { ISD::MUL, MVT::v4i32, 11 }, // pmulld in getArithmeticInstrCost()
199 { ISD::MUL, MVT::v8i16, 2 }, // pmullw in getArithmeticInstrCost()
200 { ISD::MUL, MVT::v16i8, 14 }, // extend/pmullw/trunc sequence. in getArithmeticInstrCost()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
HDARMTargetTransformInfo.cpp155 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
156 assert(ISD && "Invalid opcode"); in getCastInstrCost()
161 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
162 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
163 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
166 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
167 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
169 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second)) in getCastInstrCost()
182 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
183 {ISD::ZERO_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
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HDARMISelLowering.cpp159 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
162 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
168 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
HDAMDGPUISelLowering.cpp70 setOperationAction(ISD::LOAD, MVT::f32, Promote); in AMDGPUTargetLowering()
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote); in AMDGPUTargetLowering()
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); in AMDGPUTargetLowering()
76 setOperationAction(ISD::LOAD, MVT::v3f32, Promote); in AMDGPUTargetLowering()
77 AddPromotedToType(ISD::LOAD, MVT::v3f32, MVT::v3i32); in AMDGPUTargetLowering()
79 setOperationAction(ISD::LOAD, MVT::v4f32, Promote); in AMDGPUTargetLowering()
80 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32); in AMDGPUTargetLowering()
82 setOperationAction(ISD::LOAD, MVT::v5f32, Promote); in AMDGPUTargetLowering()
83 AddPromotedToType(ISD::LOAD, MVT::v5f32, MVT::v5i32); in AMDGPUTargetLowering()
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HDR600ISelLowering.cpp72 setOperationAction(ISD::LOAD, MVT::i32, Custom); in R600TargetLowering()
73 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); in R600TargetLowering()
74 setOperationAction(ISD::LOAD, MVT::v4i32, Custom); in R600TargetLowering()
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
87 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp62 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
63 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
66 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
67 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
68 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
69 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
70 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
76 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
78 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp465 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) in getSYNC()
466 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) in getSYNC()
467 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) in getSYNC()
468 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) in getSYNC()
469 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) in getSYNC()
470 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) in getSYNC()
471 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) in getSYNC()
472 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) in getSYNC()
473 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) in getSYNC()
474 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) in getSYNC()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
HDAArch64TargetTransformInfo.cpp271 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
272 assert(ISD && "Invalid opcode"); in getCastInstrCost()
302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
303 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
304 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
305 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
310 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
311 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
[all …]
HDAArch64ISelLowering.cpp187 setOperationAction(ISD::SADDSAT, VT, Legal); in AArch64TargetLowering()
188 setOperationAction(ISD::UADDSAT, VT, Legal); in AArch64TargetLowering()
189 setOperationAction(ISD::SSUBSAT, VT, Legal); in AArch64TargetLowering()
190 setOperationAction(ISD::USUBSAT, VT, Legal); in AArch64TargetLowering()
191 setOperationAction(ISD::SMAX, VT, Legal); in AArch64TargetLowering()
192 setOperationAction(ISD::UMAX, VT, Legal); in AArch64TargetLowering()
193 setOperationAction(ISD::SMIN, VT, Legal); in AArch64TargetLowering()
194 setOperationAction(ISD::UMIN, VT, Legal); in AArch64TargetLowering()
200 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Legal); in AArch64TargetLowering()
207 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
HDSelectionDAGNodes.h83 namespace ISD {
667 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
675 return NodeType >= ISD::FIRST_TARGET_STRICTFP_OPCODE;
682 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
686 bool isUndef() const { return NodeType == ISD::UNDEF; }
694 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
695 NodeType == ISD::INTRINSIC_VOID) &&
705 case ISD::STRICT_##DAGN:
895 if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
1027 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
HDAVRISelLowering.cpp50 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); in AVRTargetLowering()
51 setOperationAction(ISD::BlockAddress, MVT::i16, Custom); in AVRTargetLowering()
53 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in AVRTargetLowering()
54 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AVRTargetLowering()
55 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand); in AVRTargetLowering()
56 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand); in AVRTargetLowering()
59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in AVRTargetLowering()
68 setOperationAction(ISD::ADDC, VT, Legal); in AVRTargetLowering()
69 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
70 setOperationAction(ISD::ADDE, VT, Legal); in AVRTargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
HDWebAssemblyISelLowering.cpp72 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
73 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
74 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
75 setOperationAction(ISD::BlockAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
76 setOperationAction(ISD::BRIND, MVT::Other, Custom); in WebAssemblyTargetLowering()
80 setOperationAction(ISD::VASTART, MVT::Other, Custom); in WebAssemblyTargetLowering()
81 setOperationAction(ISD::VAARG, MVT::Other, Expand); in WebAssemblyTargetLowering()
82 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in WebAssemblyTargetLowering()
83 setOperationAction(ISD::VAEND, MVT::Other, Expand); in WebAssemblyTargetLowering()
87 setOperationAction(ISD::ConstantFP, T, Legal); in WebAssemblyTargetLowering()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp43 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
56 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
84 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
108 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
153 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
199 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
210 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
295 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
HDLanaiISelLowering.cpp85 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in LanaiTargetLowering()
86 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in LanaiTargetLowering()
87 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in LanaiTargetLowering()
88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
89 setOperationAction(ISD::SELECT, MVT::i32, Expand); in LanaiTargetLowering()
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in LanaiTargetLowering()
92 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in LanaiTargetLowering()
93 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in LanaiTargetLowering()
94 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in LanaiTargetLowering()
95 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in LanaiTargetLowering()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp134 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_SkipOdd()
167 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
179 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
195 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
320 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
376 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
378 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
437 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
453 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
456 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
[all …]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
92 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in MipsSETargetLowering()
95 setOperationAction(ISD::ADD, VecTys[i], Legal); in MipsSETargetLowering()
96 setOperationAction(ISD::SUB, VecTys[i], Legal); in MipsSETargetLowering()
97 setOperationAction(ISD::LOAD, VecTys[i], Legal); in MipsSETargetLowering()
98 setOperationAction(ISD::STORE, VecTys[i], Legal); in MipsSETargetLowering()
99 setOperationAction(ISD::BITCAST, VecTys[i], Legal); in MipsSETargetLowering()
102 setTargetDAGCombine(ISD::SHL); in MipsSETargetLowering()
[all …]

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