Lines Matching refs:ISD
72 setOperationAction(ISD::GlobalAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
73 setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom); in WebAssemblyTargetLowering()
74 setOperationAction(ISD::JumpTable, MVTPtr, Custom); in WebAssemblyTargetLowering()
75 setOperationAction(ISD::BlockAddress, MVTPtr, Custom); in WebAssemblyTargetLowering()
76 setOperationAction(ISD::BRIND, MVT::Other, Custom); in WebAssemblyTargetLowering()
80 setOperationAction(ISD::VASTART, MVT::Other, Custom); in WebAssemblyTargetLowering()
81 setOperationAction(ISD::VAARG, MVT::Other, Expand); in WebAssemblyTargetLowering()
82 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in WebAssemblyTargetLowering()
83 setOperationAction(ISD::VAEND, MVT::Other, Expand); in WebAssemblyTargetLowering()
87 setOperationAction(ISD::ConstantFP, T, Legal); in WebAssemblyTargetLowering()
89 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
90 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
94 {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
99 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
102 setOperationAction(ISD::FMINIMUM, T, Legal); in WebAssemblyTargetLowering()
103 setOperationAction(ISD::FMAXIMUM, T, Legal); in WebAssemblyTargetLowering()
105 setOperationAction(ISD::FP16_TO_FP, T, Expand); in WebAssemblyTargetLowering()
106 setOperationAction(ISD::FP_TO_FP16, T, Expand); in WebAssemblyTargetLowering()
107 setLoadExtAction(ISD::EXTLOAD, T, MVT::f16, Expand); in WebAssemblyTargetLowering()
113 {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, in WebAssemblyTargetLowering()
114 ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, in WebAssemblyTargetLowering()
115 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
128 for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) in WebAssemblyTargetLowering()
134 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in WebAssemblyTargetLowering()
137 setOperationAction(ISD::BUILD_VECTOR, T, Custom); in WebAssemblyTargetLowering()
141 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
144 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
147 for (auto Op : {ISD::SHL, ISD::SRA, ISD::SRL}) { in WebAssemblyTargetLowering()
155 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) { in WebAssemblyTargetLowering()
164 setOperationAction(ISD::MUL, MVT::v2i64, Expand); in WebAssemblyTargetLowering()
167 for (auto Op : {ISD::VSELECT, ISD::SELECT_CC, ISD::SELECT}) { in WebAssemblyTargetLowering()
176 for (auto Op : {ISD::CTLZ, ISD::CTTZ, ISD::CTPOP, ISD::SDIV, ISD::UDIV, in WebAssemblyTargetLowering()
177 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) { in WebAssemblyTargetLowering()
186 for (auto Op : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in WebAssemblyTargetLowering()
192 for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, in WebAssemblyTargetLowering()
193 ISD::FCOPYSIGN, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, in WebAssemblyTargetLowering()
194 ISD::FEXP, ISD::FEXP2, ISD::FRINT}) { in WebAssemblyTargetLowering()
202 for (unsigned CC = 0; CC < ISD::SETCC_INVALID; ++CC) in WebAssemblyTargetLowering()
203 setCondCodeAction(static_cast<ISD::CondCode>(CC), MVT::v2i64, Custom); in WebAssemblyTargetLowering()
207 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
208 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in WebAssemblyTargetLowering()
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in WebAssemblyTargetLowering()
219 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Action); in WebAssemblyTargetLowering()
222 setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand); in WebAssemblyTargetLowering()
225 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in WebAssemblyTargetLowering()
226 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in WebAssemblyTargetLowering()
227 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand); in WebAssemblyTargetLowering()
229 setOperationAction(ISD::FrameIndex, MVT::i32, Custom); in WebAssemblyTargetLowering()
230 setOperationAction(ISD::CopyToReg, MVT::Other, Custom); in WebAssemblyTargetLowering()
234 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC}) in WebAssemblyTargetLowering()
238 setOperationAction(ISD::BR_JT, MVT::Other, Custom); in WebAssemblyTargetLowering()
245 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in WebAssemblyTargetLowering()
248 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
256 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
263 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in WebAssemblyTargetLowering()
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in WebAssemblyTargetLowering()
275 setOperationAction(ISD::TRAP, MVT::Other, Legal); in WebAssemblyTargetLowering()
278 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in WebAssemblyTargetLowering()
279 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in WebAssemblyTargetLowering()
592 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
606 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
614 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
704 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
708 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
722 const ISD::OutputArg &Out = Outs[I]; in LowerCall()
761 const ISD::OutputArg &Out = Outs[I]; in LowerCall()
793 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode, in LowerCall()
800 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains); in LowerCall()
805 if (Callee->getOpcode() == ISD::GlobalAddress) { in LowerCall()
869 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
877 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
890 for (const ISD::OutputArg &Out : Outs) { in LowerReturn()
907 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
919 for (const ISD::InputArg &In : Ins) { in LowerFormalArguments()
972 case ISD::SIGN_EXTEND_INREG: in ReplaceNodeResults()
995 case ISD::FrameIndex: in LowerOperation()
997 case ISD::GlobalAddress: in LowerOperation()
999 case ISD::ExternalSymbol: in LowerOperation()
1001 case ISD::JumpTable: in LowerOperation()
1003 case ISD::BR_JT: in LowerOperation()
1005 case ISD::VASTART: in LowerOperation()
1007 case ISD::BlockAddress: in LowerOperation()
1008 case ISD::BRIND: in LowerOperation()
1011 case ISD::RETURNADDR: in LowerOperation()
1013 case ISD::FRAMEADDR: in LowerOperation()
1015 case ISD::CopyToReg: in LowerOperation()
1017 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1018 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
1020 case ISD::INTRINSIC_VOID: in LowerOperation()
1021 case ISD::INTRINSIC_WO_CHAIN: in LowerOperation()
1022 case ISD::INTRINSIC_W_CHAIN: in LowerOperation()
1024 case ISD::SIGN_EXTEND_INREG: in LowerOperation()
1026 case ISD::BUILD_VECTOR: in LowerOperation()
1028 case ISD::VECTOR_SHUFFLE: in LowerOperation()
1030 case ISD::SETCC: in LowerOperation()
1032 case ISD::SHL: in LowerOperation()
1033 case ISD::SRA: in LowerOperation()
1034 case ISD::SRL: in LowerOperation()
1141 return DAG.getNode(ISD::ADD, DL, VT, BaseAddr, SymAddr); in LowerGlobalAddress()
1220 case ISD::INTRINSIC_VOID: in LowerIntrinsic()
1221 case ISD::INTRINSIC_W_CHAIN: in LowerIntrinsic()
1224 case ISD::INTRINSIC_WO_CHAIN: in LowerIntrinsic()
1279 if (Op.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerSIGN_EXTEND_INREG()
1299 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1301 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), in LowerSIGN_EXTEND_INREG()
1327 return V.getOpcode() == ISD::Constant || V.getOpcode() == ISD::ConstantFP; in LowerBUILD_VECTOR()
1337 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1341 if (IndexExt->getOpcode() != ISD::SIGN_EXTEND_INREG) in LowerBUILD_VECTOR()
1344 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1349 Index->getOperand(1)->getOpcode() != ISD::Constant || in LowerBUILD_VECTOR()
1463 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()
1512 return DAG.getNode(ISD::SELECT_CC, DL, MVT::i64, LHS[I], RHS[I], in LowerSETCC()
1542 ISD::AND, // mask opcode in unrollVectorShift()
1579 case ISD::SHL: in LowerShift()
1582 case ISD::SRA: in LowerShift()
1585 case ISD::SRL: in LowerShift()