Lines Matching refs:ISD
134 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_SkipOdd()
167 SDValue Chain, ISD::ArgFlagsTy Flags, in CreateCopyOfByValArgument()
179 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
195 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
320 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerCallResult()
376 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
378 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall()
437 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall()
453 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
456 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
459 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
467 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr); in LowerCall()
500 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall()
600 SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, in getPostIndexedAddressParts()
616 if (Op->getOpcode() != ISD::ADD) in getPostIndexedAddressParts()
622 AM = ISD::POST_INC; in getPostIndexedAddressParts()
635 if ((Op.getOpcode() != ISD::INLINEASM && in LowerINLINEASM()
636 Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR()) in LowerINLINEASM()
747 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments()
774 ISD::ArgFlagsTy Flags = Ins[i].Flags; in LowerFormalArguments()
801 SDValue T = DAG.getNode(ISD::AND, dl, RegVT, in LowerFormalArguments()
804 ISD::SETNE); in LowerFormalArguments()
868 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
891 case ISD::TRUNCATE: { in LowerSETCC()
894 if (Op.getOpcode() != ISD::AssertSext) in LowerSETCC()
904 case ISD::LOAD: in LowerSETCC()
1036 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), in LowerRETURNADDR()
1190 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym); in LowerToTLSInitialExecModel()
1200 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset); in LowerToTLSInitialExecModel()
1222 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym); in LowerToTLSLocalExecModel()
1244 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym); in LowerToTLSGeneralDynamicModel()
1346 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in HexagonTargetLowering()
1347 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in HexagonTargetLowering()
1348 setOperationAction(ISD::TRAP, MVT::Other, Legal); in HexagonTargetLowering()
1349 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in HexagonTargetLowering()
1350 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in HexagonTargetLowering()
1351 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
1352 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in HexagonTargetLowering()
1353 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in HexagonTargetLowering()
1354 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in HexagonTargetLowering()
1355 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); in HexagonTargetLowering()
1356 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in HexagonTargetLowering()
1357 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
1358 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); in HexagonTargetLowering()
1359 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); in HexagonTargetLowering()
1360 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in HexagonTargetLowering()
1361 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in HexagonTargetLowering()
1364 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in HexagonTargetLowering()
1365 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); in HexagonTargetLowering()
1366 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in HexagonTargetLowering()
1369 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1370 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1371 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1372 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1375 setOperationAction(ISD::VASTART, MVT::Other, Custom); in HexagonTargetLowering()
1376 setOperationAction(ISD::VAEND, MVT::Other, Expand); in HexagonTargetLowering()
1377 setOperationAction(ISD::VAARG, MVT::Other, Expand); in HexagonTargetLowering()
1378 setOperationAction(ISD::VACOPY, MVT::Other, Expand); in HexagonTargetLowering()
1380 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in HexagonTargetLowering()
1381 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in HexagonTargetLowering()
1382 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in HexagonTargetLowering()
1388 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in HexagonTargetLowering()
1390 setOperationAction(ISD::ABS, MVT::i32, Legal); in HexagonTargetLowering()
1391 setOperationAction(ISD::ABS, MVT::i64, Legal); in HexagonTargetLowering()
1396 setOperationAction(ISD::UADDO, VT, Custom); in HexagonTargetLowering()
1397 setOperationAction(ISD::USUBO, VT, Custom); in HexagonTargetLowering()
1398 setOperationAction(ISD::SADDO, VT, Expand); in HexagonTargetLowering()
1399 setOperationAction(ISD::SSUBO, VT, Expand); in HexagonTargetLowering()
1400 setOperationAction(ISD::ADDCARRY, VT, Expand); in HexagonTargetLowering()
1401 setOperationAction(ISD::SUBCARRY, VT, Expand); in HexagonTargetLowering()
1403 setOperationAction(ISD::ADDCARRY, MVT::i64, Custom); in HexagonTargetLowering()
1404 setOperationAction(ISD::SUBCARRY, MVT::i64, Custom); in HexagonTargetLowering()
1406 setOperationAction(ISD::CTLZ, MVT::i8, Promote); in HexagonTargetLowering()
1407 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in HexagonTargetLowering()
1408 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1409 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1412 setOperationAction(ISD::CTPOP, MVT::i8, Promote); in HexagonTargetLowering()
1413 setOperationAction(ISD::CTPOP, MVT::i16, Promote); in HexagonTargetLowering()
1414 setOperationAction(ISD::CTPOP, MVT::i32, Promote); in HexagonTargetLowering()
1415 setOperationAction(ISD::CTPOP, MVT::i64, Legal); in HexagonTargetLowering()
1417 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1418 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1419 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in HexagonTargetLowering()
1420 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in HexagonTargetLowering()
1422 setOperationAction(ISD::FSHL, MVT::i32, Legal); in HexagonTargetLowering()
1423 setOperationAction(ISD::FSHL, MVT::i64, Legal); in HexagonTargetLowering()
1424 setOperationAction(ISD::FSHR, MVT::i32, Legal); in HexagonTargetLowering()
1425 setOperationAction(ISD::FSHR, MVT::i64, Legal); in HexagonTargetLowering()
1428 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1429 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1430 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS, in HexagonTargetLowering()
1431 ISD::SMUL_LOHI, ISD::UMUL_LOHI}) { in HexagonTargetLowering()
1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1438 ISD::FPOW, ISD::FCOPYSIGN}) { in HexagonTargetLowering()
1445 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1446 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1447 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1453 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in HexagonTargetLowering()
1457 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1458 setOperationAction(ISD::SELECT_CC, VT, Expand); in HexagonTargetLowering()
1461 setOperationAction(ISD::BR_CC, VT, Expand); in HexagonTargetLowering()
1462 setOperationAction(ISD::SELECT_CC, VT, Expand); in HexagonTargetLowering()
1464 setOperationAction(ISD::BR_CC, MVT::Other, Expand); in HexagonTargetLowering()
1474 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV, in HexagonTargetLowering()
1475 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
1476 ISD::UADDO, ISD::SSUBO, ISD::USUBO, ISD::SMUL_LOHI, ISD::UMUL_LOHI, in HexagonTargetLowering()
1478 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1479 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, in HexagonTargetLowering()
1481 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV, in HexagonTargetLowering()
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN, in HexagonTargetLowering()
1483 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2, in HexagonTargetLowering()
1484 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
1485 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR, in HexagonTargetLowering()
1486 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
1488 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool, in HexagonTargetLowering()
1490 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR, in HexagonTargetLowering()
1491 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1492 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1493 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1504 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1505 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1506 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1513 setOperationAction(ISD::SELECT, VT, Promote); in HexagonTargetLowering()
1514 AddPromotedToType(ISD::SELECT, VT, VT32); in HexagonTargetLowering()
1516 setOperationAction(ISD::SRA, VT, Custom); in HexagonTargetLowering()
1517 setOperationAction(ISD::SHL, VT, Custom); in HexagonTargetLowering()
1518 setOperationAction(ISD::SRL, VT, Custom); in HexagonTargetLowering()
1523 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1524 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1525 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1526 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1527 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1528 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1530 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in HexagonTargetLowering()
1531 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in HexagonTargetLowering()
1532 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in HexagonTargetLowering()
1537 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom); in HexagonTargetLowering()
1538 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
1539 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
1540 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
1541 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
1542 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
1544 setOperationAction(ISD::ADD, NativeVT, Legal); in HexagonTargetLowering()
1545 setOperationAction(ISD::SUB, NativeVT, Legal); in HexagonTargetLowering()
1546 setOperationAction(ISD::MUL, NativeVT, Legal); in HexagonTargetLowering()
1547 setOperationAction(ISD::AND, NativeVT, Legal); in HexagonTargetLowering()
1548 setOperationAction(ISD::OR, NativeVT, Legal); in HexagonTargetLowering()
1549 setOperationAction(ISD::XOR, NativeVT, Legal); in HexagonTargetLowering()
1558 setOperationAction(ISD::LOAD, VT, Custom); in HexagonTargetLowering()
1559 setOperationAction(ISD::STORE, VT, Custom); in HexagonTargetLowering()
1564 setCondCodeAction(ISD::SETNE, VT, Expand); in HexagonTargetLowering()
1565 setCondCodeAction(ISD::SETLE, VT, Expand); in HexagonTargetLowering()
1566 setCondCodeAction(ISD::SETGE, VT, Expand); in HexagonTargetLowering()
1567 setCondCodeAction(ISD::SETLT, VT, Expand); in HexagonTargetLowering()
1568 setCondCodeAction(ISD::SETULE, VT, Expand); in HexagonTargetLowering()
1569 setCondCodeAction(ISD::SETUGE, VT, Expand); in HexagonTargetLowering()
1570 setCondCodeAction(ISD::SETULT, VT, Expand); in HexagonTargetLowering()
1574 setOperationAction(ISD::BITCAST, MVT::i8, Custom); in HexagonTargetLowering()
1575 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1576 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1577 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1578 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1579 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
1583 setOperationAction(ISD::FMA, MVT::f64, Expand); in HexagonTargetLowering()
1584 setOperationAction(ISD::FADD, MVT::f64, Expand); in HexagonTargetLowering()
1585 setOperationAction(ISD::FSUB, MVT::f64, Expand); in HexagonTargetLowering()
1586 setOperationAction(ISD::FMUL, MVT::f64, Expand); in HexagonTargetLowering()
1588 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in HexagonTargetLowering()
1589 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); in HexagonTargetLowering()
1591 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in HexagonTargetLowering()
1592 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); in HexagonTargetLowering()
1593 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); in HexagonTargetLowering()
1594 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1595 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1596 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1597 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1598 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1599 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1600 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1601 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1602 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1608 setIndexedLoadAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
1609 setIndexedStoreAction(ISD::POST_INC, VT, Legal); in HexagonTargetLowering()
1615 setOperationAction(ISD::ROTL, MVT::i32, Legal); in HexagonTargetLowering()
1616 setOperationAction(ISD::ROTL, MVT::i64, Legal); in HexagonTargetLowering()
1617 setOperationAction(ISD::ROTR, MVT::i32, Legal); in HexagonTargetLowering()
1618 setOperationAction(ISD::ROTR, MVT::i64, Legal); in HexagonTargetLowering()
1621 setOperationAction(ISD::FADD, MVT::f64, Legal); in HexagonTargetLowering()
1622 setOperationAction(ISD::FSUB, MVT::f64, Legal); in HexagonTargetLowering()
1625 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
1845 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
1876 Info.opc = ISD::INTRINSIC_W_CHAIN; in getTgtMemIntrinsic()
1910 return isOperationLegalOrCustom(ISD::FMA, VT); in isFMAFasterThanFMulAndFAdd()
1958 if (Addr.getOpcode() == ISD::ADD) { in getBaseAndOffset()
2039 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0); in LowerVECTOR_SHUFFLE()
2066 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0); in LowerVECTOR_SHUFFLE()
2102 case ISD::SHL: in getVectorShiftByInt()
2105 case ISD::SRA: in getVectorShiftByInt()
2108 case ISD::SRL: in getVectorShiftByInt()
2249 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8}); in buildVector32()
2250 SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8}); in buildVector32()
2251 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0}); in buildVector32()
2252 SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1}); in buildVector32()
2356 SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0); in extractVector()
2370 SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVector()
2373 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0); in extractVector()
2412 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in extractVector()
2448 SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, in insertVector()
2482 SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV); in insertVector()
2487 return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV); in insertVector()
2571 Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]); in LowerBUILD_VECTOR()
2768 BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
2793 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in LowerUnalignedLoad()
2819 if (Opc == ISD::UADDO) { in LowerUAddSubO()
2820 SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y}); in LowerUAddSubO()
2822 ISD::SETEQ); in LowerUAddSubO()
2825 if (Opc == ISD::USUBO) { in LowerUAddSubO()
2826 SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y}); in LowerUAddSubO()
2828 DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ); in LowerUAddSubO()
2842 if (Opc == ISD::ADDCARRY) in LowerAddSubCarry()
2870 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT), in LowerEH_RETURN()
2886 if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR) in LowerOperation()
2903 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
2904 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
2905 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
2906 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
2907 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
2908 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
2909 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
2910 case ISD::BITCAST: return LowerBITCAST(Op, DAG); in LowerOperation()
2911 case ISD::LOAD: return LowerLoad(Op, DAG); in LowerOperation()
2912 case ISD::STORE: return LowerStore(Op, DAG); in LowerOperation()
2913 case ISD::UADDO: in LowerOperation()
2914 case ISD::USUBO: return LowerUAddSubO(Op, DAG); in LowerOperation()
2915 case ISD::ADDCARRY: in LowerOperation()
2916 case ISD::SUBCARRY: return LowerAddSubCarry(Op, DAG); in LowerOperation()
2917 case ISD::SRA: in LowerOperation()
2918 case ISD::SHL: in LowerOperation()
2919 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG); in LowerOperation()
2920 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
2921 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
2922 case ISD::JumpTable: return LowerJumpTable(Op, DAG); in LowerOperation()
2923 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); in LowerOperation()
2924 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); in LowerOperation()
2925 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); in LowerOperation()
2926 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
2927 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); in LowerOperation()
2928 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); in LowerOperation()
2929 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
2930 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); in LowerOperation()
2931 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
2932 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); in LowerOperation()
2933 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
2934 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
2935 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
2936 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
2937 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG); in LowerOperation()
2938 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); in LowerOperation()
2954 if (N->getOpcode() != ISD::STORE) in LowerOperationWrapper()
2964 case ISD::SRL: in ReplaceNodeResults()
2965 case ISD::SRA: in ReplaceNodeResults()
2966 case ISD::SHL: in ReplaceNodeResults()
2968 case ISD::BITCAST: in ReplaceNodeResults()
3003 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3008 if (Cond->getOpcode() == ISD::XOR) { in PerformDAGCombine()
3011 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
3179 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
3181 const SmallVectorImpl<ISD::InputArg> &Ins, in IsEligibleForTailCallOptimization()
3280 ISD::LoadExtType ExtTy, EVT NewVT) const { in shouldReduceLoadWidth()