Lines Matching refs:ISD
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
92 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in MipsSETargetLowering()
95 setOperationAction(ISD::ADD, VecTys[i], Legal); in MipsSETargetLowering()
96 setOperationAction(ISD::SUB, VecTys[i], Legal); in MipsSETargetLowering()
97 setOperationAction(ISD::LOAD, VecTys[i], Legal); in MipsSETargetLowering()
98 setOperationAction(ISD::STORE, VecTys[i], Legal); in MipsSETargetLowering()
99 setOperationAction(ISD::BITCAST, VecTys[i], Legal); in MipsSETargetLowering()
102 setTargetDAGCombine(ISD::SHL); in MipsSETargetLowering()
103 setTargetDAGCombine(ISD::SRA); in MipsSETargetLowering()
104 setTargetDAGCombine(ISD::SRL); in MipsSETargetLowering()
105 setTargetDAGCombine(ISD::SETCC); in MipsSETargetLowering()
106 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
109 setOperationAction(ISD::ADDC, MVT::i32, Legal); in MipsSETargetLowering()
110 setOperationAction(ISD::ADDE, MVT::i32, Legal); in MipsSETargetLowering()
115 setOperationAction(ISD::MUL, MVT::v2i16, Legal); in MipsSETargetLowering()
128 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
129 setOperationAction(ISD::BR_CC, MVT::f16, Promote); in MipsSETargetLowering()
130 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in MipsSETargetLowering()
131 setOperationAction(ISD::SELECT, MVT::f16, Promote); in MipsSETargetLowering()
132 setOperationAction(ISD::FADD, MVT::f16, Promote); in MipsSETargetLowering()
133 setOperationAction(ISD::FSUB, MVT::f16, Promote); in MipsSETargetLowering()
134 setOperationAction(ISD::FMUL, MVT::f16, Promote); in MipsSETargetLowering()
135 setOperationAction(ISD::FDIV, MVT::f16, Promote); in MipsSETargetLowering()
136 setOperationAction(ISD::FREM, MVT::f16, Promote); in MipsSETargetLowering()
137 setOperationAction(ISD::FMA, MVT::f16, Promote); in MipsSETargetLowering()
138 setOperationAction(ISD::FNEG, MVT::f16, Promote); in MipsSETargetLowering()
139 setOperationAction(ISD::FABS, MVT::f16, Promote); in MipsSETargetLowering()
140 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in MipsSETargetLowering()
141 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); in MipsSETargetLowering()
142 setOperationAction(ISD::FCOS, MVT::f16, Promote); in MipsSETargetLowering()
143 setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote); in MipsSETargetLowering()
144 setOperationAction(ISD::FFLOOR, MVT::f16, Promote); in MipsSETargetLowering()
145 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); in MipsSETargetLowering()
146 setOperationAction(ISD::FPOW, MVT::f16, Promote); in MipsSETargetLowering()
147 setOperationAction(ISD::FPOWI, MVT::f16, Promote); in MipsSETargetLowering()
148 setOperationAction(ISD::FRINT, MVT::f16, Promote); in MipsSETargetLowering()
149 setOperationAction(ISD::FSIN, MVT::f16, Promote); in MipsSETargetLowering()
150 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in MipsSETargetLowering()
151 setOperationAction(ISD::FSQRT, MVT::f16, Promote); in MipsSETargetLowering()
152 setOperationAction(ISD::FEXP, MVT::f16, Promote); in MipsSETargetLowering()
153 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in MipsSETargetLowering()
154 setOperationAction(ISD::FLOG, MVT::f16, Promote); in MipsSETargetLowering()
155 setOperationAction(ISD::FLOG2, MVT::f16, Promote); in MipsSETargetLowering()
156 setOperationAction(ISD::FLOG10, MVT::f16, Promote); in MipsSETargetLowering()
157 setOperationAction(ISD::FROUND, MVT::f16, Promote); in MipsSETargetLowering()
158 setOperationAction(ISD::FTRUNC, MVT::f16, Promote); in MipsSETargetLowering()
159 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in MipsSETargetLowering()
160 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); in MipsSETargetLowering()
161 setOperationAction(ISD::FMINIMUM, MVT::f16, Promote); in MipsSETargetLowering()
162 setOperationAction(ISD::FMAXIMUM, MVT::f16, Promote); in MipsSETargetLowering()
164 setTargetDAGCombine(ISD::AND); in MipsSETargetLowering()
165 setTargetDAGCombine(ISD::OR); in MipsSETargetLowering()
166 setTargetDAGCombine(ISD::SRA); in MipsSETargetLowering()
167 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
168 setTargetDAGCombine(ISD::XOR); in MipsSETargetLowering()
183 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in MipsSETargetLowering()
184 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); in MipsSETargetLowering()
185 setOperationAction(ISD::MULHS, MVT::i32, Custom); in MipsSETargetLowering()
186 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
189 setOperationAction(ISD::MUL, MVT::i64, Legal); in MipsSETargetLowering()
191 setOperationAction(ISD::MUL, MVT::i64, Custom); in MipsSETargetLowering()
194 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom); in MipsSETargetLowering()
195 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom); in MipsSETargetLowering()
196 setOperationAction(ISD::MULHS, MVT::i64, Custom); in MipsSETargetLowering()
197 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
198 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
199 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
202 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); in MipsSETargetLowering()
203 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); in MipsSETargetLowering()
205 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
206 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
207 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); in MipsSETargetLowering()
208 setOperationAction(ISD::LOAD, MVT::i32, Custom); in MipsSETargetLowering()
209 setOperationAction(ISD::STORE, MVT::i32, Custom); in MipsSETargetLowering()
211 setTargetDAGCombine(ISD::MUL); in MipsSETargetLowering()
213 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in MipsSETargetLowering()
214 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); in MipsSETargetLowering()
215 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in MipsSETargetLowering()
219 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in MipsSETargetLowering()
223 setOperationAction(ISD::LOAD, MVT::f64, Custom); in MipsSETargetLowering()
224 setOperationAction(ISD::STORE, MVT::f64, Custom); in MipsSETargetLowering()
230 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in MipsSETargetLowering()
231 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in MipsSETargetLowering()
232 setOperationAction(ISD::MUL, MVT::i32, Legal); in MipsSETargetLowering()
233 setOperationAction(ISD::MULHS, MVT::i32, Legal); in MipsSETargetLowering()
234 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
238 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
239 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
240 setOperationAction(ISD::SDIV, MVT::i32, Legal); in MipsSETargetLowering()
241 setOperationAction(ISD::UDIV, MVT::i32, Legal); in MipsSETargetLowering()
242 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
243 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
247 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
248 setOperationAction(ISD::SELECT, MVT::i32, Legal); in MipsSETargetLowering()
249 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsSETargetLowering()
251 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
252 setOperationAction(ISD::SELECT, MVT::f32, Legal); in MipsSETargetLowering()
253 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in MipsSETargetLowering()
256 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
257 setOperationAction(ISD::SELECT, MVT::f64, Custom); in MipsSETargetLowering()
258 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in MipsSETargetLowering()
260 setOperationAction(ISD::BRCOND, MVT::Other, Legal); in MipsSETargetLowering()
263 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering()
264 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in MipsSETargetLowering()
265 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
266 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
268 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering()
269 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering()
270 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
271 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
277 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in MipsSETargetLowering()
278 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in MipsSETargetLowering()
279 setOperationAction(ISD::MUL, MVT::i64, Legal); in MipsSETargetLowering()
280 setOperationAction(ISD::MULHS, MVT::i64, Legal); in MipsSETargetLowering()
281 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
285 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
286 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
287 setOperationAction(ISD::SDIV, MVT::i64, Legal); in MipsSETargetLowering()
288 setOperationAction(ISD::UDIV, MVT::i64, Legal); in MipsSETargetLowering()
289 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
290 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
294 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
295 setOperationAction(ISD::SELECT, MVT::i64, Legal); in MipsSETargetLowering()
296 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsSETargetLowering()
322 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in addMSAIntType()
325 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAIntType()
326 setOperationAction(ISD::LOAD, Ty, Legal); in addMSAIntType()
327 setOperationAction(ISD::STORE, Ty, Legal); in addMSAIntType()
328 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); in addMSAIntType()
329 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
330 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); in addMSAIntType()
331 setOperationAction(ISD::UNDEF, Ty, Legal); in addMSAIntType()
333 setOperationAction(ISD::ADD, Ty, Legal); in addMSAIntType()
334 setOperationAction(ISD::AND, Ty, Legal); in addMSAIntType()
335 setOperationAction(ISD::CTLZ, Ty, Legal); in addMSAIntType()
336 setOperationAction(ISD::CTPOP, Ty, Legal); in addMSAIntType()
337 setOperationAction(ISD::MUL, Ty, Legal); in addMSAIntType()
338 setOperationAction(ISD::OR, Ty, Legal); in addMSAIntType()
339 setOperationAction(ISD::SDIV, Ty, Legal); in addMSAIntType()
340 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
341 setOperationAction(ISD::SHL, Ty, Legal); in addMSAIntType()
342 setOperationAction(ISD::SRA, Ty, Legal); in addMSAIntType()
343 setOperationAction(ISD::SRL, Ty, Legal); in addMSAIntType()
344 setOperationAction(ISD::SUB, Ty, Legal); in addMSAIntType()
345 setOperationAction(ISD::SMAX, Ty, Legal); in addMSAIntType()
346 setOperationAction(ISD::SMIN, Ty, Legal); in addMSAIntType()
347 setOperationAction(ISD::UDIV, Ty, Legal); in addMSAIntType()
348 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
349 setOperationAction(ISD::UMAX, Ty, Legal); in addMSAIntType()
350 setOperationAction(ISD::UMIN, Ty, Legal); in addMSAIntType()
351 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
352 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
353 setOperationAction(ISD::XOR, Ty, Legal); in addMSAIntType()
356 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); in addMSAIntType()
357 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); in addMSAIntType()
358 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); in addMSAIntType()
359 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); in addMSAIntType()
362 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
363 setCondCodeAction(ISD::SETNE, Ty, Expand); in addMSAIntType()
364 setCondCodeAction(ISD::SETGE, Ty, Expand); in addMSAIntType()
365 setCondCodeAction(ISD::SETGT, Ty, Expand); in addMSAIntType()
366 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
367 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
376 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in addMSAFloatType()
379 setOperationAction(ISD::LOAD, Ty, Legal); in addMSAFloatType()
380 setOperationAction(ISD::STORE, Ty, Legal); in addMSAFloatType()
381 setOperationAction(ISD::BITCAST, Ty, Legal); in addMSAFloatType()
382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
383 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
384 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); in addMSAFloatType()
387 setOperationAction(ISD::FABS, Ty, Legal); in addMSAFloatType()
388 setOperationAction(ISD::FADD, Ty, Legal); in addMSAFloatType()
389 setOperationAction(ISD::FDIV, Ty, Legal); in addMSAFloatType()
390 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
391 setOperationAction(ISD::FLOG2, Ty, Legal); in addMSAFloatType()
392 setOperationAction(ISD::FMA, Ty, Legal); in addMSAFloatType()
393 setOperationAction(ISD::FMUL, Ty, Legal); in addMSAFloatType()
394 setOperationAction(ISD::FRINT, Ty, Legal); in addMSAFloatType()
395 setOperationAction(ISD::FSQRT, Ty, Legal); in addMSAFloatType()
396 setOperationAction(ISD::FSUB, Ty, Legal); in addMSAFloatType()
397 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
399 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
400 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
401 setCondCodeAction(ISD::SETOGT, Ty, Expand); in addMSAFloatType()
402 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
403 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
404 setCondCodeAction(ISD::SETGE, Ty, Expand); in addMSAFloatType()
405 setCondCodeAction(ISD::SETGT, Ty, Expand); in addMSAFloatType()
452 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
453 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
454 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
455 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); in LowerOperation()
456 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
458 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
459 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
460 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, in LowerOperation()
462 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
463 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); in LowerOperation()
464 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
465 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
466 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); in LowerOperation()
467 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
468 case ISD::SELECT: return lowerSELECT(Op, DAG); in LowerOperation()
469 case ISD::BITCAST: return lowerBITCAST(Op, DAG); in LowerOperation()
557 if (N->getOpcode() == ISD::BITCAST) in isVectorAllOnes()
579 if (N->getOpcode() != ISD::XOR) in isBitwiseInverse()
611 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) { in performORCombine()
711 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
805 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
819 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); in genConstMult()
826 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); in genConstMult()
906 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { in performSRACombine()
950 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { in isLegalDSPCondCode()
954 case ISD::SETEQ: in isLegalDSPCondCode()
955 case ISD::SETNE: return true; in isLegalDSPCondCode()
956 case ISD::SETLT: in isLegalDSPCondCode()
957 case ISD::SETLE: in isLegalDSPCondCode()
958 case ISD::SETGT: in isLegalDSPCondCode()
959 case ISD::SETGE: return IsV216; in isLegalDSPCondCode()
960 case ISD::SETULT: in isLegalDSPCondCode()
961 case ISD::SETULE: in isLegalDSPCondCode()
962 case ISD::SETUGT: in isLegalDSPCondCode()
963 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
1010 if (ISD::isBuildVectorAllOnes(Op0.getNode())) in performXORCombine()
1012 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) in performXORCombine()
1017 if (NotOp->getOpcode() == ISD::OR) in performXORCombine()
1031 case ISD::AND: in PerformDAGCombine()
1034 case ISD::OR: in PerformDAGCombine()
1037 case ISD::MUL: in PerformDAGCombine()
1039 case ISD::SHL: in PerformDAGCombine()
1042 case ISD::SRA: in PerformDAGCombine()
1044 case ISD::SRL: in PerformDAGCombine()
1046 case ISD::VSELECT: in PerformDAGCombine()
1048 case ISD::XOR: in PerformDAGCombine()
1051 case ISD::SETCC: in PerformDAGCombine()
1190 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); in lowerLOAD()
1227 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT)); in lowerSTORE()
1241 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, in lowerBITCAST()
1243 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, in lowerBITCAST()
1256 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in lowerBITCAST()
1288 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, in initAccumulator()
1290 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, in initAccumulator()
1298 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in extractLOHI()
1324 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); in lowerDSPIntr()
1412 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, in lowerMSASplatZExt()
1413 DAG.getNode(ISD::AND, DL, ViaVecTy, Result, One)); in lowerMSASplatZExt()
1439 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue); in getBuildVectorSplat()
1440 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue, in getBuildVectorSplat()
1442 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB); in getBuildVectorSplat()
1459 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); in getBuildVectorSplat()
1485 ISD::BITCAST, DL, MVT::v2i64, in lowerMSABinaryBitImmIntr()
1497 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm); in lowerMSABinaryBitImmIntr()
1501 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy), in lowerMSABinaryBitImmIntr()
1518 return DAG.getNode(ISD::AND, DL, ResTy, Vec, SplatVec); in truncateVecElts()
1525 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, truncateVecElts(Op, DAG)); in lowerMSABitClear()
1527 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), in lowerMSABitClear()
1538 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); in lowerMSABitClearImm()
1584 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1590 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1593 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1596 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1619 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1634 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1639 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1642 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1646 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), in lowerINTRINSIC_WO_CHAIN()
1649 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1659 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1660 DAG.getNode(ISD::SHL, DL, VecTy, One, in lowerINTRINSIC_WO_CHAIN()
1667 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), in lowerINTRINSIC_WO_CHAIN()
1680 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1685 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1695 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1696 DAG.getNode(ISD::SHL, DL, VecTy, One, in lowerINTRINSIC_WO_CHAIN()
1703 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), in lowerINTRINSIC_WO_CHAIN()
1719 Op->getOperand(2), ISD::SETEQ); in lowerINTRINSIC_WO_CHAIN()
1725 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ); in lowerINTRINSIC_WO_CHAIN()
1731 Op->getOperand(2), ISD::SETLE); in lowerINTRINSIC_WO_CHAIN()
1737 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE); in lowerINTRINSIC_WO_CHAIN()
1743 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1749 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1755 Op->getOperand(2), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
1761 lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT); in lowerINTRINSIC_WO_CHAIN()
1767 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1773 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1803 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1811 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1817 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1822 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1828 Op->getOperand(2), ISD::SETOEQ); in lowerINTRINSIC_WO_CHAIN()
1832 Op->getOperand(2), ISD::SETOLE); in lowerINTRINSIC_WO_CHAIN()
1836 Op->getOperand(2), ISD::SETOLT); in lowerINTRINSIC_WO_CHAIN()
1840 Op->getOperand(2), ISD::SETONE); in lowerINTRINSIC_WO_CHAIN()
1844 Op->getOperand(2), ISD::SETO); in lowerINTRINSIC_WO_CHAIN()
1848 Op->getOperand(2), ISD::SETUEQ); in lowerINTRINSIC_WO_CHAIN()
1852 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1856 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1860 Op->getOperand(2), ISD::SETUO); in lowerINTRINSIC_WO_CHAIN()
1864 Op->getOperand(2), ISD::SETUNE); in lowerINTRINSIC_WO_CHAIN()
1868 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1872 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1876 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1895 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1896 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
1900 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1903 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1908 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1918 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1921 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
1925 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1929 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1933 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1963 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1993 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
1994 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, in lowerINTRINSIC_WO_CHAIN()
2002 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2003 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, in lowerINTRINSIC_WO_CHAIN()
2010 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2016 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2022 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2028 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2034 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2040 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2046 return DAG.getNode(ISD::SMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2052 return DAG.getNode(ISD::UMIN, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2058 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2064 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2070 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2077 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2078 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, in lowerINTRINSIC_WO_CHAIN()
2085 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2087 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2092 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2098 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2101 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2119 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); in lowerINTRINSIC_WO_CHAIN()
2177 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2183 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2207 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2213 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2237 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2243 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2267 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2273 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2282 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
2285 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2307 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset); in lowerMSALoadIntr()
2309 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); in lowerMSALoadIntr()
2381 Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset); in lowerMSAStoreIntr()
2383 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); in lowerMSAStoreIntr()
2510 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); in lowerBUILD_VECTOR()
2526 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()