Lines Matching refs:ISD
43 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
56 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Split_64()
84 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_Ret_Split_64()
108 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
153 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
199 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
210 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
295 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
331 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, in LowerReturn_64()
346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); in LowerReturn_64()
347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); in LowerReturn_64()
371 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments()
385 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, in LowerFormalArguments_32()
443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
444 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
452 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments_32()
454 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments_32()
456 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments_32()
499 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
500 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue); in LowerFormalArguments_32()
531 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); in LowerFormalArguments_32()
570 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerFormalArguments_32()
580 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments_64()
606 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
613 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
617 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
626 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerFormalArguments_64()
681 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); in LowerFormalArguments_64()
721 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32()
723 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; in LowerCall_32()
750 ISD::ArgFlagsTy Flags = Outs[i].Flags; in LowerCall_32()
791 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; in LowerCall_32()
806 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
809 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
812 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall_32()
815 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall_32()
824 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
858 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); in LowerCall_32()
861 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
864 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
879 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
888 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
893 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
907 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_32()
918 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); in LowerCall_32()
926 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32()
990 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); in LowerCall_32()
995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo, in LowerCall_32()
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi, in LowerCall_32()
1047 ArrayRef<ISD::OutputArg> Outs) { in fixupVariableFloatArgs()
1148 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1151 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1154 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall_64()
1161 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall_64()
1173 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff); in LowerCall_64()
1175 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff); in LowerCall_64()
1195 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, in LowerCall_64()
1202 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, in LowerCall_64()
1204 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); in LowerCall_64()
1222 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); in LowerCall_64()
1229 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall_64()
1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
1322 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, in LowerCall_64()
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, in LowerCall_64()
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
1342 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); in LowerCall_64()
1364 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
1367 case ISD::SETEQ: return SPCC::ICC_E; in IntCondCCodeToICC()
1368 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
1369 case ISD::SETLT: return SPCC::ICC_L; in IntCondCCodeToICC()
1370 case ISD::SETGT: return SPCC::ICC_G; in IntCondCCodeToICC()
1371 case ISD::SETLE: return SPCC::ICC_LE; in IntCondCCodeToICC()
1372 case ISD::SETGE: return SPCC::ICC_GE; in IntCondCCodeToICC()
1373 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
1374 case ISD::SETULE: return SPCC::ICC_LEU; in IntCondCCodeToICC()
1375 case ISD::SETUGT: return SPCC::ICC_GU; in IntCondCCodeToICC()
1376 case ISD::SETUGE: return SPCC::ICC_CC; in IntCondCCodeToICC()
1382 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
1385 case ISD::SETEQ: in FPCondCCodeToFCC()
1386 case ISD::SETOEQ: return SPCC::FCC_E; in FPCondCCodeToFCC()
1387 case ISD::SETNE: in FPCondCCodeToFCC()
1388 case ISD::SETUNE: return SPCC::FCC_NE; in FPCondCCodeToFCC()
1389 case ISD::SETLT: in FPCondCCodeToFCC()
1390 case ISD::SETOLT: return SPCC::FCC_L; in FPCondCCodeToFCC()
1391 case ISD::SETGT: in FPCondCCodeToFCC()
1392 case ISD::SETOGT: return SPCC::FCC_G; in FPCondCCodeToFCC()
1393 case ISD::SETLE: in FPCondCCodeToFCC()
1394 case ISD::SETOLE: return SPCC::FCC_LE; in FPCondCCodeToFCC()
1395 case ISD::SETGE: in FPCondCCodeToFCC()
1396 case ISD::SETOGE: return SPCC::FCC_GE; in FPCondCCodeToFCC()
1397 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
1398 case ISD::SETULE: return SPCC::FCC_ULE; in FPCondCCodeToFCC()
1399 case ISD::SETUGT: return SPCC::FCC_UG; in FPCondCCodeToFCC()
1400 case ISD::SETUGE: return SPCC::FCC_UGE; in FPCondCCodeToFCC()
1401 case ISD::SETUO: return SPCC::FCC_U; in FPCondCCodeToFCC()
1402 case ISD::SETO: return SPCC::FCC_O; in FPCondCCodeToFCC()
1403 case ISD::SETONE: return SPCC::FCC_LG; in FPCondCCodeToFCC()
1404 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
1437 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) { in SparcTargetLowering()
1442 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1443 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1444 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand); in SparcTargetLowering()
1446 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1447 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1448 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand); in SparcTargetLowering()
1454 setOperationAction(ISD::LOAD, MVT::v2i32, Legal); in SparcTargetLowering()
1455 setOperationAction(ISD::STORE, MVT::v2i32, Legal); in SparcTargetLowering()
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal); in SparcTargetLowering()
1460 setOperationAction(ISD::LOAD, MVT::i64, Custom); in SparcTargetLowering()
1461 setOperationAction(ISD::STORE, MVT::i64, Custom); in SparcTargetLowering()
1470 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in SparcTargetLowering()
1471 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in SparcTargetLowering()
1476 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
1484 setOperationAction(ISD::GlobalAddress, PtrVT, Custom); in SparcTargetLowering()
1485 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom); in SparcTargetLowering()
1486 setOperationAction(ISD::ConstantPool, PtrVT, Custom); in SparcTargetLowering()
1487 setOperationAction(ISD::BlockAddress, PtrVT, Custom); in SparcTargetLowering()
1490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); in SparcTargetLowering()
1491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); in SparcTargetLowering()
1492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); in SparcTargetLowering()
1495 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1496 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1497 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1498 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1502 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
1503 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
1504 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1505 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in SparcTargetLowering()
1509 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1511 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
1512 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1515 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in SparcTargetLowering()
1516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1517 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in SparcTargetLowering()
1518 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
1520 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
1521 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
1524 setOperationAction(ISD::SELECT, MVT::i32, Expand); in SparcTargetLowering()
1525 setOperationAction(ISD::SELECT, MVT::f32, Expand); in SparcTargetLowering()
1526 setOperationAction(ISD::SELECT, MVT::f64, Expand); in SparcTargetLowering()
1527 setOperationAction(ISD::SELECT, MVT::f128, Expand); in SparcTargetLowering()
1529 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1530 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1531 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1532 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1535 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in SparcTargetLowering()
1536 setOperationAction(ISD::BRIND, MVT::Other, Expand); in SparcTargetLowering()
1537 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in SparcTargetLowering()
1538 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in SparcTargetLowering()
1539 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in SparcTargetLowering()
1540 setOperationAction(ISD::BR_CC, MVT::f64, Custom); in SparcTargetLowering()
1541 setOperationAction(ISD::BR_CC, MVT::f128, Custom); in SparcTargetLowering()
1543 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1544 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1545 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1546 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1548 setOperationAction(ISD::ADDC, MVT::i32, Custom); in SparcTargetLowering()
1549 setOperationAction(ISD::ADDE, MVT::i32, Custom); in SparcTargetLowering()
1550 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1551 setOperationAction(ISD::SUBE, MVT::i32, Custom); in SparcTargetLowering()
1554 setOperationAction(ISD::ADDC, MVT::i64, Custom); in SparcTargetLowering()
1555 setOperationAction(ISD::ADDE, MVT::i64, Custom); in SparcTargetLowering()
1556 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
1557 setOperationAction(ISD::SUBE, MVT::i64, Custom); in SparcTargetLowering()
1558 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in SparcTargetLowering()
1559 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in SparcTargetLowering()
1560 setOperationAction(ISD::SELECT, MVT::i64, Expand); in SparcTargetLowering()
1561 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
1562 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in SparcTargetLowering()
1563 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
1565 setOperationAction(ISD::CTPOP, MVT::i64, in SparcTargetLowering()
1567 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SparcTargetLowering()
1568 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SparcTargetLowering()
1569 setOperationAction(ISD::BSWAP, MVT::i64, Expand); in SparcTargetLowering()
1570 setOperationAction(ISD::ROTL , MVT::i64, Expand); in SparcTargetLowering()
1571 setOperationAction(ISD::ROTR , MVT::i64, Expand); in SparcTargetLowering()
1572 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in SparcTargetLowering()
1588 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); in SparcTargetLowering()
1590 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); in SparcTargetLowering()
1593 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); in SparcTargetLowering()
1594 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); in SparcTargetLowering()
1597 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1598 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); in SparcTargetLowering()
1599 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); in SparcTargetLowering()
1600 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); in SparcTargetLowering()
1612 setOperationAction(ISD::FNEG, MVT::f64, Custom); in SparcTargetLowering()
1613 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1616 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1617 setOperationAction(ISD::FCOS , MVT::f128, Expand); in SparcTargetLowering()
1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1619 setOperationAction(ISD::FREM , MVT::f128, Expand); in SparcTargetLowering()
1620 setOperationAction(ISD::FMA , MVT::f128, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1622 setOperationAction(ISD::FCOS , MVT::f64, Expand); in SparcTargetLowering()
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1624 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering()
1625 setOperationAction(ISD::FMA , MVT::f64, Expand); in SparcTargetLowering()
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1627 setOperationAction(ISD::FCOS , MVT::f32, Expand); in SparcTargetLowering()
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
1629 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
1630 setOperationAction(ISD::FMA , MVT::f32, Expand); in SparcTargetLowering()
1631 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SparcTargetLowering()
1632 setOperationAction(ISD::CTLZ , MVT::i32, Expand); in SparcTargetLowering()
1633 setOperationAction(ISD::ROTL , MVT::i32, Expand); in SparcTargetLowering()
1634 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
1635 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in SparcTargetLowering()
1636 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in SparcTargetLowering()
1637 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in SparcTargetLowering()
1638 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in SparcTargetLowering()
1639 setOperationAction(ISD::FPOW , MVT::f128, Expand); in SparcTargetLowering()
1640 setOperationAction(ISD::FPOW , MVT::f64, Expand); in SparcTargetLowering()
1641 setOperationAction(ISD::FPOW , MVT::f32, Expand); in SparcTargetLowering()
1643 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1644 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1645 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); in SparcTargetLowering()
1648 setOperationAction(ISD::MULHU, MVT::i32, Expand); in SparcTargetLowering()
1649 setOperationAction(ISD::MULHS, MVT::i32, Expand); in SparcTargetLowering()
1650 setOperationAction(ISD::MUL, MVT::i32, Expand); in SparcTargetLowering()
1654 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1655 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in SparcTargetLowering()
1658 setOperationAction(ISD::SDIV, MVT::i32, Expand); in SparcTargetLowering()
1661 setOperationAction(ISD::UDIV, MVT::i32, Expand); in SparcTargetLowering()
1669 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1670 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in SparcTargetLowering()
1671 setOperationAction(ISD::MULHU, MVT::i64, Expand); in SparcTargetLowering()
1672 setOperationAction(ISD::MULHS, MVT::i64, Expand); in SparcTargetLowering()
1674 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
1675 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering()
1677 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1679 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); in SparcTargetLowering()
1683 setOperationAction(ISD::VASTART , MVT::Other, Custom); in SparcTargetLowering()
1685 setOperationAction(ISD::VAARG , MVT::Other, Custom); in SparcTargetLowering()
1687 setOperationAction(ISD::TRAP , MVT::Other, Legal); in SparcTargetLowering()
1688 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal); in SparcTargetLowering()
1691 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in SparcTargetLowering()
1692 setOperationAction(ISD::VAEND , MVT::Other, Expand); in SparcTargetLowering()
1693 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in SparcTargetLowering()
1694 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); in SparcTargetLowering()
1695 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in SparcTargetLowering()
1699 setOperationAction(ISD::CTPOP, MVT::i32, in SparcTargetLowering()
1703 setOperationAction(ISD::LOAD, MVT::f128, Legal); in SparcTargetLowering()
1704 setOperationAction(ISD::STORE, MVT::f128, Legal); in SparcTargetLowering()
1706 setOperationAction(ISD::LOAD, MVT::f128, Custom); in SparcTargetLowering()
1707 setOperationAction(ISD::STORE, MVT::f128, Custom); in SparcTargetLowering()
1711 setOperationAction(ISD::FADD, MVT::f128, Legal); in SparcTargetLowering()
1712 setOperationAction(ISD::FSUB, MVT::f128, Legal); in SparcTargetLowering()
1713 setOperationAction(ISD::FMUL, MVT::f128, Legal); in SparcTargetLowering()
1714 setOperationAction(ISD::FDIV, MVT::f128, Legal); in SparcTargetLowering()
1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal); in SparcTargetLowering()
1716 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in SparcTargetLowering()
1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in SparcTargetLowering()
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal); in SparcTargetLowering()
1720 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1723 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1736 setOperationAction(ISD::FADD, MVT::f128, Custom); in SparcTargetLowering()
1737 setOperationAction(ISD::FSUB, MVT::f128, Custom); in SparcTargetLowering()
1738 setOperationAction(ISD::FMUL, MVT::f128, Custom); in SparcTargetLowering()
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom); in SparcTargetLowering()
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom); in SparcTargetLowering()
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom); in SparcTargetLowering()
1742 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1744 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); in SparcTargetLowering()
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); in SparcTargetLowering()
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); in SparcTargetLowering()
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote); in SparcTargetLowering()
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote); in SparcTargetLowering()
1796 setOperationAction(ISD::FMUL, MVT::f32, Promote); in SparcTargetLowering()
1801 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
1804 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); in SparcTargetLowering()
1806 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in SparcTargetLowering()
1882 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC()
1884 CC == ISD::SETNE && in LookThroughSetCC()
1936 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeHiLoPair()
1962 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx); in makeAddress()
1983 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); in makeAddress()
1986 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); in makeAddress()
1992 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); in makeAddress()
1995 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeAddress()
2080 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2099 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); in LowerGlobalTLSAddress()
2114 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); in LowerGlobalTLSAddress()
2116 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2248 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2281 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2288 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); in LowerF128Compare()
2356 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in LowerFP_TO_SINT()
2382 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); in LowerSINT_TO_FP()
2431 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
2469 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2513 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT), in LowerVASTART()
2531 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
2588 Size = DAG.getNode(ISD::ADD, dl, VT, Size, in LowerDYNAMIC_STACKALLOC()
2595 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
2600 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, in LowerDYNAMIC_STACKALLOC()
2636 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2641 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, in getFRAMEADDR()
2682 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2740 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Load()
2763 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Load()
2808 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, in LowerF128Store()
2813 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains); in LowerF128Store()
2828 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
2888 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); in LowerADDC_ADDE_SUBC_SUBE()
2889 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, in LowerADDC_ADDE_SUBC_SUBE()
2891 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); in LowerADDC_ADDE_SUBC_SUBE()
2894 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); in LowerADDC_ADDE_SUBC_SUBE()
2895 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, in LowerADDC_ADDE_SUBC_SUBE()
2897 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); in LowerADDC_ADDE_SUBC_SUBE()
2904 case ISD::ADDC: hiOpc = ISD::ADDE; break; in LowerADDC_ADDE_SUBC_SUBE()
2905 case ISD::ADDE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2906 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
2907 case ISD::SUBE: hasChain = true; break; in LowerADDC_ADDE_SUBC_SUBE()
2920 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2921 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); in LowerADDC_ADDE_SUBC_SUBE()
2922 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, in LowerADDC_ADDE_SUBC_SUBE()
2925 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); in LowerADDC_ADDE_SUBC_SUBE()
2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2938 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO()
2950 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); in LowerUMULO_SMULO()
2951 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); in LowerUMULO_SMULO()
2959 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
2961 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, in LowerUMULO_SMULO()
2964 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); in LowerUMULO_SMULO()
2965 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); in LowerUMULO_SMULO()
2968 ISD::SETNE); in LowerUMULO_SMULO()
3011 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, in LowerOperation()
3013 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, in LowerOperation()
3015 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
3016 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
3017 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
3018 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
3019 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3021 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3023 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, in LowerOperation()
3025 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3027 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, in LowerOperation()
3029 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
3031 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); in LowerOperation()
3032 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
3033 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, in LowerOperation()
3036 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
3037 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
3038 case ISD::FADD: return LowerF128Op(Op, DAG, in LowerOperation()
3040 case ISD::FSUB: return LowerF128Op(Op, DAG, in LowerOperation()
3042 case ISD::FMUL: return LowerF128Op(Op, DAG, in LowerOperation()
3044 case ISD::FDIV: return LowerF128Op(Op, DAG, in LowerOperation()
3046 case ISD::FSQRT: return LowerF128Op(Op, DAG, in LowerOperation()
3048 case ISD::FABS: in LowerOperation()
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); in LowerOperation()
3050 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); in LowerOperation()
3051 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); in LowerOperation()
3052 case ISD::ADDC: in LowerOperation()
3053 case ISD::ADDE: in LowerOperation()
3054 case ISD::SUBC: in LowerOperation()
3055 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); in LowerOperation()
3056 case ISD::UMULO: in LowerOperation()
3057 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
3058 case ISD::ATOMIC_LOAD: in LowerOperation()
3059 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); in LowerOperation()
3060 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
3092 case ISD::BITCAST: in PerformDAGCombine()
3346 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3347 case ISD::FP_TO_UINT: in ReplaceNodeResults()
3352 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
3361 case ISD::READCYCLECOUNTER: { in ReplaceNodeResults()
3366 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops); in ReplaceNodeResults()
3371 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3372 case ISD::UINT_TO_FP: in ReplaceNodeResults()
3378 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
3387 case ISD::LOAD: { in ReplaceNodeResults()
3400 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes); in ReplaceNodeResults()