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Searched refs:AArch64 (Results 1 – 25 of 130) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h31 case AArch64::X0: return AArch64::W0; in getWRegFromXReg()
32 case AArch64::X1: return AArch64::W1; in getWRegFromXReg()
33 case AArch64::X2: return AArch64::W2; in getWRegFromXReg()
34 case AArch64::X3: return AArch64::W3; in getWRegFromXReg()
35 case AArch64::X4: return AArch64::W4; in getWRegFromXReg()
36 case AArch64::X5: return AArch64::W5; in getWRegFromXReg()
37 case AArch64::X6: return AArch64::W6; in getWRegFromXReg()
38 case AArch64::X7: return AArch64::W7; in getWRegFromXReg()
39 case AArch64::X8: return AArch64::W8; in getWRegFromXReg()
40 case AArch64::X9: return AArch64::W9; in getWRegFromXReg()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64MacroFusion.cpp24 if (SecondMI.getOpcode() != AArch64::Bcc) in isArithmeticBccPair()
33 if (CmpOnly && !(FirstMI->getOperand(0).getReg() == AArch64::XZR || in isArithmeticBccPair()
34 FirstMI->getOperand(0).getReg() == AArch64::WZR)) { in isArithmeticBccPair()
39 case AArch64::ADDSWri: in isArithmeticBccPair()
40 case AArch64::ADDSWrr: in isArithmeticBccPair()
41 case AArch64::ADDSXri: in isArithmeticBccPair()
42 case AArch64::ADDSXrr: in isArithmeticBccPair()
43 case AArch64::ANDSWri: in isArithmeticBccPair()
44 case AArch64::ANDSWrr: in isArithmeticBccPair()
45 case AArch64::ANDSXri: in isArithmeticBccPair()
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DAArch64FalkorHWPFFix.cpp247 case AArch64::LD1i64: in getLoadInfo()
248 case AArch64::LD2i64: in getLoadInfo()
255 case AArch64::LD1i8: in getLoadInfo()
256 case AArch64::LD1i16: in getLoadInfo()
257 case AArch64::LD1i32: in getLoadInfo()
258 case AArch64::LD2i8: in getLoadInfo()
259 case AArch64::LD2i16: in getLoadInfo()
260 case AArch64::LD2i32: in getLoadInfo()
261 case AArch64::LD3i8: in getLoadInfo()
262 case AArch64::LD3i16: in getLoadInfo()
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DAArch64InstrInfo.cpp71 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP, in AArch64InstrInfo()
72 AArch64::CATCHRET), in AArch64InstrInfo()
84 if (Op == AArch64::INLINEASM || Op == AArch64::INLINEASM_BR) in getInstSizeInBytes()
118 case AArch64::TLSDESC_CALLSEQ: in getInstSizeInBytes()
122 case AArch64::SpeculationBarrierISBDSBEndBB: in getInstSizeInBytes()
126 case AArch64::SpeculationBarrierSBEndBB: in getInstSizeInBytes()
130 case AArch64::JumpTableDest32: in getInstSizeInBytes()
131 case AArch64::JumpTableDest16: in getInstSizeInBytes()
132 case AArch64::JumpTableDest8: in getInstSizeInBytes()
135 case AArch64::SPACE: in getInstSizeInBytes()
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DAArch64SIMDInstrOpt.cpp103 RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
104 AArch64::STPQi, AArch64::FPR128RegClass),
105 RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
106 AArch64::STPQi, AArch64::FPR128RegClass),
107 RuleST2(AArch64::ST2Twov2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
108 AArch64::STPDi, AArch64::FPR64RegClass),
109 RuleST2(AArch64::ST2Twov8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
110 AArch64::STPQi, AArch64::FPR128RegClass),
111 RuleST2(AArch64::ST2Twov4h, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
112 AArch64::STPDi, AArch64::FPR64RegClass),
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DAArch64DeadRegisterDefinitionsPass.cpp79 case AArch64::LDADDB: case AArch64::LDADDH: in atomicReadDroppedOnZero()
80 case AArch64::LDADDW: case AArch64::LDADDX: in atomicReadDroppedOnZero()
81 case AArch64::LDADDLB: case AArch64::LDADDLH: in atomicReadDroppedOnZero()
82 case AArch64::LDADDLW: case AArch64::LDADDLX: in atomicReadDroppedOnZero()
83 case AArch64::LDCLRB: case AArch64::LDCLRH: in atomicReadDroppedOnZero()
84 case AArch64::LDCLRW: case AArch64::LDCLRX: in atomicReadDroppedOnZero()
85 case AArch64::LDCLRLB: case AArch64::LDCLRLH: in atomicReadDroppedOnZero()
86 case AArch64::LDCLRLW: case AArch64::LDCLRLX: in atomicReadDroppedOnZero()
87 case AArch64::LDEORB: case AArch64::LDEORH: in atomicReadDroppedOnZero()
88 case AArch64::LDEORW: case AArch64::LDEORX: in atomicReadDroppedOnZero()
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DAArch64PBQPRegAlloc.cpp37 return AArch64::FPR32RegClass.contains(reg) || in isFPReg()
38 AArch64::FPR64RegClass.contains(reg) || in isFPReg()
39 AArch64::FPR128RegClass.contains(reg); in isFPReg()
47 case AArch64::S1: in isOdd()
48 case AArch64::S3: in isOdd()
49 case AArch64::S5: in isOdd()
50 case AArch64::S7: in isOdd()
51 case AArch64::S9: in isOdd()
52 case AArch64::S11: in isOdd()
53 case AArch64::S13: in isOdd()
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DAArch64CondBrTuning.cpp94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV) in convertToFlagSetting()
103 NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in convertToFlagSetting()
120 case AArch64::CBZW: in convertToCondBr()
121 case AArch64::CBZX: in convertToCondBr()
124 case AArch64::CBNZW: in convertToCondBr()
125 case AArch64::CBNZX: in convertToCondBr()
128 case AArch64::TBZW: in convertToCondBr()
129 case AArch64::TBZX: in convertToCondBr()
132 case AArch64::TBNZW: in convertToCondBr()
133 case AArch64::TBNZX: in convertToCondBr()
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DAArch64LoadStoreOptimizer.cpp218 case AArch64::STRBBui: in isNarrowStore()
219 case AArch64::STURBBi: in isNarrowStore()
220 case AArch64::STRHHui: in isNarrowStore()
221 case AArch64::STURHHi: in isNarrowStore()
232 case AArch64::STGOffset: in isTagStore()
233 case AArch64::STZGOffset: in isTagStore()
234 case AArch64::ST2GOffset: in isTagStore()
235 case AArch64::STZ2GOffset: in isTagStore()
249 case AArch64::STRDui: in getMatchingNonSExtOpcode()
250 case AArch64::STURDi: in getMatchingNonSExtOpcode()
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DAArch64ExpandPseudoInsts.cpp127 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
145 case AArch64::ORRWri: in expandMOVImm()
146 case AArch64::ORRXri: in expandMOVImm()
149 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR) in expandMOVImm()
152 case AArch64::MOVNWi: in expandMOVImm()
153 case AArch64::MOVNXi: in expandMOVImm()
154 case AArch64::MOVZWi: in expandMOVImm()
155 case AArch64::MOVZXi: { in expandMOVImm()
164 case AArch64::MOVKWi: in expandMOVImm()
165 case AArch64::MOVKXi: { in expandMOVImm()
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DAArch64CallingConvention.cpp23 static const MCPhysReg XRegList[] = {AArch64::X0, AArch64::X1, AArch64::X2,
24 AArch64::X3, AArch64::X4, AArch64::X5,
25 AArch64::X6, AArch64::X7};
26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
27 AArch64::H3, AArch64::H4, AArch64::H5,
28 AArch64::H6, AArch64::H7};
29 static const MCPhysReg SRegList[] = {AArch64::S0, AArch64::S1, AArch64::S2,
30 AArch64::S3, AArch64::S4, AArch64::S5,
31 AArch64::S6, AArch64::S7};
32 static const MCPhysReg DRegList[] = {AArch64::D0, AArch64::D1, AArch64::D2,
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DAArch64SLSHardening.cpp87 ? AArch64::SpeculationBarrierSBEndBB in insertSpeculationBarrier()
88 : AArch64::SpeculationBarrierISBDSBEndBB; in insertSpeculationBarrier()
90 (MBBI->getOpcode() != AArch64::SpeculationBarrierSBEndBB && in insertSpeculationBarrier()
91 MBBI->getOpcode() != AArch64::SpeculationBarrierISBDSBEndBB)) in insertSpeculationBarrier()
111 case AArch64::BLR: in isBLR()
112 case AArch64::BLRNoIP: in isBLR()
114 case AArch64::BLRAA: in isBLR()
115 case AArch64::BLRAB: in isBLR()
116 case AArch64::BLRAAZ: in isBLR()
117 case AArch64::BLRABZ: in isBLR()
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DAArch64AsmPrinter.cpp304 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8)); in emitSled()
307 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0)); in emitSled()
316 MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES; in LowerHWASAN_CHECK_MEMACCESS()
325 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" + in LowerHWASAN_CHECK_MEMACCESS()
333 MCInstBuilder(AArch64::BL) in LowerHWASAN_CHECK_MEMACCESS()
384 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SBFMXri) in emitHwasanMemaccessSymbols()
385 .addReg(AArch64::X16) in emitHwasanMemaccessSymbols()
391 MCInstBuilder(AArch64::LDRBBroX) in emitHwasanMemaccessSymbols()
392 .addReg(AArch64::W16) in emitHwasanMemaccessSymbols()
393 .addReg(IsShort ? AArch64::X20 : AArch64::X9) in emitHwasanMemaccessSymbols()
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DAArch64ISelDAGToDAG.cpp702 MLAOpc = AArch64::MLAv4i16_indexed; in tryMLAV64LaneV128()
705 MLAOpc = AArch64::MLAv8i16_indexed; in tryMLAV64LaneV128()
708 MLAOpc = AArch64::MLAv2i32_indexed; in tryMLAV64LaneV128()
711 MLAOpc = AArch64::MLAv4i32_indexed; in tryMLAV64LaneV128()
740 SMULLOpc = AArch64::SMULLv4i16_indexed; in tryMULLV64LaneV128()
743 SMULLOpc = AArch64::SMULLv2i32_indexed; in tryMULLV64LaneV128()
751 SMULLOpc = AArch64::UMULLv4i16_indexed; in tryMULLV64LaneV128()
754 SMULLOpc = AArch64::UMULLv2i32_indexed; in tryMULLV64LaneV128()
773 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded()
1017 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen()
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DAArch64StackTaggingPreRA.cpp106 case AArch64::LDRBBui: in isUncheckedLoadOrStoreOpcode()
107 case AArch64::LDRHHui: in isUncheckedLoadOrStoreOpcode()
108 case AArch64::LDRWui: in isUncheckedLoadOrStoreOpcode()
109 case AArch64::LDRXui: in isUncheckedLoadOrStoreOpcode()
111 case AArch64::LDRBui: in isUncheckedLoadOrStoreOpcode()
112 case AArch64::LDRHui: in isUncheckedLoadOrStoreOpcode()
113 case AArch64::LDRSui: in isUncheckedLoadOrStoreOpcode()
114 case AArch64::LDRDui: in isUncheckedLoadOrStoreOpcode()
115 case AArch64::LDRQui: in isUncheckedLoadOrStoreOpcode()
117 case AArch64::LDRSHWui: in isUncheckedLoadOrStoreOpcode()
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DAArch64FrameLowering.cpp208 IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi || in getArgumentStackToRestore()
209 RetOpcode == AArch64::TCRETURNri || in getArgumentStackToRestore()
210 RetOpcode == AArch64::TCRETURNriBTI; in getArgumentStackToRestore()
290 MI.getOpcode() == AArch64::ADDXri || in estimateRSStackSizeLimit()
291 MI.getOpcode() == AArch64::ADDSXri) in estimateRSStackSizeLimit()
430 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, in eliminateCallFramePseudoInstr()
437 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, in eliminateCallFramePseudoInstr()
489 TRI.getDwarfRegNum(AArch64::VG, true), Comment); in createDefCFAExpressionFromSP()
522 TRI.getDwarfRegNum(AArch64::VG, true), Comment); in createCfaOffset()
593 return AArch64::X9; in findScratchNonCalleeSaveRegister()
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DAArch64CollectLOH.cpp180 case AArch64::ADRP: in canDefBePartOfLOH()
182 case AArch64::ADDXri: in canDefBePartOfLOH()
184 case AArch64::LDRXui: in canDefBePartOfLOH()
185 case AArch64::LDRWui: in canDefBePartOfLOH()
202 case AArch64::STRBBui: in isCandidateStore()
203 case AArch64::STRHHui: in isCandidateStore()
204 case AArch64::STRBui: in isCandidateStore()
205 case AArch64::STRHui: in isCandidateStore()
206 case AArch64::STRWui: in isCandidateStore()
207 case AArch64::STRXui: in isCandidateStore()
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DAArch64FastISel.cpp358 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca()
359 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), in fastMaterializeAlloca()
378 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
379 : &AArch64::GPR32RegClass; in materializeInt()
380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
403 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP()
409 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
430 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeFP()
431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in materializeFP()
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DAArch64ConditionalCompares.cpp261 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in isDeadDef()
286 case AArch64::CBZW: in parseCond()
287 case AArch64::CBZX: in parseCond()
291 case AArch64::CBNZW: in parseCond()
292 case AArch64::CBNZX: in parseCond()
304 if (!I->readsRegister(AArch64::NZCV)) { in findConvertibleCompare()
306 case AArch64::CBZW: in findConvertibleCompare()
307 case AArch64::CBZX: in findConvertibleCompare()
308 case AArch64::CBNZW: in findConvertibleCompare()
309 case AArch64::CBNZX: in findConvertibleCompare()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp299 case AArch64::LDR_ZA: in getInstruction()
300 case AArch64::STR_ZA: { in getInstruction()
301 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZA)); in getInstruction()
310 case AArch64::LD1_MXIPXX_H_B: in getInstruction()
311 case AArch64::LD1_MXIPXX_V_B: in getInstruction()
312 case AArch64::ST1_MXIPXX_H_B: in getInstruction()
313 case AArch64::ST1_MXIPXX_V_B: in getInstruction()
314 case AArch64::INSERT_MXIPZ_H_B: in getInstruction()
315 case AArch64::INSERT_MXIPZ_V_B: in getInstruction()
319 MI.insert(MI.begin(), MCOperand::createReg(AArch64::ZAB0)); in getInstruction()
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/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DAArch64TargetParser.def19 ARMBuildAttrs::CPUArch::v8_A, FK_NONE, AArch64::AEK_NONE)
22 (AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD))
25 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
26 AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RDM))
29 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
30 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
31 AArch64::AEK_RDM))
34 (AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
35 AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
36 AArch64::AEK_RDM | AArch64::AEK_RCPC))
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64InstPrinter.cpp74 if (Opcode == AArch64::SYSxt) in printInst()
81 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || in printInst()
82 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { in printInst()
88 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); in printInst()
89 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); in printInst()
131 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
134 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
138 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
141 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
144 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
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DAArch64MCTargetDesc.cpp69 {codeview::RegisterId::ARM64_W0, AArch64::W0}, in initLLVMToCVRegMapping()
70 {codeview::RegisterId::ARM64_W1, AArch64::W1}, in initLLVMToCVRegMapping()
71 {codeview::RegisterId::ARM64_W2, AArch64::W2}, in initLLVMToCVRegMapping()
72 {codeview::RegisterId::ARM64_W3, AArch64::W3}, in initLLVMToCVRegMapping()
73 {codeview::RegisterId::ARM64_W4, AArch64::W4}, in initLLVMToCVRegMapping()
74 {codeview::RegisterId::ARM64_W5, AArch64::W5}, in initLLVMToCVRegMapping()
75 {codeview::RegisterId::ARM64_W6, AArch64::W6}, in initLLVMToCVRegMapping()
76 {codeview::RegisterId::ARM64_W7, AArch64::W7}, in initLLVMToCVRegMapping()
77 {codeview::RegisterId::ARM64_W8, AArch64::W8}, in initLLVMToCVRegMapping()
78 {codeview::RegisterId::ARM64_W9, AArch64::W9}, in initLLVMToCVRegMapping()
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DAArch64AsmBackend.cpp46 return AArch64::NumTargetFixupKinds; in getNumFixupKinds()
52 const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = { in getFixupKindInfo()
118 case AArch64::fixup_aarch64_movw: in getFixupKindNumBytes()
119 case AArch64::fixup_aarch64_pcrel_branch14: in getFixupKindNumBytes()
120 case AArch64::fixup_aarch64_add_imm12: in getFixupKindNumBytes()
121 case AArch64::fixup_aarch64_ldst_imm12_scale1: in getFixupKindNumBytes()
122 case AArch64::fixup_aarch64_ldst_imm12_scale2: in getFixupKindNumBytes()
123 case AArch64::fixup_aarch64_ldst_imm12_scale4: in getFixupKindNumBytes()
124 case AArch64::fixup_aarch64_ldst_imm12_scale8: in getFixupKindNumBytes()
125 case AArch64::fixup_aarch64_ldst_imm12_scale16: in getFixupKindNumBytes()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Support/
DAArch64TargetParser.cpp27 unsigned AArch64::getDefaultFPU(StringRef CPU, AArch64::ArchKind AK) { in getDefaultFPU()
38 uint64_t AArch64::getDefaultExtensions(StringRef CPU, AArch64::ArchKind AK) { in getDefaultExtensions()
48 .Default(AArch64::AEK_INVALID); in getDefaultExtensions()
51 AArch64::ArchKind AArch64::getCPUArchKind(StringRef CPU) { in getCPUArchKind()
55 return StringSwitch<AArch64::ArchKind>(CPU) in getCPUArchKind()
62 bool AArch64::getExtensionFeatures(uint64_t Extensions, in getExtensionFeatures()
64 if (Extensions == AArch64::AEK_INVALID) in getExtensionFeatures()
109 if (Extensions & AArch64::AEK_SME) in getExtensionFeatures()
111 if (Extensions & AArch64::AEK_SMEF64) in getExtensionFeatures()
113 if (Extensions & AArch64::AEK_SMEI64) in getExtensionFeatures()
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