103     RuleST2(AArch64::ST2Twov2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
104           AArch64::STPQi, AArch64::FPR128RegClass),
105     RuleST2(AArch64::ST2Twov4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
106           AArch64::STPQi, AArch64::FPR128RegClass),
107     RuleST2(AArch64::ST2Twov2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
108           AArch64::STPDi, AArch64::FPR64RegClass),
109     RuleST2(AArch64::ST2Twov8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
110           AArch64::STPQi, AArch64::FPR128RegClass),
111     RuleST2(AArch64::ST2Twov4h, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
112           AArch64::STPDi, AArch64::FPR64RegClass),
113     RuleST2(AArch64::ST2Twov16b, AArch64::ZIP1v16i8, AArch64::ZIP2v16i8,
114           AArch64::STPQi, AArch64::FPR128RegClass),
115     RuleST2(AArch64::ST2Twov8b, AArch64::ZIP1v8i8, AArch64::ZIP2v8i8,
116           AArch64::STPDi, AArch64::FPR64RegClass),
118     RuleST4(AArch64::ST4Fourv2d, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
119           AArch64::ZIP1v2i64, AArch64::ZIP2v2i64, AArch64::ZIP1v2i64,
120           AArch64::ZIP2v2i64, AArch64::ZIP1v2i64, AArch64::ZIP2v2i64,
121           AArch64::STPQi, AArch64::STPQi, AArch64::FPR128RegClass),
122     RuleST4(AArch64::ST4Fourv4s, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
123           AArch64::ZIP1v4i32, AArch64::ZIP2v4i32, AArch64::ZIP1v4i32,
124           AArch64::ZIP2v4i32, AArch64::ZIP1v4i32, AArch64::ZIP2v4i32,
125           AArch64::STPQi, AArch64::STPQi, AArch64::FPR128RegClass),
126     RuleST4(AArch64::ST4Fourv2s, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
127           AArch64::ZIP1v2i32, AArch64::ZIP2v2i32, AArch64::ZIP1v2i32,
128           AArch64::ZIP2v2i32, AArch64::ZIP1v2i32, AArch64::ZIP2v2i32,
129           AArch64::STPDi, AArch64::STPDi, AArch64::FPR64RegClass),
130     RuleST4(AArch64::ST4Fourv8h, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
131           AArch64::ZIP1v8i16, AArch64::ZIP2v8i16, AArch64::ZIP1v8i16,
132           AArch64::ZIP2v8i16, AArch64::ZIP1v8i16, AArch64::ZIP2v8i16,
133           AArch64::STPQi, AArch64::STPQi, AArch64::FPR128RegClass),
134     RuleST4(AArch64::ST4Fourv4h, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
135           AArch64::ZIP1v4i16, AArch64::ZIP2v4i16, AArch64::ZIP1v4i16,
136           AArch64::ZIP2v4i16, AArch64::ZIP1v4i16, AArch64::ZIP2v4i16,
137           AArch64::STPDi, AArch64::STPDi, AArch64::FPR64RegClass),
138     RuleST4(AArch64::ST4Fourv16b, AArch64::ZIP1v16i8, AArch64::ZIP2v16i8,
139           AArch64::ZIP1v16i8, AArch64::ZIP2v16i8, AArch64::ZIP1v16i8,
140           AArch64::ZIP2v16i8, AArch64::ZIP1v16i8, AArch64::ZIP2v16i8,
141           AArch64::STPQi, AArch64::STPQi, AArch64::FPR128RegClass),
142     RuleST4(AArch64::ST4Fourv8b, AArch64::ZIP1v8i8, AArch64::ZIP2v8i8,
143           AArch64::ZIP1v8i8, AArch64::ZIP2v8i8, AArch64::ZIP1v8i8,
144           AArch64::ZIP2v8i8, AArch64::ZIP1v8i8, AArch64::ZIP2v8i8,
145           AArch64::STPDi, AArch64::STPDi, AArch64::FPR64RegClass)
283     OriginalMCID = &TII->get(AArch64::FMLAv4i32_indexed);  in shouldExitEarly()
284     ReplInstrMCID.push_back(&TII->get(AArch64::DUPv4i32lane));  in shouldExitEarly()
285     ReplInstrMCID.push_back(&TII->get(AArch64::FMLAv4f32));  in shouldExitEarly()
355   const TargetRegisterClass *RC = &AArch64::FPR128RegClass;  in optimizeVectElement()
362   case AArch64::FMLAv4i32_indexed:  in optimizeVectElement()
363     DupMCID = &TII->get(AArch64::DUPv4i32lane);  in optimizeVectElement()
364     MulMCID = &TII->get(AArch64::FMLAv4f32);  in optimizeVectElement()
366   case AArch64::FMLSv4i32_indexed:  in optimizeVectElement()
367     DupMCID = &TII->get(AArch64::DUPv4i32lane);  in optimizeVectElement()
368     MulMCID = &TII->get(AArch64::FMLSv4f32);  in optimizeVectElement()
370   case AArch64::FMULXv4i32_indexed:  in optimizeVectElement()
371     DupMCID = &TII->get(AArch64::DUPv4i32lane);  in optimizeVectElement()
372     MulMCID = &TII->get(AArch64::FMULXv4f32);  in optimizeVectElement()
374   case AArch64::FMULv4i32_indexed:  in optimizeVectElement()
375     DupMCID = &TII->get(AArch64::DUPv4i32lane);  in optimizeVectElement()
376     MulMCID = &TII->get(AArch64::FMULv4f32);  in optimizeVectElement()
380   case AArch64::FMLAv2i64_indexed:  in optimizeVectElement()
381     DupMCID = &TII->get(AArch64::DUPv2i64lane);  in optimizeVectElement()
382     MulMCID = &TII->get(AArch64::FMLAv2f64);  in optimizeVectElement()
384   case AArch64::FMLSv2i64_indexed:  in optimizeVectElement()
385     DupMCID = &TII->get(AArch64::DUPv2i64lane);  in optimizeVectElement()
386     MulMCID = &TII->get(AArch64::FMLSv2f64);  in optimizeVectElement()
388   case AArch64::FMULXv2i64_indexed:  in optimizeVectElement()
389     DupMCID = &TII->get(AArch64::DUPv2i64lane);  in optimizeVectElement()
390     MulMCID = &TII->get(AArch64::FMULXv2f64);  in optimizeVectElement()
392   case AArch64::FMULv2i64_indexed:  in optimizeVectElement()
393     DupMCID = &TII->get(AArch64::DUPv2i64lane);  in optimizeVectElement()
394     MulMCID = &TII->get(AArch64::FMULv2f64);  in optimizeVectElement()
398   case AArch64::FMLAv2i32_indexed:  in optimizeVectElement()
399     RC = &AArch64::FPR64RegClass;  in optimizeVectElement()
400     DupMCID = &TII->get(AArch64::DUPv2i32lane);  in optimizeVectElement()
401     MulMCID = &TII->get(AArch64::FMLAv2f32);  in optimizeVectElement()
403   case AArch64::FMLSv2i32_indexed:  in optimizeVectElement()
404     RC = &AArch64::FPR64RegClass;  in optimizeVectElement()
405     DupMCID = &TII->get(AArch64::DUPv2i32lane);  in optimizeVectElement()
406     MulMCID = &TII->get(AArch64::FMLSv2f32);  in optimizeVectElement()
408   case AArch64::FMULXv2i32_indexed:  in optimizeVectElement()
409     RC = &AArch64::FPR64RegClass;  in optimizeVectElement()
410     DupMCID = &TII->get(AArch64::DUPv2i32lane);  in optimizeVectElement()
411     MulMCID = &TII->get(AArch64::FMULXv2f32);  in optimizeVectElement()
413   case AArch64::FMULv2i32_indexed:  in optimizeVectElement()
414     RC = &AArch64::FPR64RegClass;  in optimizeVectElement()
415     DupMCID = &TII->get(AArch64::DUPv2i32lane);  in optimizeVectElement()
416     MulMCID = &TII->get(AArch64::FMULv2f32);  in optimizeVectElement()
530         if (Repl != AArch64::STPQi && Repl != AArch64::STPDi)  in optimizeLdStInterleave()
557   case AArch64::ST2Twov16b:  in optimizeLdStInterleave()
558   case AArch64::ST2Twov8b:  in optimizeLdStInterleave()
559   case AArch64::ST2Twov8h:  in optimizeLdStInterleave()
560   case AArch64::ST2Twov4h:  in optimizeLdStInterleave()
561   case AArch64::ST2Twov4s:  in optimizeLdStInterleave()
562   case AArch64::ST2Twov2s:  in optimizeLdStInterleave()
563   case AArch64::ST2Twov2d:  in optimizeLdStInterleave()
579   case AArch64::ST4Fourv16b:  in optimizeLdStInterleave()
580   case AArch64::ST4Fourv8b:  in optimizeLdStInterleave()
581   case AArch64::ST4Fourv8h:  in optimizeLdStInterleave()
582   case AArch64::ST4Fourv4h:  in optimizeLdStInterleave()
583   case AArch64::ST4Fourv4s:  in optimizeLdStInterleave()
584   case AArch64::ST4Fourv2s:  in optimizeLdStInterleave()
585   case AArch64::ST4Fourv2d:  in optimizeLdStInterleave()
637   if (DefiningMI->getOpcode() != AArch64::REG_SEQUENCE)  in processSeqRegInst()
650       case AArch64::dsub0:  in processSeqRegInst()
651       case AArch64::dsub1:  in processSeqRegInst()
652       case AArch64::dsub2:  in processSeqRegInst()
653       case AArch64::dsub3:  in processSeqRegInst()
654       case AArch64::qsub0:  in processSeqRegInst()
655       case AArch64::qsub1:  in processSeqRegInst()
656       case AArch64::qsub2:  in processSeqRegInst()
657       case AArch64::qsub3:  in processSeqRegInst()
674   case AArch64::ST2Twov16b:  in determineSrcReg()
675   case AArch64::ST2Twov8b:  in determineSrcReg()
676   case AArch64::ST2Twov8h:  in determineSrcReg()
677   case AArch64::ST2Twov4h:  in determineSrcReg()
678   case AArch64::ST2Twov4s:  in determineSrcReg()
679   case AArch64::ST2Twov2s:  in determineSrcReg()
680   case AArch64::ST2Twov2d:  in determineSrcReg()
683   case AArch64::ST4Fourv16b:  in determineSrcReg()
684   case AArch64::ST4Fourv8b:  in determineSrcReg()
685   case AArch64::ST4Fourv8h:  in determineSrcReg()
686   case AArch64::ST4Fourv4h:  in determineSrcReg()
687   case AArch64::ST4Fourv4s:  in determineSrcReg()
688   case AArch64::ST4Fourv2s:  in determineSrcReg()
689   case AArch64::ST4Fourv2d:  in determineSrcReg()