Lines Matching refs:AArch64
358 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca()
359 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), in fastMaterializeAlloca()
378 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()
379 : &AArch64::GPR32RegClass; in materializeInt()
380 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt()
403 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP()
409 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm; in materializeFP()
411 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
430 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeFP()
431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in materializeFP()
434 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP()
458 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in materializeGV()
463 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in materializeGV()
469 ResultReg = createResultReg(&AArch64::GPR32RegClass); in materializeGV()
470 LdrOpc = AArch64::LDRWui; in materializeGV()
472 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
473 LdrOpc = AArch64::LDRXui; in materializeGV()
485 unsigned Result64 = createResultReg(&AArch64::GPR64RegClass); in materializeGV()
491 .addImm(AArch64::sub_32); in materializeGV()
495 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in materializeGV()
499 ResultReg = createResultReg(&AArch64::GPR64spRegClass); in materializeGV()
500 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), in materializeGV()
545 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in fastMaterializeFloatZero()
546 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero()
757 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, AArch64::sub_32); in computeAddress()
853 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, AArch64::sub_32); in computeAddress()
1037 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in simplifyAddress()
1038 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri), in simplifyAddress()
1285 if (LHSReg == AArch64::SP || LHSReg == AArch64::WSP || in emitAddSub_rr()
1286 RHSReg == AArch64::SP || RHSReg == AArch64::WSP) in emitAddSub_rr()
1293 { { AArch64::SUBWrr, AArch64::SUBXrr }, in emitAddSub_rr()
1294 { AArch64::ADDWrr, AArch64::ADDXrr } }, in emitAddSub_rr()
1295 { { AArch64::SUBSWrr, AArch64::SUBSXrr }, in emitAddSub_rr()
1296 { AArch64::ADDSWrr, AArch64::ADDSXrr } } in emitAddSub_rr()
1301 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1306 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rr()
1335 { { AArch64::SUBWri, AArch64::SUBXri }, in emitAddSub_ri()
1336 { AArch64::ADDWri, AArch64::ADDXri } }, in emitAddSub_ri()
1337 { { AArch64::SUBSWri, AArch64::SUBSXri }, in emitAddSub_ri()
1338 { AArch64::ADDSWri, AArch64::ADDSXri } } in emitAddSub_ri()
1344 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1346 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass; in emitAddSub_ri()
1351 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_ri()
1368 assert(LHSReg != AArch64::SP && LHSReg != AArch64::WSP && in emitAddSub_rs()
1369 RHSReg != AArch64::SP && RHSReg != AArch64::WSP); in emitAddSub_rs()
1379 { { AArch64::SUBWrs, AArch64::SUBXrs }, in emitAddSub_rs()
1380 { AArch64::ADDWrs, AArch64::ADDXrs } }, in emitAddSub_rs()
1381 { { AArch64::SUBSWrs, AArch64::SUBSXrs }, in emitAddSub_rs()
1382 { AArch64::ADDSWrs, AArch64::ADDSXrs } } in emitAddSub_rs()
1387 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1392 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rs()
1410 assert(LHSReg != AArch64::XZR && LHSReg != AArch64::WZR && in emitAddSub_rx()
1411 RHSReg != AArch64::XZR && RHSReg != AArch64::WZR); in emitAddSub_rx()
1420 { { AArch64::SUBWrx, AArch64::SUBXrx }, in emitAddSub_rx()
1421 { AArch64::ADDWrx, AArch64::ADDXrx } }, in emitAddSub_rx()
1422 { { AArch64::SUBSWrx, AArch64::SUBSXrx }, in emitAddSub_rx()
1423 { AArch64::ADDSWrx, AArch64::ADDSXrx } } in emitAddSub_rx()
1429 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1431 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass; in emitAddSub_rx()
1436 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in emitAddSub_rx()
1497 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1507 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1646 { AArch64::ANDWri, AArch64::ANDXri }, in emitLogicalOp_ri()
1647 { AArch64::ORRWri, AArch64::ORRXri }, in emitLogicalOp_ri()
1648 { AArch64::EORWri, AArch64::EORXri } in emitLogicalOp_ri()
1662 RC = &AArch64::GPR32spRegClass; in emitLogicalOp_ri()
1668 RC = &AArch64::GPR64spRegClass; in emitLogicalOp_ri()
1692 { AArch64::ANDWrs, AArch64::ANDXrs }, in emitLogicalOp_rs()
1693 { AArch64::ORRWrs, AArch64::ORRXrs }, in emitLogicalOp_rs()
1694 { AArch64::EORWrs, AArch64::EORXrs } in emitLogicalOp_rs()
1711 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1715 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()
1756 { { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURWi, in emitLoad()
1757 AArch64::LDURXi }, in emitLoad()
1758 { AArch64::LDURSBXi, AArch64::LDURSHXi, AArch64::LDURSWi, in emitLoad()
1759 AArch64::LDURXi }, in emitLoad()
1760 { AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRWui, in emitLoad()
1761 AArch64::LDRXui }, in emitLoad()
1762 { AArch64::LDRSBXui, AArch64::LDRSHXui, AArch64::LDRSWui, in emitLoad()
1763 AArch64::LDRXui }, in emitLoad()
1764 { AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRWroX, in emitLoad()
1765 AArch64::LDRXroX }, in emitLoad()
1766 { AArch64::LDRSBXroX, AArch64::LDRSHXroX, AArch64::LDRSWroX, in emitLoad()
1767 AArch64::LDRXroX }, in emitLoad()
1768 { AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRWroW, in emitLoad()
1769 AArch64::LDRXroW }, in emitLoad()
1770 { AArch64::LDRSBXroW, AArch64::LDRSHXroW, AArch64::LDRSWroW, in emitLoad()
1771 AArch64::LDRXroW } in emitLoad()
1774 { { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, in emitLoad()
1775 AArch64::LDURXi }, in emitLoad()
1776 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, in emitLoad()
1777 AArch64::LDURXi }, in emitLoad()
1778 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, in emitLoad()
1779 AArch64::LDRXui }, in emitLoad()
1780 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, in emitLoad()
1781 AArch64::LDRXui }, in emitLoad()
1782 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, in emitLoad()
1783 AArch64::LDRXroX }, in emitLoad()
1784 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, in emitLoad()
1785 AArch64::LDRXroX }, in emitLoad()
1786 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, in emitLoad()
1787 AArch64::LDRXroW }, in emitLoad()
1788 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, in emitLoad()
1789 AArch64::LDRXroW } in emitLoad()
1794 { AArch64::LDURSi, AArch64::LDURDi }, in emitLoad()
1795 { AArch64::LDRSui, AArch64::LDRDui }, in emitLoad()
1796 { AArch64::LDRSroX, AArch64::LDRDroX }, in emitLoad()
1797 { AArch64::LDRSroW, AArch64::LDRDroW } in emitLoad()
1817 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1822 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1827 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1831 RC = &AArch64::GPR64RegClass; in emitLoad()
1835 RC = &AArch64::FPR32RegClass; in emitLoad()
1839 RC = &AArch64::FPR64RegClass; in emitLoad()
1859 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad()
1861 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1864 .addImm(AArch64::sub_32); in emitLoad()
2005 AArch64::sub_32); in selectLoad()
2042 case MVT::i8: Opc = AArch64::STLRB; break; in emitStoreRelease()
2043 case MVT::i16: Opc = AArch64::STLRH; break; in emitStoreRelease()
2044 case MVT::i32: Opc = AArch64::STLRW; break; in emitStoreRelease()
2045 case MVT::i64: Opc = AArch64::STLRX; break; in emitStoreRelease()
2080 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi, in emitStore()
2081 AArch64::STURSi, AArch64::STURDi }, in emitStore()
2082 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui, in emitStore()
2083 AArch64::STRSui, AArch64::STRDui }, in emitStore()
2084 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX, in emitStore()
2085 AArch64::STRSroX, AArch64::STRDroX }, in emitStore()
2086 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW, in emitStore()
2087 AArch64::STRSroW, AArch64::STRDroW } in emitStore()
2111 if (VTIsi1 && SrcReg != AArch64::WZR) { in emitStore()
2155 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2159 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectStore()
2328 { {AArch64::CBZW, AArch64::CBZX }, in emitCompareAndBranch()
2329 {AArch64::CBNZW, AArch64::CBNZX} }, in emitCompareAndBranch()
2330 { {AArch64::TBZW, AArch64::TBZX }, in emitCompareAndBranch()
2331 {AArch64::TBNZW, AArch64::TBNZX} } in emitCompareAndBranch()
2347 SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, AArch64::sub_32); in emitCompareAndBranch()
2425 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc)) in selectBranch()
2431 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc)) in selectBranch()
2441 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B)) in selectBranch()
2462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc)) in selectBranch()
2476 unsigned Opcode = AArch64::TBNZW; in selectBranch()
2479 Opcode = AArch64::TBZW; in selectBranch()
2501 const MCInstrDesc &II = TII.get(AArch64::BR); in selectIndirectBr()
2526 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2529 .addReg(AArch64::WZR, getKillRegState(true)); in selectCmp()
2545 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2566 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass); in selectCmp()
2567 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr), in selectCmp()
2569 .addReg(AArch64::WZR, getKillRegState(true)) in selectCmp()
2570 .addReg(AArch64::WZR, getKillRegState(true)) in selectCmp()
2572 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr), in selectCmp()
2575 .addReg(AArch64::WZR, getKillRegState(true)) in selectCmp()
2586 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr), in selectCmp()
2588 .addReg(AArch64::WZR, getKillRegState(true)) in selectCmp()
2589 .addReg(AArch64::WZR, getKillRegState(true)) in selectCmp()
2609 Opc = AArch64::ORRWrr; in optimizeSelect()
2614 Opc = AArch64::BICWrr; in optimizeSelect()
2620 Opc = AArch64::ORRWrr; in optimizeSelect()
2626 Opc = AArch64::ANDWrr; in optimizeSelect()
2644 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2665 Opc = AArch64::CSELWr; in selectSelect()
2666 RC = &AArch64::GPR32RegClass; in selectSelect()
2669 Opc = AArch64::CSELXr; in selectSelect()
2670 RC = &AArch64::GPR64RegClass; in selectSelect()
2673 Opc = AArch64::FCSELSrrr; in selectSelect()
2674 RC = &AArch64::FPR32RegClass; in selectSelect()
2677 Opc = AArch64::FCSELDrrr; in selectSelect()
2678 RC = &AArch64::FPR64RegClass; in selectSelect()
2746 const MCInstrDesc &II = TII.get(AArch64::ANDSWri); in selectSelect()
2751 AArch64::WZR) in selectSelect()
2779 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass); in selectFPExt()
2780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr), in selectFPExt()
2795 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass); in selectFPTrunc()
2796 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr), in selectFPTrunc()
2819 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2821 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2824 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2826 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2829 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2864 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri; in selectIntToFP()
2866 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri; in selectIntToFP()
2869 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri; in selectIntToFP()
2871 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri; in selectIntToFP()
2936 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, in fastLowerArguments()
2937 AArch64::W5, AArch64::W6, AArch64::W7 }, in fastLowerArguments()
2938 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, in fastLowerArguments()
2939 AArch64::X5, AArch64::X6, AArch64::X7 }, in fastLowerArguments()
2940 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, in fastLowerArguments()
2941 AArch64::H5, AArch64::H6, AArch64::H7 }, in fastLowerArguments()
2942 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, in fastLowerArguments()
2943 AArch64::S5, AArch64::S6, AArch64::S7 }, in fastLowerArguments()
2944 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, in fastLowerArguments()
2945 AArch64::D5, AArch64::D6, AArch64::D7 }, in fastLowerArguments()
2946 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, in fastLowerArguments()
2947 AArch64::Q5, AArch64::Q6, AArch64::Q7 } in fastLowerArguments()
2958 RC = &AArch64::GPR32RegClass; in fastLowerArguments()
2962 RC = &AArch64::GPR64RegClass; in fastLowerArguments()
2965 RC = &AArch64::FPR16RegClass; in fastLowerArguments()
2968 RC = &AArch64::FPR32RegClass; in fastLowerArguments()
2971 RC = &AArch64::FPR64RegClass; in fastLowerArguments()
2974 RC = &AArch64::FPR128RegClass; in fastLowerArguments()
3066 Addr.setReg(AArch64::SP); in processCallArgs()
3205 TII.get(Addr.getReg() ? getBLRCallOpcode(*MF) : (unsigned)AArch64::BL); in fastLowerCall()
3219 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass); in fastLowerCall()
3220 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP), in fastLowerCall()
3224 CallReg = createResultReg(&AArch64::GPR64RegClass); in fastLowerCall()
3226 TII.get(AArch64::LDRXui), CallReg) in fastLowerCall()
3416 Register SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in fastLowerIntrinsicCall()
3427 DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass, in fastLowerIntrinsicCall()
3441 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastLowerIntrinsicCall()
3443 TII.get(AArch64::ADDXri), ResultReg) in fastLowerIntrinsicCall()
3565 Opc = AArch64::FABSSr; in fastLowerIntrinsicCall()
3568 Opc = AArch64::FABSDr; in fastLowerIntrinsicCall()
3581 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK)) in fastLowerIntrinsicCall()
3585 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK)) in fastLowerIntrinsicCall()
3685 fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3716 TII.get(AArch64::ANDSXri), AArch64::XZR) in fastLowerIntrinsicCall()
3719 MulReg = fastEmitInst_extractsubreg(VT, MulReg, AArch64::sub_32); in fastLowerIntrinsicCall()
3726 emitSubs_rr(VT, AArch64::XZR, UMULHReg, /*WantResult=*/false); in fastLowerIntrinsicCall()
3741 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass, in fastLowerIntrinsicCall()
3742 AArch64::WZR, AArch64::WZR, in fastLowerIntrinsicCall()
3854 TII.get(AArch64::RET_ReallyLR)); in selectRet()
3910 AArch64::sub_32); in selectTrunc()
3915 ResultReg = createResultReg(&AArch64::GPR32RegClass); in selectTrunc()
3939 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext()
3941 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3944 .addImm(AArch64::sub_32); in emiti1Ext()
3953 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg, in emiti1Ext()
3966 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
3968 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
3972 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
3980 return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass, in emitSMULL_rr()
3981 Op0, Op1, AArch64::XZR); in emitSMULL_rr()
3988 return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass, in emitUMULL_rr()
3989 Op0, Op1, AArch64::XZR); in emitUMULL_rr()
3999 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSL_rr()
4000 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSL_rr()
4001 case MVT::i32: Opc = AArch64::LSLVWr; break; in emitLSL_rr()
4002 case MVT::i64: Opc = AArch64::LSLVXr; break; in emitLSL_rr()
4006 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4031 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_ri()
4078 {AArch64::SBFMWri, AArch64::SBFMXri}, in emitLSL_ri()
4079 {AArch64::UBFMWri, AArch64::UBFMXri} in emitLSL_ri()
4085 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSL_ri()
4088 .addImm(AArch64::sub_32); in emitLSL_ri()
4101 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSR_rr()
4102 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSR_rr()
4103 case MVT::i32: Opc = AArch64::LSRVWr; break; in emitLSR_rr()
4104 case MVT::i64: Opc = AArch64::LSRVXr; break; in emitLSR_rr()
4108 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4134 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_ri()
4194 {AArch64::SBFMWri, AArch64::SBFMXri}, in emitLSR_ri()
4195 {AArch64::UBFMWri, AArch64::UBFMXri} in emitLSR_ri()
4201 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitLSR_ri()
4204 .addImm(AArch64::sub_32); in emitLSR_ri()
4217 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break; in emitASR_rr()
4218 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitASR_rr()
4219 case MVT::i32: Opc = AArch64::ASRVWr; break; in emitASR_rr()
4220 case MVT::i64: Opc = AArch64::ASRVXr; break; in emitASR_rr()
4224 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4250 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_ri()
4299 {AArch64::SBFMWri, AArch64::SBFMXri}, in emitASR_ri()
4300 {AArch64::UBFMWri, AArch64::UBFMXri} in emitASR_ri()
4306 TII.get(AArch64::SUBREG_TO_REG), TmpReg) in emitASR_ri()
4309 .addImm(AArch64::sub_32); in emitASR_ri()
4339 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4341 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4346 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4348 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4353 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4362 Register Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emitIntExt()
4364 TII.get(AArch64::SUBREG_TO_REG), Src64) in emitIntExt()
4367 .addImm(AArch64::sub_32); in emitIntExt()
4372 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitIntExt()
4380 case AArch64::LDURBBi: in isZExtLoad()
4381 case AArch64::LDURHHi: in isZExtLoad()
4382 case AArch64::LDURWi: in isZExtLoad()
4383 case AArch64::LDRBBui: in isZExtLoad()
4384 case AArch64::LDRHHui: in isZExtLoad()
4385 case AArch64::LDRWui: in isZExtLoad()
4386 case AArch64::LDRBBroX: in isZExtLoad()
4387 case AArch64::LDRHHroX: in isZExtLoad()
4388 case AArch64::LDRWroX: in isZExtLoad()
4389 case AArch64::LDRBBroW: in isZExtLoad()
4390 case AArch64::LDRHHroW: in isZExtLoad()
4391 case AArch64::LDRWroW: in isZExtLoad()
4400 case AArch64::LDURSBWi: in isSExtLoad()
4401 case AArch64::LDURSHWi: in isSExtLoad()
4402 case AArch64::LDURSBXi: in isSExtLoad()
4403 case AArch64::LDURSHXi: in isSExtLoad()
4404 case AArch64::LDURSWi: in isSExtLoad()
4405 case AArch64::LDRSBWui: in isSExtLoad()
4406 case AArch64::LDRSHWui: in isSExtLoad()
4407 case AArch64::LDRSBXui: in isSExtLoad()
4408 case AArch64::LDRSHXui: in isSExtLoad()
4409 case AArch64::LDRSWui: in isSExtLoad()
4410 case AArch64::LDRSBWroX: in isSExtLoad()
4411 case AArch64::LDRSHWroX: in isSExtLoad()
4412 case AArch64::LDRSBXroX: in isSExtLoad()
4413 case AArch64::LDRSHXroX: in isSExtLoad()
4414 case AArch64::LDRSWroX: in isSExtLoad()
4415 case AArch64::LDRSBWroW: in isSExtLoad()
4416 case AArch64::LDRSHWroW: in isSExtLoad()
4417 case AArch64::LDRSBXroW: in isSExtLoad()
4418 case AArch64::LDRSHXroW: in isSExtLoad()
4419 case AArch64::LDRSWroW: in isSExtLoad()
4444 LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) { in optimizeIntExtLoad()
4459 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad()
4461 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4464 .addImm(AArch64::sub_32); in optimizeIntExtLoad()
4468 MI->getOperand(1).getSubReg() == AArch64::sub_32) && in optimizeIntExtLoad()
4502 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass); in selectIntExt()
4504 TII.get(AArch64::SUBREG_TO_REG), ResultReg) in selectIntExt()
4507 .addImm(AArch64::sub_32); in selectIntExt()
4539 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr; in selectRem()
4542 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr; in selectRem()
4545 unsigned MSubOpc = Is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr; in selectRem()
4555 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in selectRem()
4731 Opc = AArch64::FMOVWSr; in selectBitCast()
4733 Opc = AArch64::FMOVXDr; in selectBitCast()
4735 Opc = AArch64::FMOVSWr; in selectBitCast()
4737 Opc = AArch64::FMOVDXr; in selectBitCast()
4744 case MVT::i32: RC = &AArch64::GPR32RegClass; break; in selectBitCast()
4745 case MVT::i64: RC = &AArch64::GPR64RegClass; break; in selectBitCast()
4746 case MVT::f32: RC = &AArch64::FPR32RegClass; break; in selectBitCast()
4747 case MVT::f64: RC = &AArch64::FPR64RegClass; break; in selectBitCast()
4837 SelectOpc = AArch64::CSELXr; in selectSDiv()
4838 RC = &AArch64::GPR64RegClass; in selectSDiv()
4840 SelectOpc = AArch64::CSELWr; in selectSDiv()
4841 RC = &AArch64::GPR32RegClass; in selectSDiv()
4850 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv()
4973 Opc = AArch64::CMP_SWAP_32; in selectAtomicCmpXchg()
4974 CmpOpc = AArch64::SUBSWrs; in selectAtomicCmpXchg()
4975 ResRC = &AArch64::GPR32RegClass; in selectAtomicCmpXchg()
4977 Opc = AArch64::CMP_SWAP_64; in selectAtomicCmpXchg()
4978 CmpOpc = AArch64::SUBSXrs; in selectAtomicCmpXchg()
4979 ResRC = &AArch64::GPR64RegClass; in selectAtomicCmpXchg()
4994 const unsigned ResultReg2 = createResultReg(&AArch64::GPR32RegClass); in selectAtomicCmpXchg()
4995 const unsigned ScratchReg = createResultReg(&AArch64::GPR32RegClass); in selectAtomicCmpXchg()
5006 .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR) in selectAtomicCmpXchg()
5011 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr)) in selectAtomicCmpXchg()
5013 .addUse(AArch64::WZR) in selectAtomicCmpXchg()
5014 .addUse(AArch64::WZR) in selectAtomicCmpXchg()
5103 FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo, in createFastISel()