87                             ? AArch64::SpeculationBarrierSBEndBB  in insertSpeculationBarrier()
88                             : AArch64::SpeculationBarrierISBDSBEndBB;  in insertSpeculationBarrier()
90       (MBBI->getOpcode() != AArch64::SpeculationBarrierSBEndBB &&  in insertSpeculationBarrier()
91        MBBI->getOpcode() != AArch64::SpeculationBarrierISBDSBEndBB))  in insertSpeculationBarrier()
111   case AArch64::BLR:  in isBLR()
112   case AArch64::BLRNoIP:  in isBLR()
114   case AArch64::BLRAA:  in isBLR()
115   case AArch64::BLRAB:  in isBLR()
116   case AArch64::BLRAAZ:  in isBLR()
117   case AArch64::BLRABZ:  in isBLR()
149   { "__llvm_slsblr_thunk_x0",  AArch64::X0},
150   { "__llvm_slsblr_thunk_x1",  AArch64::X1},
151   { "__llvm_slsblr_thunk_x2",  AArch64::X2},
152   { "__llvm_slsblr_thunk_x3",  AArch64::X3},
153   { "__llvm_slsblr_thunk_x4",  AArch64::X4},
154   { "__llvm_slsblr_thunk_x5",  AArch64::X5},
155   { "__llvm_slsblr_thunk_x6",  AArch64::X6},
156   { "__llvm_slsblr_thunk_x7",  AArch64::X7},
157   { "__llvm_slsblr_thunk_x8",  AArch64::X8},
158   { "__llvm_slsblr_thunk_x9",  AArch64::X9},
159   { "__llvm_slsblr_thunk_x10",  AArch64::X10},
160   { "__llvm_slsblr_thunk_x11",  AArch64::X11},
161   { "__llvm_slsblr_thunk_x12",  AArch64::X12},
162   { "__llvm_slsblr_thunk_x13",  AArch64::X13},
163   { "__llvm_slsblr_thunk_x14",  AArch64::X14},
164   { "__llvm_slsblr_thunk_x15",  AArch64::X15},
168   { "__llvm_slsblr_thunk_x18",  AArch64::X18},
169   { "__llvm_slsblr_thunk_x19",  AArch64::X19},
170   { "__llvm_slsblr_thunk_x20",  AArch64::X20},
171   { "__llvm_slsblr_thunk_x21",  AArch64::X21},
172   { "__llvm_slsblr_thunk_x22",  AArch64::X22},
173   { "__llvm_slsblr_thunk_x23",  AArch64::X23},
174   { "__llvm_slsblr_thunk_x24",  AArch64::X24},
175   { "__llvm_slsblr_thunk_x25",  AArch64::X25},
176   { "__llvm_slsblr_thunk_x26",  AArch64::X26},
177   { "__llvm_slsblr_thunk_x27",  AArch64::X27},
178   { "__llvm_slsblr_thunk_x28",  AArch64::X28},
179   { "__llvm_slsblr_thunk_x29",  AArch64::FP},
182   { "__llvm_slsblr_thunk_x31",  AArch64::XZR},
231   BuildMI(Entry, DebugLoc(), TII->get(AArch64::ORRXrs), AArch64::X16)  in populateThunk()
232       .addReg(AArch64::XZR)  in populateThunk()
235   BuildMI(Entry, DebugLoc(), TII->get(AArch64::BR)).addReg(AArch64::X16);  in populateThunk()
287   case AArch64::BLR:  in ConvertBLRToBL()
288   case AArch64::BLRNoIP:  in ConvertBLRToBL()
289     BLOpcode = AArch64::BL;  in ConvertBLRToBL()
291     assert(Reg != AArch64::X16 && Reg != AArch64::X17 && Reg != AArch64::LR);  in ConvertBLRToBL()
294   case AArch64::BLRAA:  in ConvertBLRToBL()
295   case AArch64::BLRAB:  in ConvertBLRToBL()
296   case AArch64::BLRAAZ:  in ConvertBLRToBL()
297   case AArch64::BLRABZ:  in ConvertBLRToBL()
354     if (Op.getReg() == AArch64::LR && Op.isDef())  in ConvertBLRToBL()
356     if (Op.getReg() == AArch64::SP && !Op.isDef())  in ConvertBLRToBL()