Searched refs:PCH_PP_CONTROL (Results 1 – 5 of 5) sorted by relevance
314 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; in ironlake_edp_have_panel_vdd()329 I915_READ(PCH_PP_CONTROL)); in intel_dp_check_edp()973 I915_READ(PCH_PP_CONTROL)); in ironlake_wait_panel_status()978 I915_READ(PCH_PP_CONTROL)); in ironlake_wait_panel_status()1007 u32 control = I915_READ(PCH_PP_CONTROL); in ironlake_get_pp_control()1039 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_vdd_on()1040 POSTING_READ(PCH_PP_CONTROL); in ironlake_edp_panel_vdd_on()1042 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); in ironlake_edp_panel_vdd_on()1062 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_panel_vdd_off_sync()1063 POSTING_READ(PCH_PP_CONTROL); in ironlake_panel_vdd_off_sync()[all …]
107 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()150 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()1122 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()1123 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); in intel_lvds_init()
634 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()756 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
4039 #define PCH_PP_CONTROL 0xc7204 macro
1193 pp_reg = PCH_PP_CONTROL; in assert_panel_unlocked()