1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/drm_edid.h>
32 #include <dev/drm2/i915/intel_drv.h>
33 #include <dev/drm2/i915/i915_drm.h>
34 #include <dev/drm2/i915/i915_drv.h>
35 #include <dev/drm2/drm_dp_helper.h>
36 #include <dev/drm2/drm_crtc_helper.h>
37
38 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
39 static void intel_increase_pllclock(struct drm_crtc *crtc);
40 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
41
42 typedef struct {
43 /* given values */
44 int n;
45 int m1, m2;
46 int p1, p2;
47 /* derived values */
48 int dot;
49 int vco;
50 int m;
51 int p;
52 } intel_clock_t;
53
54 typedef struct {
55 int min, max;
56 } intel_range_t;
57
58 typedef struct {
59 int dot_limit;
60 int p2_slow, p2_fast;
61 } intel_p2_t;
62
63 #define INTEL_P2_NUM 2
64 typedef struct intel_limit intel_limit_t;
65 struct intel_limit {
66 intel_range_t dot, vco, n, m, m1, m2, p, p1;
67 intel_p2_t p2;
68 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
69 int, int, intel_clock_t *, intel_clock_t *);
70 };
71
72 /* FDI */
73 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
75 int
intel_pch_rawclk(struct drm_device * dev)76 intel_pch_rawclk(struct drm_device *dev)
77 {
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83 }
84
85 static bool
86 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *match_clock,
88 intel_clock_t *best_clock);
89 static bool
90 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *match_clock,
92 intel_clock_t *best_clock);
93
94 static bool
95 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *match_clock,
97 intel_clock_t *best_clock);
98 static bool
99 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
100 int target, int refclk, intel_clock_t *match_clock,
101 intel_clock_t *best_clock);
102
103 static bool
104 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
105 int target, int refclk, intel_clock_t *match_clock,
106 intel_clock_t *best_clock);
107
108 static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device * dev)109 intel_fdi_link_freq(struct drm_device *dev)
110 {
111 if (IS_GEN5(dev)) {
112 struct drm_i915_private *dev_priv = dev->dev_private;
113 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
114 } else
115 return 27;
116 }
117
118 static const intel_limit_t intel_limits_i8xx_dvo = {
119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 2, .max = 33 },
127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 4, .p2_fast = 2 },
129 .find_pll = intel_find_best_PLL,
130 };
131
132 static const intel_limit_t intel_limits_i8xx_lvds = {
133 .dot = { .min = 25000, .max = 350000 },
134 .vco = { .min = 930000, .max = 1400000 },
135 .n = { .min = 3, .max = 16 },
136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
143 .find_pll = intel_find_best_PLL,
144 };
145
146 static const intel_limit_t intel_limits_i9xx_sdvo = {
147 .dot = { .min = 20000, .max = 400000 },
148 .vco = { .min = 1400000, .max = 2800000 },
149 .n = { .min = 1, .max = 6 },
150 .m = { .min = 70, .max = 120 },
151 .m1 = { .min = 8, .max = 18 },
152 .m2 = { .min = 3, .max = 7 },
153 .p = { .min = 5, .max = 80 },
154 .p1 = { .min = 1, .max = 8 },
155 .p2 = { .dot_limit = 200000,
156 .p2_slow = 10, .p2_fast = 5 },
157 .find_pll = intel_find_best_PLL,
158 };
159
160 static const intel_limit_t intel_limits_i9xx_lvds = {
161 .dot = { .min = 20000, .max = 400000 },
162 .vco = { .min = 1400000, .max = 2800000 },
163 .n = { .min = 1, .max = 6 },
164 .m = { .min = 70, .max = 120 },
165 .m1 = { .min = 10, .max = 22 },
166 .m2 = { .min = 5, .max = 9 },
167 .p = { .min = 7, .max = 98 },
168 .p1 = { .min = 1, .max = 8 },
169 .p2 = { .dot_limit = 112000,
170 .p2_slow = 14, .p2_fast = 7 },
171 .find_pll = intel_find_best_PLL,
172 };
173
174
175 static const intel_limit_t intel_limits_g4x_sdvo = {
176 .dot = { .min = 25000, .max = 270000 },
177 .vco = { .min = 1750000, .max = 3500000},
178 .n = { .min = 1, .max = 4 },
179 .m = { .min = 104, .max = 138 },
180 .m1 = { .min = 17, .max = 23 },
181 .m2 = { .min = 5, .max = 11 },
182 .p = { .min = 10, .max = 30 },
183 .p1 = { .min = 1, .max = 3},
184 .p2 = { .dot_limit = 270000,
185 .p2_slow = 10,
186 .p2_fast = 10
187 },
188 .find_pll = intel_g4x_find_best_PLL,
189 };
190
191 static const intel_limit_t intel_limits_g4x_hdmi = {
192 .dot = { .min = 22000, .max = 400000 },
193 .vco = { .min = 1750000, .max = 3500000},
194 .n = { .min = 1, .max = 4 },
195 .m = { .min = 104, .max = 138 },
196 .m1 = { .min = 16, .max = 23 },
197 .m2 = { .min = 5, .max = 11 },
198 .p = { .min = 5, .max = 80 },
199 .p1 = { .min = 1, .max = 8},
200 .p2 = { .dot_limit = 165000,
201 .p2_slow = 10, .p2_fast = 5 },
202 .find_pll = intel_g4x_find_best_PLL,
203 };
204
205 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
206 .dot = { .min = 20000, .max = 115000 },
207 .vco = { .min = 1750000, .max = 3500000 },
208 .n = { .min = 1, .max = 3 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 28, .max = 112 },
213 .p1 = { .min = 2, .max = 8 },
214 .p2 = { .dot_limit = 0,
215 .p2_slow = 14, .p2_fast = 14
216 },
217 .find_pll = intel_g4x_find_best_PLL,
218 };
219
220 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
221 .dot = { .min = 80000, .max = 224000 },
222 .vco = { .min = 1750000, .max = 3500000 },
223 .n = { .min = 1, .max = 3 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 17, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 14, .max = 42 },
228 .p1 = { .min = 2, .max = 6 },
229 .p2 = { .dot_limit = 0,
230 .p2_slow = 7, .p2_fast = 7
231 },
232 .find_pll = intel_g4x_find_best_PLL,
233 };
234
235 static const intel_limit_t intel_limits_g4x_display_port = {
236 .dot = { .min = 161670, .max = 227000 },
237 .vco = { .min = 1750000, .max = 3500000},
238 .n = { .min = 1, .max = 2 },
239 .m = { .min = 97, .max = 108 },
240 .m1 = { .min = 0x10, .max = 0x12 },
241 .m2 = { .min = 0x05, .max = 0x06 },
242 .p = { .min = 10, .max = 20 },
243 .p1 = { .min = 1, .max = 2},
244 .p2 = { .dot_limit = 0,
245 .p2_slow = 10, .p2_fast = 10 },
246 .find_pll = intel_find_pll_g4x_dp,
247 };
248
249 static const intel_limit_t intel_limits_pineview_sdvo = {
250 .dot = { .min = 20000, .max = 400000},
251 .vco = { .min = 1700000, .max = 3500000 },
252 /* Pineview's Ncounter is a ring counter */
253 .n = { .min = 3, .max = 6 },
254 .m = { .min = 2, .max = 256 },
255 /* Pineview only has one combined m divider, which we treat as m2. */
256 .m1 = { .min = 0, .max = 0 },
257 .m2 = { .min = 0, .max = 254 },
258 .p = { .min = 5, .max = 80 },
259 .p1 = { .min = 1, .max = 8 },
260 .p2 = { .dot_limit = 200000,
261 .p2_slow = 10, .p2_fast = 5 },
262 .find_pll = intel_find_best_PLL,
263 };
264
265 static const intel_limit_t intel_limits_pineview_lvds = {
266 .dot = { .min = 20000, .max = 400000 },
267 .vco = { .min = 1700000, .max = 3500000 },
268 .n = { .min = 3, .max = 6 },
269 .m = { .min = 2, .max = 256 },
270 .m1 = { .min = 0, .max = 0 },
271 .m2 = { .min = 0, .max = 254 },
272 .p = { .min = 7, .max = 112 },
273 .p1 = { .min = 1, .max = 8 },
274 .p2 = { .dot_limit = 112000,
275 .p2_slow = 14, .p2_fast = 14 },
276 .find_pll = intel_find_best_PLL,
277 };
278
279 /* Ironlake / Sandybridge
280 *
281 * We calculate clock using (register_value + 2) for N/M1/M2, so here
282 * the range value for them is (actual_value - 2).
283 */
284 static const intel_limit_t intel_limits_ironlake_dac = {
285 .dot = { .min = 25000, .max = 350000 },
286 .vco = { .min = 1760000, .max = 3510000 },
287 .n = { .min = 1, .max = 5 },
288 .m = { .min = 79, .max = 127 },
289 .m1 = { .min = 12, .max = 22 },
290 .m2 = { .min = 5, .max = 9 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8 },
293 .p2 = { .dot_limit = 225000,
294 .p2_slow = 10, .p2_fast = 5 },
295 .find_pll = intel_g4x_find_best_PLL,
296 };
297
298 static const intel_limit_t intel_limits_ironlake_single_lvds = {
299 .dot = { .min = 25000, .max = 350000 },
300 .vco = { .min = 1760000, .max = 3510000 },
301 .n = { .min = 1, .max = 3 },
302 .m = { .min = 79, .max = 118 },
303 .m1 = { .min = 12, .max = 22 },
304 .m2 = { .min = 5, .max = 9 },
305 .p = { .min = 28, .max = 112 },
306 .p1 = { .min = 2, .max = 8 },
307 .p2 = { .dot_limit = 225000,
308 .p2_slow = 14, .p2_fast = 14 },
309 .find_pll = intel_g4x_find_best_PLL,
310 };
311
312 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
313 .dot = { .min = 25000, .max = 350000 },
314 .vco = { .min = 1760000, .max = 3510000 },
315 .n = { .min = 1, .max = 3 },
316 .m = { .min = 79, .max = 127 },
317 .m1 = { .min = 12, .max = 22 },
318 .m2 = { .min = 5, .max = 9 },
319 .p = { .min = 14, .max = 56 },
320 .p1 = { .min = 2, .max = 8 },
321 .p2 = { .dot_limit = 225000,
322 .p2_slow = 7, .p2_fast = 7 },
323 .find_pll = intel_g4x_find_best_PLL,
324 };
325
326 /* LVDS 100mhz refclk limits. */
327 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 2 },
331 .m = { .min = 79, .max = 126 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
338 .find_pll = intel_g4x_find_best_PLL,
339 };
340
341 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
342 .dot = { .min = 25000, .max = 350000 },
343 .vco = { .min = 1760000, .max = 3510000 },
344 .n = { .min = 1, .max = 3 },
345 .m = { .min = 79, .max = 126 },
346 .m1 = { .min = 12, .max = 22 },
347 .m2 = { .min = 5, .max = 9 },
348 .p = { .min = 14, .max = 42 },
349 .p1 = { .min = 2, .max = 6 },
350 .p2 = { .dot_limit = 225000,
351 .p2_slow = 7, .p2_fast = 7 },
352 .find_pll = intel_g4x_find_best_PLL,
353 };
354
355 static const intel_limit_t intel_limits_ironlake_display_port = {
356 .dot = { .min = 25000, .max = 350000 },
357 .vco = { .min = 1760000, .max = 3510000},
358 .n = { .min = 1, .max = 2 },
359 .m = { .min = 81, .max = 90 },
360 .m1 = { .min = 12, .max = 22 },
361 .m2 = { .min = 5, .max = 9 },
362 .p = { .min = 10, .max = 20 },
363 .p1 = { .min = 1, .max = 2},
364 .p2 = { .dot_limit = 0,
365 .p2_slow = 10, .p2_fast = 10 },
366 .find_pll = intel_find_pll_ironlake_dp,
367 };
368
369 static const intel_limit_t intel_limits_vlv_dac = {
370 .dot = { .min = 25000, .max = 270000 },
371 .vco = { .min = 4000000, .max = 6000000 },
372 .n = { .min = 1, .max = 7 },
373 .m = { .min = 22, .max = 450 }, /* guess */
374 .m1 = { .min = 2, .max = 3 },
375 .m2 = { .min = 11, .max = 156 },
376 .p = { .min = 10, .max = 30 },
377 .p1 = { .min = 2, .max = 3 },
378 .p2 = { .dot_limit = 270000,
379 .p2_slow = 2, .p2_fast = 20 },
380 .find_pll = intel_vlv_find_best_pll,
381 };
382
383 static const intel_limit_t intel_limits_vlv_hdmi = {
384 .dot = { .min = 20000, .max = 165000 },
385 .vco = { .min = 4000000, .max = 5994000},
386 .n = { .min = 1, .max = 7 },
387 .m = { .min = 60, .max = 300 }, /* guess */
388 .m1 = { .min = 2, .max = 3 },
389 .m2 = { .min = 11, .max = 156 },
390 .p = { .min = 10, .max = 30 },
391 .p1 = { .min = 2, .max = 3 },
392 .p2 = { .dot_limit = 270000,
393 .p2_slow = 2, .p2_fast = 20 },
394 .find_pll = intel_vlv_find_best_pll,
395 };
396
397 static const intel_limit_t intel_limits_vlv_dp = {
398 .dot = { .min = 25000, .max = 270000 },
399 .vco = { .min = 4000000, .max = 6000000 },
400 .n = { .min = 1, .max = 7 },
401 .m = { .min = 22, .max = 450 },
402 .m1 = { .min = 2, .max = 3 },
403 .m2 = { .min = 11, .max = 156 },
404 .p = { .min = 10, .max = 30 },
405 .p1 = { .min = 2, .max = 3 },
406 .p2 = { .dot_limit = 270000,
407 .p2_slow = 2, .p2_fast = 20 },
408 .find_pll = intel_vlv_find_best_pll,
409 };
410
intel_dpio_read(struct drm_i915_private * dev_priv,int reg)411 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
412 {
413 u32 val = 0;
414
415 sx_xlock(&dev_priv->dpio_lock);
416 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
417 DRM_ERROR("DPIO idle wait timed out\n");
418 goto out_unlock;
419 }
420
421 I915_WRITE(DPIO_REG, reg);
422 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
423 DPIO_BYTE);
424 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
425 DRM_ERROR("DPIO read wait timed out\n");
426 goto out_unlock;
427 }
428 val = I915_READ(DPIO_DATA);
429
430 out_unlock:
431 sx_xunlock(&dev_priv->dpio_lock);
432 return val;
433 }
434
intel_dpio_write(struct drm_i915_private * dev_priv,int reg,u32 val)435 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
436 u32 val)
437 {
438
439 sx_xlock(&dev_priv->dpio_lock);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 sx_xunlock(&dev_priv->dpio_lock);
454 }
455
vlv_init_dpio(struct drm_device * dev)456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
intel_dual_link_lvds_callback(const struct dmi_system_id * id)467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
is_dual_link_lvds(struct drm_i915_private * dev_priv,unsigned int reg)485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
intel_ironlake_limit(struct drm_crtc * crtc,int refclk)513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
intel_g4x_limit(struct drm_crtc * crtc)542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
intel_limit(struct drm_crtc * crtc,int refclk)568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
pineview_clock(int refclk,intel_clock_t * clock)604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
intel_clock(struct drm_device * dev,int refclk,intel_clock_t * clock)612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
intel_pipe_has_type(struct drm_crtc * crtc,int type)627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
intel_PLL_is_valid(struct drm_device * dev,const intel_limit_t * limit,const intel_clock_t * clock)645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
intel_find_best_PLL(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
intel_g4x_find_best_PLL(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
intel_find_pll_ironlake_dp(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
intel_find_pll_g4x_dp(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
intel_vlv_find_best_pll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
intel_pipe_to_cpu_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)930 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
931 enum pipe pipe)
932 {
933 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
935
936 return intel_crtc->cpu_transcoder;
937 }
938
ironlake_wait_for_vblank(struct drm_device * dev,int pipe)939 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
940 {
941 struct drm_i915_private *dev_priv = dev->dev_private;
942 u32 frame, frame_reg = PIPEFRAME(pipe);
943
944 frame = I915_READ(frame_reg);
945
946 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
947 DRM_DEBUG_KMS("vblank wait timed out\n");
948 }
949
950 /**
951 * intel_wait_for_vblank - wait for vblank on a given pipe
952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * Wait for vblank to occur on a given pipe. Needed for various bits of
956 * mode setting code.
957 */
intel_wait_for_vblank(struct drm_device * dev,int pipe)958 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
959 {
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 int pipestat_reg = PIPESTAT(pipe);
962
963 if (INTEL_INFO(dev)->gen >= 5) {
964 ironlake_wait_for_vblank(dev, pipe);
965 return;
966 }
967
968 /* Clear existing vblank status. Note this will clear any other
969 * sticky status fields as well.
970 *
971 * This races with i915_driver_irq_handler() with the result
972 * that either function could miss a vblank event. Here it is not
973 * fatal, as we will either wait upon the next vblank interrupt or
974 * timeout. Generally speaking intel_wait_for_vblank() is only
975 * called during modeset at which time the GPU should be idle and
976 * should *not* be performing page flips and thus not waiting on
977 * vblanks...
978 * Currently, the result of us stealing a vblank from the irq
979 * handler is that a single frame will be skipped during swapbuffers.
980 */
981 I915_WRITE(pipestat_reg,
982 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
983
984 /* Wait for vblank interrupt bit to set */
985 if (wait_for(I915_READ(pipestat_reg) &
986 PIPE_VBLANK_INTERRUPT_STATUS,
987 50))
988 DRM_DEBUG_KMS("vblank wait timed out\n");
989 }
990
991 /*
992 * intel_wait_for_pipe_off - wait for pipe to turn off
993 * @dev: drm device
994 * @pipe: pipe to wait for
995 *
996 * After disabling a pipe, we can't wait for vblank in the usual way,
997 * spinning on the vblank interrupt status bit, since we won't actually
998 * see an interrupt when the pipe is disabled.
999 *
1000 * On Gen4 and above:
1001 * wait for the pipe register state bit to turn off
1002 *
1003 * Otherwise:
1004 * wait for the display line value to settle (it usually
1005 * ends up stopping at the start of the next frame).
1006 *
1007 */
intel_wait_for_pipe_off(struct drm_device * dev,int pipe)1008 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1009 {
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1012 pipe);
1013
1014 if (INTEL_INFO(dev)->gen >= 4) {
1015 int reg = PIPECONF(cpu_transcoder);
1016
1017 /* Wait for the Pipe State to go off */
1018 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1019 100))
1020 WARN(1, "pipe_off wait timed out\n");
1021 } else {
1022 u32 last_line, line_mask;
1023 int reg = PIPEDSL(pipe);
1024 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1025
1026 if (IS_GEN2(dev))
1027 line_mask = DSL_LINEMASK_GEN2;
1028 else
1029 line_mask = DSL_LINEMASK_GEN3;
1030
1031 /* Wait for the display line to settle */
1032 do {
1033 last_line = I915_READ(reg) & line_mask;
1034 mdelay(5);
1035 } while (((I915_READ(reg) & line_mask) != last_line) &&
1036 time_after(timeout, jiffies));
1037 if (time_after(jiffies, timeout))
1038 WARN(1, "pipe_off wait timed out\n");
1039 }
1040 }
1041
state_string(bool enabled)1042 static const char *state_string(bool enabled)
1043 {
1044 return enabled ? "on" : "off";
1045 }
1046
1047 /* Only for pre-ILK configs */
assert_pll(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)1048 static void assert_pll(struct drm_i915_private *dev_priv,
1049 enum pipe pipe, bool state)
1050 {
1051 int reg;
1052 u32 val;
1053 bool cur_state;
1054
1055 reg = DPLL(pipe);
1056 val = I915_READ(reg);
1057 cur_state = !!(val & DPLL_VCO_ENABLE);
1058 WARN(cur_state != state,
1059 "PLL state assertion failure (expected %s, current %s)\n",
1060 state_string(state), state_string(cur_state));
1061 }
1062 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1063 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1064
1065 /* For ILK+ */
assert_pch_pll(struct drm_i915_private * dev_priv,struct intel_pch_pll * pll,struct intel_crtc * crtc,bool state)1066 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1067 struct intel_pch_pll *pll,
1068 struct intel_crtc *crtc,
1069 bool state)
1070 {
1071 u32 val;
1072 bool cur_state;
1073
1074 if (HAS_PCH_LPT(dev_priv->dev)) {
1075 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1076 return;
1077 }
1078
1079 if (WARN (!pll,
1080 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1081 return;
1082
1083 val = I915_READ(pll->pll_reg);
1084 cur_state = !!(val & DPLL_VCO_ENABLE);
1085 WARN(cur_state != state,
1086 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1087 pll->pll_reg, state_string(state), state_string(cur_state), val);
1088
1089 /* Make sure the selected PLL is correctly attached to the transcoder */
1090 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1091 u32 pch_dpll;
1092
1093 pch_dpll = I915_READ(PCH_DPLL_SEL);
1094 cur_state = pll->pll_reg == _PCH_DPLL_B;
1095 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1096 "PLL[%d] not attached to this transcoder %d: %08x\n",
1097 cur_state, crtc->pipe, pch_dpll)) {
1098 cur_state = !!(val >> (4*crtc->pipe + 3));
1099 WARN(cur_state != state,
1100 "PLL[%d] not %s on this transcoder %d: %08x\n",
1101 pll->pll_reg == _PCH_DPLL_B,
1102 state_string(state),
1103 crtc->pipe,
1104 val);
1105 }
1106 }
1107 }
1108 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1109 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1110
assert_fdi_tx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)1111 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1112 enum pipe pipe, bool state)
1113 {
1114 int reg;
1115 u32 val;
1116 bool cur_state;
1117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 pipe);
1119
1120 if (IS_HASWELL(dev_priv->dev)) {
1121 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1122 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1125 } else {
1126 reg = FDI_TX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_TX_ENABLE);
1129 }
1130 WARN(cur_state != state,
1131 "FDI TX state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133 }
1134 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1135 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1136
assert_fdi_rx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)1137 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1138 enum pipe pipe, bool state)
1139 {
1140 int reg;
1141 u32 val;
1142 bool cur_state;
1143
1144 reg = FDI_RX_CTL(pipe);
1145 val = I915_READ(reg);
1146 cur_state = !!(val & FDI_RX_ENABLE);
1147 WARN(cur_state != state,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 state_string(state), state_string(cur_state));
1150 }
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1153
assert_fdi_tx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 int reg;
1158 u32 val;
1159
1160 /* ILK FDI PLL is always enabled */
1161 if (dev_priv->info->gen == 5)
1162 return;
1163
1164 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1165 if (IS_HASWELL(dev_priv->dev))
1166 return;
1167
1168 reg = FDI_TX_CTL(pipe);
1169 val = I915_READ(reg);
1170 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 }
1172
assert_fdi_rx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)1173 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1174 enum pipe pipe)
1175 {
1176 int reg;
1177 u32 val;
1178
1179 reg = FDI_RX_CTL(pipe);
1180 val = I915_READ(reg);
1181 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1182 }
1183
assert_panel_unlocked(struct drm_i915_private * dev_priv,enum pipe pipe)1184 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 int pp_reg, lvds_reg;
1188 u32 val;
1189 enum pipe panel_pipe = PIPE_A;
1190 bool locked = true;
1191
1192 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1193 pp_reg = PCH_PP_CONTROL;
1194 lvds_reg = PCH_LVDS;
1195 } else {
1196 pp_reg = PP_CONTROL;
1197 lvds_reg = LVDS;
1198 }
1199
1200 val = I915_READ(pp_reg);
1201 if (!(val & PANEL_POWER_ON) ||
1202 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1203 locked = false;
1204
1205 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1206 panel_pipe = PIPE_B;
1207
1208 WARN(panel_pipe == pipe && locked,
1209 "panel assertion failure, pipe %c regs locked\n",
1210 pipe_name(pipe));
1211 }
1212
assert_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)1213 void assert_pipe(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 int reg;
1217 u32 val;
1218 bool cur_state;
1219 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1220 pipe);
1221
1222 /* if we need the pipe A quirk it must be always on */
1223 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1224 state = true;
1225
1226 reg = PIPECONF(cpu_transcoder);
1227 val = I915_READ(reg);
1228 cur_state = !!(val & PIPECONF_ENABLE);
1229 WARN(cur_state != state,
1230 "pipe %c assertion failure (expected %s, current %s)\n",
1231 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 }
1233
assert_plane(struct drm_i915_private * dev_priv,enum plane plane,bool state)1234 static void assert_plane(struct drm_i915_private *dev_priv,
1235 enum plane plane, bool state)
1236 {
1237 int reg;
1238 u32 val;
1239 bool cur_state;
1240
1241 reg = DSPCNTR(plane);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1244 WARN(cur_state != state,
1245 "plane %c assertion failure (expected %s, current %s)\n",
1246 plane_name(plane), state_string(state), state_string(cur_state));
1247 }
1248
1249 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1250 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1251
assert_planes_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1252 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe)
1254 {
1255 int reg, i;
1256 u32 val;
1257 int cur_pipe;
1258
1259 /* Planes are fixed to pipes on ILK+ */
1260 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1261 reg = DSPCNTR(pipe);
1262 val = I915_READ(reg);
1263 WARN((val & DISPLAY_PLANE_ENABLE),
1264 "plane %c assertion failure, should be disabled but not\n",
1265 plane_name(pipe));
1266 return;
1267 }
1268
1269 /* Need to check both planes against the pipe */
1270 for (i = 0; i < 2; i++) {
1271 reg = DSPCNTR(i);
1272 val = I915_READ(reg);
1273 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1274 DISPPLANE_SEL_PIPE_SHIFT;
1275 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1276 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1277 plane_name(i), pipe_name(pipe));
1278 }
1279 }
1280
assert_pch_refclk_enabled(struct drm_i915_private * dev_priv)1281 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1282 {
1283 u32 val;
1284 bool enabled;
1285
1286 if (HAS_PCH_LPT(dev_priv->dev)) {
1287 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1288 return;
1289 }
1290
1291 val = I915_READ(PCH_DREF_CONTROL);
1292 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1293 DREF_SUPERSPREAD_SOURCE_MASK));
1294 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1295 }
1296
assert_transcoder_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1297 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299 {
1300 int reg;
1301 u32 val;
1302 bool enabled;
1303
1304 reg = TRANSCONF(pipe);
1305 val = I915_READ(reg);
1306 enabled = !!(val & TRANS_ENABLE);
1307 WARN(enabled,
1308 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1309 pipe_name(pipe));
1310 }
1311
dp_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 port_sel,u32 val)1312 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, u32 port_sel, u32 val)
1314 {
1315 if ((val & DP_PORT_EN) == 0)
1316 return false;
1317
1318 if (HAS_PCH_CPT(dev_priv->dev)) {
1319 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1320 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1321 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1322 return false;
1323 } else {
1324 if ((val & DP_PIPE_MASK) != (pipe << 30))
1325 return false;
1326 }
1327 return true;
1328 }
1329
hdmi_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1330 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe, u32 val)
1332 {
1333 if ((val & PORT_ENABLE) == 0)
1334 return false;
1335
1336 if (HAS_PCH_CPT(dev_priv->dev)) {
1337 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1338 return false;
1339 } else {
1340 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1341 return false;
1342 }
1343 return true;
1344 }
1345
lvds_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348 {
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
1352 if (HAS_PCH_CPT(dev_priv->dev)) {
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360 }
1361
adpa_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364 {
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
1367 if (HAS_PCH_CPT(dev_priv->dev)) {
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375 }
1376
assert_pch_dp_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg,u32 port_sel)1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378 enum pipe pipe, int reg, u32 port_sel)
1379 {
1380 u32 val = I915_READ(reg);
1381 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1382 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1383 reg, pipe_name(pipe));
1384
1385 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1386 && (val & DP_PIPEB_SELECT),
1387 "IBX PCH dp port still using transcoder B\n");
1388 }
1389
assert_pch_hdmi_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg)1390 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe, int reg)
1392 {
1393 u32 val = I915_READ(reg);
1394 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1395 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1396 reg, pipe_name(pipe));
1397
1398 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1399 && (val & SDVO_PIPE_B_SELECT),
1400 "IBX PCH hdmi port still using transcoder B\n");
1401 }
1402
assert_pch_ports_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1403 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe)
1405 {
1406 int reg;
1407 u32 val;
1408
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413 reg = PCH_ADPA;
1414 val = I915_READ(reg);
1415 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1416 "PCH VGA enabled on transcoder %c, should be disabled\n",
1417 pipe_name(pipe));
1418
1419 reg = PCH_LVDS;
1420 val = I915_READ(reg);
1421 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1422 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1423 pipe_name(pipe));
1424
1425 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1426 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1427 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1428 }
1429
1430 /**
1431 * intel_enable_pll - enable a PLL
1432 * @dev_priv: i915 private structure
1433 * @pipe: pipe PLL to enable
1434 *
1435 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1436 * make sure the PLL reg is writable first though, since the panel write
1437 * protect mechanism may be enabled.
1438 *
1439 * Note! This is for pre-ILK only.
1440 *
1441 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1442 */
intel_enable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)1443 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1444 {
1445 int reg;
1446 u32 val;
1447
1448 /* No really, not for ILK+ */
1449 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1450
1451 /* PLL is protected by panel, make sure we can write it */
1452 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1453 assert_panel_unlocked(dev_priv, pipe);
1454
1455 reg = DPLL(pipe);
1456 val = I915_READ(reg);
1457 val |= DPLL_VCO_ENABLE;
1458
1459 /* We do this three times for luck */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466 I915_WRITE(reg, val);
1467 POSTING_READ(reg);
1468 udelay(150); /* wait for warmup */
1469 }
1470
1471 /**
1472 * intel_disable_pll - disable a PLL
1473 * @dev_priv: i915 private structure
1474 * @pipe: pipe PLL to disable
1475 *
1476 * Disable the PLL for @pipe, making sure the pipe is off first.
1477 *
1478 * Note! This is for pre-ILK only.
1479 */
intel_disable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)1480 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1481 {
1482 int reg;
1483 u32 val;
1484
1485 /* Don't disable pipe A or pipe A PLLs if needed */
1486 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1487 return;
1488
1489 /* Make sure the pipe isn't still relying on us */
1490 assert_pipe_disabled(dev_priv, pipe);
1491
1492 reg = DPLL(pipe);
1493 val = I915_READ(reg);
1494 val &= ~DPLL_VCO_ENABLE;
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 }
1498
1499 /* SBI access */
1500 static void
intel_sbi_write(struct drm_i915_private * dev_priv,u16 reg,u32 value,enum intel_sbi_destination destination)1501 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1502 enum intel_sbi_destination destination)
1503 {
1504 u32 tmp;
1505
1506 sx_xlock(&dev_priv->dpio_lock);
1507 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1508 DRM_ERROR("timeout waiting for SBI to become ready\n");
1509 goto out_unlock;
1510 }
1511
1512 I915_WRITE(SBI_ADDR, (reg << 16));
1513 I915_WRITE(SBI_DATA, value);
1514
1515 if (destination == SBI_ICLK)
1516 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1517 else
1518 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1519 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1520
1521 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1522 100)) {
1523 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1524 goto out_unlock;
1525 }
1526
1527 out_unlock:
1528 sx_xunlock(&dev_priv->dpio_lock);
1529 }
1530
1531 static u32
intel_sbi_read(struct drm_i915_private * dev_priv,u16 reg,enum intel_sbi_destination destination)1532 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1533 enum intel_sbi_destination destination)
1534 {
1535 u32 value = 0;
1536
1537 sx_xlock(&dev_priv->dpio_lock);
1538 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
1540 goto out_unlock;
1541 }
1542
1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544
1545 if (destination == SBI_ICLK)
1546 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1547 else
1548 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1549 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1550
1551 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1552 100)) {
1553 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1554 goto out_unlock;
1555 }
1556
1557 value = I915_READ(SBI_DATA);
1558
1559 out_unlock:
1560 sx_xunlock(&dev_priv->dpio_lock);
1561 return value;
1562 }
1563
1564 /**
1565 * ironlake_enable_pch_pll - enable PCH PLL
1566 * @dev_priv: i915 private structure
1567 * @pipe: pipe PLL to enable
1568 *
1569 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1570 * drives the transcoder clock.
1571 */
ironlake_enable_pch_pll(struct intel_crtc * intel_crtc)1572 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1573 {
1574 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1575 struct intel_pch_pll *pll;
1576 int reg;
1577 u32 val;
1578
1579 /* PCH PLLs only available on ILK, SNB and IVB */
1580 BUG_ON(dev_priv->info->gen < 5);
1581 pll = intel_crtc->pch_pll;
1582 if (pll == NULL)
1583 return;
1584
1585 if (WARN_ON(pll->refcount == 0))
1586 return;
1587
1588 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1589 pll->pll_reg, pll->active, pll->on,
1590 intel_crtc->base.base.id);
1591
1592 /* PCH refclock must be enabled first */
1593 assert_pch_refclk_enabled(dev_priv);
1594
1595 if (pll->active++ && pll->on) {
1596 assert_pch_pll_enabled(dev_priv, pll, NULL);
1597 return;
1598 }
1599
1600 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1601
1602 reg = pll->pll_reg;
1603 val = I915_READ(reg);
1604 val |= DPLL_VCO_ENABLE;
1605 I915_WRITE(reg, val);
1606 POSTING_READ(reg);
1607 udelay(200);
1608
1609 pll->on = true;
1610 }
1611
intel_disable_pch_pll(struct intel_crtc * intel_crtc)1612 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1613 {
1614 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1615 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1616 int reg;
1617 u32 val;
1618
1619 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv->info->gen < 5);
1621 if (pll == NULL)
1622 return;
1623
1624 if (WARN_ON(pll->refcount == 0))
1625 return;
1626
1627 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1628 pll->pll_reg, pll->active, pll->on,
1629 intel_crtc->base.base.id);
1630
1631 if (WARN_ON(pll->active == 0)) {
1632 assert_pch_pll_disabled(dev_priv, pll, NULL);
1633 return;
1634 }
1635
1636 if (--pll->active) {
1637 assert_pch_pll_enabled(dev_priv, pll, NULL);
1638 return;
1639 }
1640
1641 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1642
1643 /* Make sure transcoder isn't still depending on us */
1644 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1645
1646 reg = pll->pll_reg;
1647 val = I915_READ(reg);
1648 val &= ~DPLL_VCO_ENABLE;
1649 I915_WRITE(reg, val);
1650 POSTING_READ(reg);
1651 udelay(200);
1652
1653 pll->on = false;
1654 }
1655
ironlake_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)1656 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1657 enum pipe pipe)
1658 {
1659 struct drm_device *dev = dev_priv->dev;
1660 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1661 uint32_t reg, val, pipeconf_val;
1662
1663 /* PCH only available on ILK+ */
1664 BUG_ON(dev_priv->info->gen < 5);
1665
1666 /* Make sure PCH DPLL is enabled */
1667 assert_pch_pll_enabled(dev_priv,
1668 to_intel_crtc(crtc)->pch_pll,
1669 to_intel_crtc(crtc));
1670
1671 /* FDI must be feeding us bits for PCH ports */
1672 assert_fdi_tx_enabled(dev_priv, pipe);
1673 assert_fdi_rx_enabled(dev_priv, pipe);
1674
1675 if (HAS_PCH_CPT(dev)) {
1676 /* Workaround: Set the timing override bit before enabling the
1677 * pch transcoder. */
1678 reg = TRANS_CHICKEN2(pipe);
1679 val = I915_READ(reg);
1680 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1681 I915_WRITE(reg, val);
1682 }
1683
1684 reg = TRANSCONF(pipe);
1685 val = I915_READ(reg);
1686 pipeconf_val = I915_READ(PIPECONF(pipe));
1687
1688 if (HAS_PCH_IBX(dev_priv->dev)) {
1689 /*
1690 * make the BPC in transcoder be consistent with
1691 * that in pipeconf reg.
1692 */
1693 val &= ~PIPE_BPC_MASK;
1694 val |= pipeconf_val & PIPE_BPC_MASK;
1695 }
1696
1697 val &= ~TRANS_INTERLACE_MASK;
1698 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1699 if (HAS_PCH_IBX(dev_priv->dev) &&
1700 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1701 val |= TRANS_LEGACY_INTERLACED_ILK;
1702 else
1703 val |= TRANS_INTERLACED;
1704 else
1705 val |= TRANS_PROGRESSIVE;
1706
1707 I915_WRITE(reg, val | TRANS_ENABLE);
1708 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1709 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1710 }
1711
lpt_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)1712 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1713 enum transcoder cpu_transcoder)
1714 {
1715 u32 val, pipeconf_val;
1716
1717 /* PCH only available on ILK+ */
1718 BUG_ON(dev_priv->info->gen < 5);
1719
1720 /* FDI must be feeding us bits for PCH ports */
1721 assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder);
1722 assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A);
1723
1724 /* Workaround: set timing override bit. */
1725 val = I915_READ(_TRANSA_CHICKEN2);
1726 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1727 I915_WRITE(_TRANSA_CHICKEN2, val);
1728
1729 val = TRANS_ENABLE;
1730 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1731
1732 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1733 PIPECONF_INTERLACED_ILK)
1734 val |= TRANS_INTERLACED;
1735 else
1736 val |= TRANS_PROGRESSIVE;
1737
1738 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1739 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1740 DRM_ERROR("Failed to enable PCH transcoder\n");
1741 }
1742
ironlake_disable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)1743 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1744 enum pipe pipe)
1745 {
1746 struct drm_device *dev = dev_priv->dev;
1747 uint32_t reg, val;
1748
1749 /* FDI relies on the transcoder */
1750 assert_fdi_tx_disabled(dev_priv, pipe);
1751 assert_fdi_rx_disabled(dev_priv, pipe);
1752
1753 /* Ports must be off as well */
1754 assert_pch_ports_disabled(dev_priv, pipe);
1755
1756 reg = TRANSCONF(pipe);
1757 val = I915_READ(reg);
1758 val &= ~TRANS_ENABLE;
1759 I915_WRITE(reg, val);
1760 /* wait for PCH transcoder off, transcoder state */
1761 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1762 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1763
1764 if (!HAS_PCH_IBX(dev)) {
1765 /* Workaround: Clear the timing override chicken bit again. */
1766 reg = TRANS_CHICKEN2(pipe);
1767 val = I915_READ(reg);
1768 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1769 I915_WRITE(reg, val);
1770 }
1771 }
1772
lpt_disable_pch_transcoder(struct drm_i915_private * dev_priv)1773 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1774 {
1775 u32 val;
1776
1777 val = I915_READ(_TRANSACONF);
1778 val &= ~TRANS_ENABLE;
1779 I915_WRITE(_TRANSACONF, val);
1780 /* wait for PCH transcoder off, transcoder state */
1781 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1782 DRM_ERROR("Failed to disable PCH transcoder\n");
1783
1784 /* Workaround: clear timing override bit. */
1785 val = I915_READ(_TRANSA_CHICKEN2);
1786 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1787 I915_WRITE(_TRANSA_CHICKEN2, val);
1788 }
1789
1790 /**
1791 * intel_enable_pipe - enable a pipe, asserting requirements
1792 * @dev_priv: i915 private structure
1793 * @pipe: pipe to enable
1794 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1795 *
1796 * Enable @pipe, making sure that various hardware specific requirements
1797 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1798 *
1799 * @pipe should be %PIPE_A or %PIPE_B.
1800 *
1801 * Will wait until the pipe is actually running (i.e. first vblank) before
1802 * returning.
1803 */
intel_enable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool pch_port)1804 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1805 bool pch_port)
1806 {
1807 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1808 pipe);
1809 enum transcoder pch_transcoder;
1810 int reg;
1811 u32 val;
1812
1813 if (IS_HASWELL(dev_priv->dev))
1814 pch_transcoder = TRANSCODER_A;
1815 else
1816 pch_transcoder = (enum transcoder)pipe;
1817
1818 /*
1819 * A pipe without a PLL won't actually be able to drive bits from
1820 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1821 * need the check.
1822 */
1823 if (!HAS_PCH_SPLIT(dev_priv->dev))
1824 assert_pll_enabled(dev_priv, pipe);
1825 else {
1826 if (pch_port) {
1827 /* if driving the PCH, we need FDI enabled */
1828 assert_fdi_rx_pll_enabled(dev_priv, (enum pipe)pch_transcoder);
1829 assert_fdi_tx_pll_enabled(dev_priv, (enum pipe)cpu_transcoder);
1830 }
1831 /* FIXME: assert CPU port conditions for SNB+ */
1832 }
1833
1834 reg = PIPECONF(cpu_transcoder);
1835 val = I915_READ(reg);
1836 if (val & PIPECONF_ENABLE)
1837 return;
1838
1839 I915_WRITE(reg, val | PIPECONF_ENABLE);
1840 intel_wait_for_vblank(dev_priv->dev, pipe);
1841 }
1842
1843 /**
1844 * intel_disable_pipe - disable a pipe, asserting requirements
1845 * @dev_priv: i915 private structure
1846 * @pipe: pipe to disable
1847 *
1848 * Disable @pipe, making sure that various hardware specific requirements
1849 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1850 *
1851 * @pipe should be %PIPE_A or %PIPE_B.
1852 *
1853 * Will wait until the pipe has shut down before returning.
1854 */
intel_disable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1855 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1856 enum pipe pipe)
1857 {
1858 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1859 pipe);
1860 int reg;
1861 u32 val;
1862
1863 /*
1864 * Make sure planes won't keep trying to pump pixels to us,
1865 * or we might hang the display.
1866 */
1867 assert_planes_disabled(dev_priv, pipe);
1868
1869 /* Don't disable pipe A or pipe A PLLs if needed */
1870 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1871 return;
1872
1873 reg = PIPECONF(cpu_transcoder);
1874 val = I915_READ(reg);
1875 if ((val & PIPECONF_ENABLE) == 0)
1876 return;
1877
1878 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1879 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1880 }
1881
1882 /*
1883 * Plane regs are double buffered, going from enabled->disabled needs a
1884 * trigger in order to latch. The display address reg provides this.
1885 */
intel_flush_display_plane(struct drm_i915_private * dev_priv,enum plane plane)1886 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1887 enum plane plane)
1888 {
1889 if (dev_priv->info->gen >= 4)
1890 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1891 else
1892 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1893 }
1894
1895 /**
1896 * intel_enable_plane - enable a display plane on a given pipe
1897 * @dev_priv: i915 private structure
1898 * @plane: plane to enable
1899 * @pipe: pipe being fed
1900 *
1901 * Enable @plane on @pipe, making sure that @pipe is running first.
1902 */
intel_enable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)1903 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1904 enum plane plane, enum pipe pipe)
1905 {
1906 int reg;
1907 u32 val;
1908
1909 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1910 assert_pipe_enabled(dev_priv, pipe);
1911
1912 reg = DSPCNTR(plane);
1913 val = I915_READ(reg);
1914 if (val & DISPLAY_PLANE_ENABLE)
1915 return;
1916
1917 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1918 intel_flush_display_plane(dev_priv, plane);
1919 intel_wait_for_vblank(dev_priv->dev, pipe);
1920 }
1921
1922 /**
1923 * intel_disable_plane - disable a display plane
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to disable
1926 * @pipe: pipe consuming the data
1927 *
1928 * Disable @plane; should be an independent operation.
1929 */
intel_disable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)1930 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932 {
1933 int reg;
1934 u32 val;
1935
1936 reg = DSPCNTR(plane);
1937 val = I915_READ(reg);
1938 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1939 return;
1940
1941 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1942 intel_flush_display_plane(dev_priv, plane);
1943 intel_wait_for_vblank(dev_priv->dev, pipe);
1944 }
1945
1946 int
intel_pin_and_fence_fb_obj(struct drm_device * dev,struct drm_i915_gem_object * obj,struct intel_ring_buffer * pipelined)1947 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1948 struct drm_i915_gem_object *obj,
1949 struct intel_ring_buffer *pipelined)
1950 {
1951 struct drm_i915_private *dev_priv = dev->dev_private;
1952 u32 alignment;
1953 int ret;
1954
1955 switch (obj->tiling_mode) {
1956 case I915_TILING_NONE:
1957 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1958 alignment = 128 * 1024;
1959 else if (INTEL_INFO(dev)->gen >= 4)
1960 alignment = 4 * 1024;
1961 else
1962 alignment = 64 * 1024;
1963 break;
1964 case I915_TILING_X:
1965 /* pin() will align the object as required by fence */
1966 alignment = 0;
1967 break;
1968 case I915_TILING_Y:
1969 /* FIXME: Is this true? */
1970 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1971 return -EINVAL;
1972 default:
1973 BUG();
1974 }
1975
1976 dev_priv->mm.interruptible = false;
1977 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1978 if (ret)
1979 goto err_interruptible;
1980
1981 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1982 * fence, whereas 965+ only requires a fence if using
1983 * framebuffer compression. For simplicity, we always install
1984 * a fence as the cost is not that onerous.
1985 */
1986 ret = i915_gem_object_get_fence(obj);
1987 if (ret)
1988 goto err_unpin;
1989
1990 i915_gem_object_pin_fence(obj);
1991
1992 dev_priv->mm.interruptible = true;
1993 return 0;
1994
1995 err_unpin:
1996 i915_gem_object_unpin(obj);
1997 err_interruptible:
1998 dev_priv->mm.interruptible = true;
1999 return ret;
2000 }
2001
intel_unpin_fb_obj(struct drm_i915_gem_object * obj)2002 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2003 {
2004 i915_gem_object_unpin_fence(obj);
2005 i915_gem_object_unpin(obj);
2006 }
2007
2008 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2009 * is assumed to be a power-of-two. */
intel_gen4_compute_page_offset(int * x,int * y,unsigned int tiling_mode,unsigned int cpp,unsigned int pitch)2010 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2011 unsigned int tiling_mode,
2012 unsigned int cpp,
2013 unsigned int pitch)
2014 {
2015 if (tiling_mode != I915_TILING_NONE) {
2016 unsigned int tile_rows, tiles;
2017
2018 tile_rows = *y / 8;
2019 *y %= 8;
2020
2021 tiles = *x / (512/cpp);
2022 *x %= 512/cpp;
2023
2024 return tile_rows * pitch * 8 + tiles * 4096;
2025 } else {
2026 unsigned int offset;
2027
2028 offset = *y * pitch + *x * cpp;
2029 *y = 0;
2030 *x = (offset & 4095) / cpp;
2031 return offset & -4096;
2032 }
2033 }
2034
i9xx_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)2035 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2036 int x, int y)
2037 {
2038 struct drm_device *dev = crtc->dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2041 struct intel_framebuffer *intel_fb;
2042 struct drm_i915_gem_object *obj;
2043 int plane = intel_crtc->plane;
2044 unsigned long linear_offset;
2045 u32 dspcntr;
2046 u32 reg;
2047
2048 switch (plane) {
2049 case 0:
2050 case 1:
2051 break;
2052 default:
2053 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2054 return -EINVAL;
2055 }
2056
2057 intel_fb = to_intel_framebuffer(fb);
2058 obj = intel_fb->obj;
2059
2060 reg = DSPCNTR(plane);
2061 dspcntr = I915_READ(reg);
2062 /* Mask out pixel format bits in case we change it */
2063 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2064 switch (fb->pixel_format) {
2065 case DRM_FORMAT_C8:
2066 dspcntr |= DISPPLANE_8BPP;
2067 break;
2068 case DRM_FORMAT_XRGB1555:
2069 case DRM_FORMAT_ARGB1555:
2070 dspcntr |= DISPPLANE_BGRX555;
2071 break;
2072 case DRM_FORMAT_RGB565:
2073 dspcntr |= DISPPLANE_BGRX565;
2074 break;
2075 case DRM_FORMAT_XRGB8888:
2076 case DRM_FORMAT_ARGB8888:
2077 dspcntr |= DISPPLANE_BGRX888;
2078 break;
2079 case DRM_FORMAT_XBGR8888:
2080 case DRM_FORMAT_ABGR8888:
2081 dspcntr |= DISPPLANE_RGBX888;
2082 break;
2083 case DRM_FORMAT_XRGB2101010:
2084 case DRM_FORMAT_ARGB2101010:
2085 dspcntr |= DISPPLANE_BGRX101010;
2086 break;
2087 case DRM_FORMAT_XBGR2101010:
2088 case DRM_FORMAT_ABGR2101010:
2089 dspcntr |= DISPPLANE_RGBX101010;
2090 break;
2091 default:
2092 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2093 return -EINVAL;
2094 }
2095
2096 if (INTEL_INFO(dev)->gen >= 4) {
2097 if (obj->tiling_mode != I915_TILING_NONE)
2098 dspcntr |= DISPPLANE_TILED;
2099 else
2100 dspcntr &= ~DISPPLANE_TILED;
2101 }
2102
2103 I915_WRITE(reg, dspcntr);
2104
2105 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2106
2107 if (INTEL_INFO(dev)->gen >= 4) {
2108 intel_crtc->dspaddr_offset =
2109 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2110 fb->bits_per_pixel / 8,
2111 fb->pitches[0]);
2112 linear_offset -= intel_crtc->dspaddr_offset;
2113 } else {
2114 intel_crtc->dspaddr_offset = linear_offset;
2115 }
2116
2117 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2118 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2119 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2120 if (INTEL_INFO(dev)->gen >= 4) {
2121 I915_MODIFY_DISPBASE(DSPSURF(plane),
2122 obj->gtt_offset + intel_crtc->dspaddr_offset);
2123 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2124 I915_WRITE(DSPLINOFF(plane), linear_offset);
2125 } else
2126 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2127 POSTING_READ(reg);
2128
2129 return 0;
2130 }
2131
ironlake_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)2132 static int ironlake_update_plane(struct drm_crtc *crtc,
2133 struct drm_framebuffer *fb, int x, int y)
2134 {
2135 struct drm_device *dev = crtc->dev;
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2138 struct intel_framebuffer *intel_fb;
2139 struct drm_i915_gem_object *obj;
2140 int plane = intel_crtc->plane;
2141 unsigned long linear_offset;
2142 u32 dspcntr;
2143 u32 reg;
2144
2145 switch (plane) {
2146 case 0:
2147 case 1:
2148 case 2:
2149 break;
2150 default:
2151 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2152 return -EINVAL;
2153 }
2154
2155 intel_fb = to_intel_framebuffer(fb);
2156 obj = intel_fb->obj;
2157
2158 reg = DSPCNTR(plane);
2159 dspcntr = I915_READ(reg);
2160 /* Mask out pixel format bits in case we change it */
2161 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2162 switch (fb->pixel_format) {
2163 case DRM_FORMAT_C8:
2164 dspcntr |= DISPPLANE_8BPP;
2165 break;
2166 case DRM_FORMAT_RGB565:
2167 dspcntr |= DISPPLANE_BGRX565;
2168 break;
2169 case DRM_FORMAT_XRGB8888:
2170 case DRM_FORMAT_ARGB8888:
2171 dspcntr |= DISPPLANE_BGRX888;
2172 break;
2173 case DRM_FORMAT_XBGR8888:
2174 case DRM_FORMAT_ABGR8888:
2175 dspcntr |= DISPPLANE_RGBX888;
2176 break;
2177 case DRM_FORMAT_XRGB2101010:
2178 case DRM_FORMAT_ARGB2101010:
2179 dspcntr |= DISPPLANE_BGRX101010;
2180 break;
2181 case DRM_FORMAT_XBGR2101010:
2182 case DRM_FORMAT_ABGR2101010:
2183 dspcntr |= DISPPLANE_RGBX101010;
2184 break;
2185 default:
2186 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2187 return -EINVAL;
2188 }
2189
2190 if (obj->tiling_mode != I915_TILING_NONE)
2191 dspcntr |= DISPPLANE_TILED;
2192 else
2193 dspcntr &= ~DISPPLANE_TILED;
2194
2195 /* must disable */
2196 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2197
2198 I915_WRITE(reg, dspcntr);
2199
2200 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2201 intel_crtc->dspaddr_offset =
2202 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2203 fb->bits_per_pixel / 8,
2204 fb->pitches[0]);
2205 linear_offset -= intel_crtc->dspaddr_offset;
2206
2207 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2208 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2209 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2210 I915_MODIFY_DISPBASE(DSPSURF(plane),
2211 obj->gtt_offset + intel_crtc->dspaddr_offset);
2212 if (IS_HASWELL(dev)) {
2213 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2214 } else {
2215 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2216 I915_WRITE(DSPLINOFF(plane), linear_offset);
2217 }
2218 POSTING_READ(reg);
2219
2220 return 0;
2221 }
2222
2223 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2224 static int
intel_pipe_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)2225 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2226 int x, int y, enum mode_set_atomic state)
2227 {
2228 struct drm_device *dev = crtc->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230
2231 if (dev_priv->display.disable_fbc)
2232 dev_priv->display.disable_fbc(dev);
2233 intel_increase_pllclock(crtc);
2234
2235 return dev_priv->display.update_plane(crtc, fb, x, y);
2236 }
2237
2238 static int
intel_finish_fb(struct drm_framebuffer * old_fb)2239 intel_finish_fb(struct drm_framebuffer *old_fb)
2240 {
2241 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2242 struct drm_device *dev = obj->base.dev;
2243 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2244 bool was_interruptible = dev_priv->mm.interruptible;
2245 int ret;
2246
2247 mtx_lock(&dev->event_lock);
2248 while (!(atomic_read(&dev_priv->mm.wedged) ||
2249 atomic_read(&obj->pending_flip) == 0)) {
2250 msleep(&dev_priv->pending_flip_queue, &dev->event_lock,
2251 0, "915flp", 0);
2252 }
2253 mtx_unlock(&dev->event_lock);
2254
2255 /* Big Hammer, we also need to ensure that any pending
2256 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2257 * current scanout is retired before unpinning the old
2258 * framebuffer.
2259 *
2260 * This should only fail upon a hung GPU, in which case we
2261 * can safely continue.
2262 */
2263 dev_priv->mm.interruptible = false;
2264 ret = i915_gem_object_finish_gpu(obj);
2265 dev_priv->mm.interruptible = was_interruptible;
2266
2267 return ret;
2268 }
2269
intel_crtc_update_sarea_pos(struct drm_crtc * crtc,int x,int y)2270 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2271 {
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_master_private *master_priv;
2274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2275
2276 if (!dev->primary->master)
2277 return;
2278
2279 master_priv = dev->primary->master->driver_priv;
2280 if (!master_priv->sarea_priv)
2281 return;
2282
2283 switch (intel_crtc->pipe) {
2284 case 0:
2285 master_priv->sarea_priv->pipeA_x = x;
2286 master_priv->sarea_priv->pipeA_y = y;
2287 break;
2288 case 1:
2289 master_priv->sarea_priv->pipeB_x = x;
2290 master_priv->sarea_priv->pipeB_y = y;
2291 break;
2292 default:
2293 break;
2294 }
2295 }
2296
2297 static int
intel_pipe_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)2298 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2299 struct drm_framebuffer *fb)
2300 {
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 struct drm_framebuffer *old_fb;
2305 int ret;
2306
2307 /* no fb bound */
2308 if (!fb) {
2309 DRM_ERROR("No FB bound\n");
2310 return 0;
2311 }
2312
2313 if(intel_crtc->plane > dev_priv->num_pipe) {
2314 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2315 intel_crtc->plane,
2316 dev_priv->num_pipe);
2317 return -EINVAL;
2318 }
2319
2320 DRM_LOCK(dev);
2321 ret = intel_pin_and_fence_fb_obj(dev,
2322 to_intel_framebuffer(fb)->obj,
2323 NULL);
2324 if (ret != 0) {
2325 DRM_UNLOCK(dev);
2326 DRM_ERROR("pin & fence failed\n");
2327 return ret;
2328 }
2329
2330 if (crtc->fb)
2331 intel_finish_fb(crtc->fb);
2332
2333 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2334 if (ret) {
2335 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2336 DRM_UNLOCK(dev);
2337 DRM_ERROR("failed to update base address\n");
2338 return ret;
2339 }
2340
2341 old_fb = crtc->fb;
2342 crtc->fb = fb;
2343 crtc->x = x;
2344 crtc->y = y;
2345
2346 if (old_fb) {
2347 intel_wait_for_vblank(dev, intel_crtc->pipe);
2348 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2349 }
2350
2351 intel_update_fbc(dev);
2352 DRM_UNLOCK(dev);
2353
2354 intel_crtc_update_sarea_pos(crtc, x, y);
2355
2356 return 0;
2357 }
2358
ironlake_set_pll_edp(struct drm_crtc * crtc,int clock)2359 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2360 {
2361 struct drm_device *dev = crtc->dev;
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 u32 dpa_ctl;
2364
2365 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2366 dpa_ctl = I915_READ(DP_A);
2367 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2368
2369 if (clock < 200000) {
2370 u32 temp;
2371 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2372 /* workaround for 160Mhz:
2373 1) program 0x4600c bits 15:0 = 0x8124
2374 2) program 0x46010 bit 0 = 1
2375 3) program 0x46034 bit 24 = 1
2376 4) program 0x64000 bit 14 = 1
2377 */
2378 temp = I915_READ(0x4600c);
2379 temp &= 0xffff0000;
2380 I915_WRITE(0x4600c, temp | 0x8124);
2381
2382 temp = I915_READ(0x46010);
2383 I915_WRITE(0x46010, temp | 1);
2384
2385 temp = I915_READ(0x46034);
2386 I915_WRITE(0x46034, temp | (1 << 24));
2387 } else {
2388 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2389 }
2390 I915_WRITE(DP_A, dpa_ctl);
2391
2392 POSTING_READ(DP_A);
2393 udelay(500);
2394 }
2395
intel_fdi_normal_train(struct drm_crtc * crtc)2396 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2397 {
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
2402 u32 reg, temp;
2403
2404 /* enable normal train */
2405 reg = FDI_TX_CTL(pipe);
2406 temp = I915_READ(reg);
2407 if (IS_IVYBRIDGE(dev)) {
2408 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2409 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2410 } else {
2411 temp &= ~FDI_LINK_TRAIN_NONE;
2412 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2413 }
2414 I915_WRITE(reg, temp);
2415
2416 reg = FDI_RX_CTL(pipe);
2417 temp = I915_READ(reg);
2418 if (HAS_PCH_CPT(dev)) {
2419 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2420 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2421 } else {
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_NONE;
2424 }
2425 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2426
2427 /* wait one idle pattern time */
2428 POSTING_READ(reg);
2429 udelay(1000);
2430
2431 /* IVB wants error correction enabled */
2432 if (IS_IVYBRIDGE(dev))
2433 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2434 FDI_FE_ERRC_ENABLE);
2435 }
2436
ivb_modeset_global_resources(struct drm_device * dev)2437 static void ivb_modeset_global_resources(struct drm_device *dev)
2438 {
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 struct intel_crtc *pipe_B_crtc =
2441 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2442 struct intel_crtc *pipe_C_crtc =
2443 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2444 uint32_t temp;
2445
2446 /* When everything is off disable fdi C so that we could enable fdi B
2447 * with all lanes. XXX: This misses the case where a pipe is not using
2448 * any pch resources and so doesn't need any fdi lanes. */
2449 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2450 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2451 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2452
2453 temp = I915_READ(SOUTH_CHICKEN1);
2454 temp &= ~FDI_BC_BIFURCATION_SELECT;
2455 DRM_DEBUG_KMS("disabling fdi C rx\n");
2456 I915_WRITE(SOUTH_CHICKEN1, temp);
2457 }
2458 }
2459
2460 /* The FDI link training functions for ILK/Ibexpeak. */
ironlake_fdi_link_train(struct drm_crtc * crtc)2461 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2462 {
2463 struct drm_device *dev = crtc->dev;
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2466 int pipe = intel_crtc->pipe;
2467 int plane = intel_crtc->plane;
2468 u32 reg, temp, tries;
2469
2470 /* FDI needs bits from pipe & plane first */
2471 assert_pipe_enabled(dev_priv, pipe);
2472 assert_plane_enabled(dev_priv, plane);
2473
2474 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2475 for train result */
2476 reg = FDI_RX_IMR(pipe);
2477 temp = I915_READ(reg);
2478 temp &= ~FDI_RX_SYMBOL_LOCK;
2479 temp &= ~FDI_RX_BIT_LOCK;
2480 I915_WRITE(reg, temp);
2481 I915_READ(reg);
2482 udelay(150);
2483
2484 /* enable CPU FDI TX and PCH FDI RX */
2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~(7 << 19);
2488 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2492
2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1;
2497 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2498
2499 POSTING_READ(reg);
2500 udelay(150);
2501
2502 /* Ironlake workaround, enable clock pointer after FDI enable*/
2503 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2504 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2505 FDI_RX_PHASE_SYNC_POINTER_EN);
2506
2507 reg = FDI_RX_IIR(pipe);
2508 for (tries = 0; tries < 5; tries++) {
2509 temp = I915_READ(reg);
2510 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2511
2512 if ((temp & FDI_RX_BIT_LOCK)) {
2513 DRM_DEBUG_KMS("FDI train 1 done.\n");
2514 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2515 break;
2516 }
2517 }
2518 if (tries == 5)
2519 DRM_ERROR("FDI train 1 fail!\n");
2520
2521 /* Train 2 */
2522 reg = FDI_TX_CTL(pipe);
2523 temp = I915_READ(reg);
2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_2;
2526 I915_WRITE(reg, temp);
2527
2528 reg = FDI_RX_CTL(pipe);
2529 temp = I915_READ(reg);
2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2;
2532 I915_WRITE(reg, temp);
2533
2534 POSTING_READ(reg);
2535 udelay(150);
2536
2537 reg = FDI_RX_IIR(pipe);
2538 for (tries = 0; tries < 5; tries++) {
2539 temp = I915_READ(reg);
2540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541
2542 if (temp & FDI_RX_SYMBOL_LOCK) {
2543 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2544 DRM_DEBUG_KMS("FDI train 2 done.\n");
2545 break;
2546 }
2547 }
2548 if (tries == 5)
2549 DRM_ERROR("FDI train 2 fail!\n");
2550
2551 DRM_DEBUG_KMS("FDI train done\n");
2552
2553 }
2554
2555 static const int snb_b_fdi_train_param[] = {
2556 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2557 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2558 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2559 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2560 };
2561
2562 /* The FDI link training functions for SNB/Cougarpoint. */
gen6_fdi_link_train(struct drm_crtc * crtc)2563 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2564 {
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 int pipe = intel_crtc->pipe;
2569 u32 reg, temp, i, retry;
2570
2571 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2572 for train result */
2573 reg = FDI_RX_IMR(pipe);
2574 temp = I915_READ(reg);
2575 temp &= ~FDI_RX_SYMBOL_LOCK;
2576 temp &= ~FDI_RX_BIT_LOCK;
2577 I915_WRITE(reg, temp);
2578
2579 POSTING_READ(reg);
2580 udelay(150);
2581
2582 /* enable CPU FDI TX and PCH FDI RX */
2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
2585 temp &= ~(7 << 19);
2586 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2587 temp &= ~FDI_LINK_TRAIN_NONE;
2588 temp |= FDI_LINK_TRAIN_PATTERN_1;
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 /* SNB-B */
2591 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2592 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2593
2594 I915_WRITE(FDI_RX_MISC(pipe),
2595 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2596
2597 reg = FDI_RX_CTL(pipe);
2598 temp = I915_READ(reg);
2599 if (HAS_PCH_CPT(dev)) {
2600 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2602 } else {
2603 temp &= ~FDI_LINK_TRAIN_NONE;
2604 temp |= FDI_LINK_TRAIN_PATTERN_1;
2605 }
2606 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2607
2608 POSTING_READ(reg);
2609 udelay(150);
2610
2611 for (i = 0; i < 4; i++) {
2612 reg = FDI_TX_CTL(pipe);
2613 temp = I915_READ(reg);
2614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615 temp |= snb_b_fdi_train_param[i];
2616 I915_WRITE(reg, temp);
2617
2618 POSTING_READ(reg);
2619 udelay(500);
2620
2621 for (retry = 0; retry < 5; retry++) {
2622 reg = FDI_RX_IIR(pipe);
2623 temp = I915_READ(reg);
2624 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2625 if (temp & FDI_RX_BIT_LOCK) {
2626 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627 DRM_DEBUG_KMS("FDI train 1 done.\n");
2628 break;
2629 }
2630 udelay(50);
2631 }
2632 if (retry < 5)
2633 break;
2634 }
2635 if (i == 4)
2636 DRM_ERROR("FDI train 1 fail!\n");
2637
2638 /* Train 2 */
2639 reg = FDI_TX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_NONE;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2;
2643 if (IS_GEN6(dev)) {
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2645 /* SNB-B */
2646 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2647 }
2648 I915_WRITE(reg, temp);
2649
2650 reg = FDI_RX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 if (HAS_PCH_CPT(dev)) {
2653 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2655 } else {
2656 temp &= ~FDI_LINK_TRAIN_NONE;
2657 temp |= FDI_LINK_TRAIN_PATTERN_2;
2658 }
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 for (i = 0; i < 4; i++) {
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= snb_b_fdi_train_param[i];
2669 I915_WRITE(reg, temp);
2670
2671 POSTING_READ(reg);
2672 udelay(500);
2673
2674 for (retry = 0; retry < 5; retry++) {
2675 reg = FDI_RX_IIR(pipe);
2676 temp = I915_READ(reg);
2677 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2678 if (temp & FDI_RX_SYMBOL_LOCK) {
2679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2680 DRM_DEBUG_KMS("FDI train 2 done.\n");
2681 break;
2682 }
2683 udelay(50);
2684 }
2685 if (retry < 5)
2686 break;
2687 }
2688 if (i == 4)
2689 DRM_ERROR("FDI train 2 fail!\n");
2690
2691 DRM_DEBUG_KMS("FDI train done.\n");
2692 }
2693
2694 /* Manual link training for Ivy Bridge A0 parts */
ivb_manual_fdi_link_train(struct drm_crtc * crtc)2695 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2696 {
2697 struct drm_device *dev = crtc->dev;
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2700 int pipe = intel_crtc->pipe;
2701 u32 reg, temp, i;
2702
2703 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2704 for train result */
2705 reg = FDI_RX_IMR(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_RX_SYMBOL_LOCK;
2708 temp &= ~FDI_RX_BIT_LOCK;
2709 I915_WRITE(reg, temp);
2710
2711 POSTING_READ(reg);
2712 udelay(150);
2713
2714 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2715 I915_READ(FDI_RX_IIR(pipe)));
2716
2717 /* enable CPU FDI TX and PCH FDI RX */
2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~(7 << 19);
2721 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2722 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2723 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2724 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2726 temp |= FDI_COMPOSITE_SYNC;
2727 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2728
2729 I915_WRITE(FDI_RX_MISC(pipe),
2730 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2731
2732 reg = FDI_RX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 temp &= ~FDI_LINK_TRAIN_AUTO;
2735 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(150);
2742
2743 for (i = 0; i < 4; i++) {
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2747 temp |= snb_b_fdi_train_param[i];
2748 I915_WRITE(reg, temp);
2749
2750 POSTING_READ(reg);
2751 udelay(500);
2752
2753 reg = FDI_RX_IIR(pipe);
2754 temp = I915_READ(reg);
2755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2756
2757 if (temp & FDI_RX_BIT_LOCK ||
2758 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2759 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2760 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2761 break;
2762 }
2763 }
2764 if (i == 4)
2765 DRM_ERROR("FDI train 1 fail!\n");
2766
2767 /* Train 2 */
2768 reg = FDI_TX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2771 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2772 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2773 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2774 I915_WRITE(reg, temp);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2779 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2780 I915_WRITE(reg, temp);
2781
2782 POSTING_READ(reg);
2783 udelay(150);
2784
2785 for (i = 0; i < 4; i++) {
2786 reg = FDI_TX_CTL(pipe);
2787 temp = I915_READ(reg);
2788 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2789 temp |= snb_b_fdi_train_param[i];
2790 I915_WRITE(reg, temp);
2791
2792 POSTING_READ(reg);
2793 udelay(500);
2794
2795 reg = FDI_RX_IIR(pipe);
2796 temp = I915_READ(reg);
2797 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2798
2799 if (temp & FDI_RX_SYMBOL_LOCK) {
2800 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2801 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2802 break;
2803 }
2804 }
2805 if (i == 4)
2806 DRM_ERROR("FDI train 2 fail!\n");
2807
2808 DRM_DEBUG_KMS("FDI train done.\n");
2809 }
2810
ironlake_fdi_pll_enable(struct intel_crtc * intel_crtc)2811 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2812 {
2813 struct drm_device *dev = intel_crtc->base.dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818
2819 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2820 reg = FDI_RX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 temp &= ~((0x7 << 19) | (0x7 << 16));
2823 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2826
2827 POSTING_READ(reg);
2828 udelay(200);
2829
2830 /* Switch from Rawclk to PCDclk */
2831 temp = I915_READ(reg);
2832 I915_WRITE(reg, temp | FDI_PCDCLK);
2833
2834 POSTING_READ(reg);
2835 udelay(200);
2836
2837 /* On Haswell, the PLL configuration for ports and pipes is handled
2838 * separately, as part of DDI setup */
2839 if (!IS_HASWELL(dev)) {
2840 /* Enable CPU FDI TX PLL, always on for Ironlake */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2844 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2845
2846 POSTING_READ(reg);
2847 udelay(100);
2848 }
2849 }
2850 }
2851
ironlake_fdi_pll_disable(struct intel_crtc * intel_crtc)2852 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2853 {
2854 struct drm_device *dev = intel_crtc->base.dev;
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856 int pipe = intel_crtc->pipe;
2857 u32 reg, temp;
2858
2859 /* Switch from PCDclk to Rawclk */
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2863
2864 /* Disable CPU FDI TX PLL */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871
2872 reg = FDI_RX_CTL(pipe);
2873 temp = I915_READ(reg);
2874 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2875
2876 /* Wait for the clocks to turn off. */
2877 POSTING_READ(reg);
2878 udelay(100);
2879 }
2880
ironlake_fdi_disable(struct drm_crtc * crtc)2881 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2882 {
2883 struct drm_device *dev = crtc->dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2886 int pipe = intel_crtc->pipe;
2887 u32 reg, temp;
2888
2889 /* disable CPU FDI tx and PCH FDI rx */
2890 reg = FDI_TX_CTL(pipe);
2891 temp = I915_READ(reg);
2892 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2893 POSTING_READ(reg);
2894
2895 reg = FDI_RX_CTL(pipe);
2896 temp = I915_READ(reg);
2897 temp &= ~(0x7 << 16);
2898 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2899 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2900
2901 POSTING_READ(reg);
2902 udelay(100);
2903
2904 /* Ironlake workaround, disable clock pointer after downing FDI */
2905 if (HAS_PCH_IBX(dev)) {
2906 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2907 }
2908
2909 /* still set train pattern 1 */
2910 reg = FDI_TX_CTL(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_LINK_TRAIN_NONE;
2913 temp |= FDI_LINK_TRAIN_PATTERN_1;
2914 I915_WRITE(reg, temp);
2915
2916 reg = FDI_RX_CTL(pipe);
2917 temp = I915_READ(reg);
2918 if (HAS_PCH_CPT(dev)) {
2919 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2920 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2921 } else {
2922 temp &= ~FDI_LINK_TRAIN_NONE;
2923 temp |= FDI_LINK_TRAIN_PATTERN_1;
2924 }
2925 /* BPC in FDI rx is consistent with that in PIPECONF */
2926 temp &= ~(0x07 << 16);
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2928 I915_WRITE(reg, temp);
2929
2930 POSTING_READ(reg);
2931 udelay(100);
2932 }
2933
intel_crtc_has_pending_flip(struct drm_crtc * crtc)2934 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2935 {
2936 struct drm_device *dev = crtc->dev;
2937 struct drm_i915_private *dev_priv = dev->dev_private;
2938 bool pending;
2939
2940 if (atomic_read(&dev_priv->mm.wedged))
2941 return false;
2942
2943 /*
2944 * NOTE Linux<->FreeBSD dev->event_lock is already locked in
2945 * intel_crtc_wait_for_pending_flips().
2946 */
2947 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2948
2949 return pending;
2950 }
2951
intel_crtc_wait_for_pending_flips(struct drm_crtc * crtc)2952 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2953 {
2954 struct drm_device *dev = crtc->dev;
2955 struct drm_i915_private *dev_priv = dev->dev_private;
2956
2957 if (crtc->fb == NULL)
2958 return;
2959
2960 mtx_lock(&dev->event_lock);
2961 while (intel_crtc_has_pending_flip(crtc)) {
2962 msleep(&dev_priv->pending_flip_queue, &dev->event_lock,
2963 0, "915flp", 0);
2964 }
2965 mtx_unlock(&dev->event_lock);
2966
2967 DRM_LOCK(dev);
2968 intel_finish_fb(crtc->fb);
2969 DRM_UNLOCK(dev);
2970 }
2971
ironlake_crtc_driving_pch(struct drm_crtc * crtc)2972 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2973 {
2974 struct drm_device *dev = crtc->dev;
2975 struct intel_encoder *intel_encoder;
2976
2977 /*
2978 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2979 * must be driven by its own crtc; no sharing is possible.
2980 */
2981 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2982 switch (intel_encoder->type) {
2983 case INTEL_OUTPUT_EDP:
2984 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2985 return false;
2986 continue;
2987 }
2988 }
2989
2990 return true;
2991 }
2992
haswell_crtc_driving_pch(struct drm_crtc * crtc)2993 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2994 {
2995 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2996 }
2997
2998 /* Program iCLKIP clock to the desired frequency */
lpt_program_iclkip(struct drm_crtc * crtc)2999 static void lpt_program_iclkip(struct drm_crtc *crtc)
3000 {
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3004 u32 temp;
3005
3006 /* It is necessary to ungate the pixclk gate prior to programming
3007 * the divisors, and gate it back when it is done.
3008 */
3009 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3010
3011 /* Disable SSCCTL */
3012 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3013 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3014 SBI_SSCCTL_DISABLE,
3015 SBI_ICLK);
3016
3017 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3018 if (crtc->mode.clock == 20000) {
3019 auxdiv = 1;
3020 divsel = 0x41;
3021 phaseinc = 0x20;
3022 } else {
3023 /* The iCLK virtual clock root frequency is in MHz,
3024 * but the crtc->mode.clock in in KHz. To get the divisors,
3025 * it is necessary to divide one by another, so we
3026 * convert the virtual clock precision to KHz here for higher
3027 * precision.
3028 */
3029 u32 iclk_virtual_root_freq = 172800 * 1000;
3030 u32 iclk_pi_range = 64;
3031 u32 desired_divisor, msb_divisor_value, pi_value;
3032
3033 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3034 msb_divisor_value = desired_divisor / iclk_pi_range;
3035 pi_value = desired_divisor % iclk_pi_range;
3036
3037 auxdiv = 0;
3038 divsel = msb_divisor_value - 2;
3039 phaseinc = pi_value;
3040 }
3041
3042 /* This should not happen with any sane values */
3043 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3044 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3046 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3047
3048 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3049 crtc->mode.clock,
3050 auxdiv,
3051 divsel,
3052 phasedir,
3053 phaseinc);
3054
3055 /* Program SSCDIVINTPHASE6 */
3056 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3057 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3058 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3059 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3060 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3061 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3062 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3063 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3064
3065 /* Program SSCAUXDIV */
3066 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3067 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3068 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3069 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3070
3071 /* Enable modulator and associated divider */
3072 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3073 temp &= ~SBI_SSCCTL_DISABLE;
3074 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3075
3076 /* Wait for initialization time */
3077 udelay(24);
3078
3079 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3080 }
3081
3082 /*
3083 * Enable PCH resources required for PCH ports:
3084 * - PCH PLLs
3085 * - FDI training & RX/TX
3086 * - update transcoder timings
3087 * - DP transcoding bits
3088 * - transcoder
3089 */
ironlake_pch_enable(struct drm_crtc * crtc)3090 static void ironlake_pch_enable(struct drm_crtc *crtc)
3091 {
3092 struct drm_device *dev = crtc->dev;
3093 struct drm_i915_private *dev_priv = dev->dev_private;
3094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3095 int pipe = intel_crtc->pipe;
3096 u32 reg, temp;
3097
3098 assert_transcoder_disabled(dev_priv, pipe);
3099
3100 /* Write the TU size bits before fdi link training, so that error
3101 * detection works. */
3102 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3103 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3104
3105 /* For PCH output, training FDI link */
3106 dev_priv->display.fdi_link_train(crtc);
3107
3108 /* XXX: pch pll's can be enabled any time before we enable the PCH
3109 * transcoder, and we actually should do this to not upset any PCH
3110 * transcoder that already use the clock when we share it.
3111 *
3112 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3113 * unconditionally resets the pll - we need that to have the right LVDS
3114 * enable sequence. */
3115 ironlake_enable_pch_pll(intel_crtc);
3116
3117 if (HAS_PCH_CPT(dev)) {
3118 u32 sel;
3119
3120 temp = I915_READ(PCH_DPLL_SEL);
3121 switch (pipe) {
3122 default:
3123 case 0:
3124 temp |= TRANSA_DPLL_ENABLE;
3125 sel = TRANSA_DPLLB_SEL;
3126 break;
3127 case 1:
3128 temp |= TRANSB_DPLL_ENABLE;
3129 sel = TRANSB_DPLLB_SEL;
3130 break;
3131 case 2:
3132 temp |= TRANSC_DPLL_ENABLE;
3133 sel = TRANSC_DPLLB_SEL;
3134 break;
3135 }
3136 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3137 temp |= sel;
3138 else
3139 temp &= ~sel;
3140 I915_WRITE(PCH_DPLL_SEL, temp);
3141 }
3142
3143 /* set transcoder timing, panel must allow it */
3144 assert_panel_unlocked(dev_priv, pipe);
3145 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3146 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3147 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3148
3149 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3150 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3151 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3152 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3153
3154 intel_fdi_normal_train(crtc);
3155
3156 /* For PCH DP, enable TRANS_DP_CTL */
3157 if (HAS_PCH_CPT(dev) &&
3158 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3159 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3160 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3161 reg = TRANS_DP_CTL(pipe);
3162 temp = I915_READ(reg);
3163 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3164 TRANS_DP_SYNC_MASK |
3165 TRANS_DP_BPC_MASK);
3166 temp |= (TRANS_DP_OUTPUT_ENABLE |
3167 TRANS_DP_ENH_FRAMING);
3168 temp |= bpc << 9; /* same format but at 11:9 */
3169
3170 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3171 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3172 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3173 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3174
3175 switch (intel_trans_dp_port_sel(crtc)) {
3176 case PCH_DP_B:
3177 temp |= TRANS_DP_PORT_SEL_B;
3178 break;
3179 case PCH_DP_C:
3180 temp |= TRANS_DP_PORT_SEL_C;
3181 break;
3182 case PCH_DP_D:
3183 temp |= TRANS_DP_PORT_SEL_D;
3184 break;
3185 default:
3186 BUG();
3187 }
3188
3189 I915_WRITE(reg, temp);
3190 }
3191
3192 ironlake_enable_pch_transcoder(dev_priv, pipe);
3193 }
3194
lpt_pch_enable(struct drm_crtc * crtc)3195 static void lpt_pch_enable(struct drm_crtc *crtc)
3196 {
3197 struct drm_device *dev = crtc->dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3201
3202 assert_transcoder_disabled(dev_priv, (enum pipe)TRANSCODER_A);
3203
3204 lpt_program_iclkip(crtc);
3205
3206 /* Set transcoder timing. */
3207 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3208 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3209 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3210
3211 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3212 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3213 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3214 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3215
3216 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3217 }
3218
intel_put_pch_pll(struct intel_crtc * intel_crtc)3219 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3220 {
3221 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3222
3223 if (pll == NULL)
3224 return;
3225
3226 if (pll->refcount == 0) {
3227 WARN(1, "bad PCH PLL refcount\n");
3228 return;
3229 }
3230
3231 --pll->refcount;
3232 intel_crtc->pch_pll = NULL;
3233 }
3234
intel_get_pch_pll(struct intel_crtc * intel_crtc,u32 dpll,u32 fp)3235 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3236 {
3237 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3238 struct intel_pch_pll *pll;
3239 int i;
3240
3241 pll = intel_crtc->pch_pll;
3242 if (pll) {
3243 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3244 intel_crtc->base.base.id, pll->pll_reg);
3245 goto prepare;
3246 }
3247
3248 if (HAS_PCH_IBX(dev_priv->dev)) {
3249 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3250 i = intel_crtc->pipe;
3251 pll = &dev_priv->pch_plls[i];
3252
3253 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3254 intel_crtc->base.base.id, pll->pll_reg);
3255
3256 goto found;
3257 }
3258
3259 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3260 pll = &dev_priv->pch_plls[i];
3261
3262 /* Only want to check enabled timings first */
3263 if (pll->refcount == 0)
3264 continue;
3265
3266 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3267 fp == I915_READ(pll->fp0_reg)) {
3268 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3269 intel_crtc->base.base.id,
3270 pll->pll_reg, pll->refcount, pll->active);
3271
3272 goto found;
3273 }
3274 }
3275
3276 /* Ok no matching timings, maybe there's a free one? */
3277 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3278 pll = &dev_priv->pch_plls[i];
3279 if (pll->refcount == 0) {
3280 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3281 intel_crtc->base.base.id, pll->pll_reg);
3282 goto found;
3283 }
3284 }
3285
3286 return NULL;
3287
3288 found:
3289 intel_crtc->pch_pll = pll;
3290 pll->refcount++;
3291 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3292 prepare: /* separate function? */
3293 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3294
3295 /* Wait for the clocks to stabilize before rewriting the regs */
3296 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3297 POSTING_READ(pll->pll_reg);
3298 udelay(150);
3299
3300 I915_WRITE(pll->fp0_reg, fp);
3301 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3302 pll->on = false;
3303 return pll;
3304 }
3305
intel_cpt_verify_modeset(struct drm_device * dev,int pipe)3306 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3307 {
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 int dslreg = PIPEDSL(pipe);
3310 u32 temp;
3311
3312 temp = I915_READ(dslreg);
3313 udelay(500);
3314 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3315 if (wait_for(I915_READ(dslreg) != temp, 5))
3316 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3317 }
3318 }
3319
ironlake_crtc_enable(struct drm_crtc * crtc)3320 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3321 {
3322 struct drm_device *dev = crtc->dev;
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3325 struct intel_encoder *encoder;
3326 int pipe = intel_crtc->pipe;
3327 int plane = intel_crtc->plane;
3328 u32 temp;
3329 bool is_pch_port;
3330
3331 WARN_ON(!crtc->enabled);
3332
3333 if (intel_crtc->active)
3334 return;
3335
3336 intel_crtc->active = true;
3337 intel_update_watermarks(dev);
3338
3339 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3340 temp = I915_READ(PCH_LVDS);
3341 if ((temp & LVDS_PORT_EN) == 0)
3342 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3343 }
3344
3345 is_pch_port = ironlake_crtc_driving_pch(crtc);
3346
3347 if (is_pch_port) {
3348 /* Note: FDI PLL enabling _must_ be done before we enable the
3349 * cpu pipes, hence this is separate from all the other fdi/pch
3350 * enabling. */
3351 ironlake_fdi_pll_enable(intel_crtc);
3352 } else {
3353 assert_fdi_tx_disabled(dev_priv, pipe);
3354 assert_fdi_rx_disabled(dev_priv, pipe);
3355 }
3356
3357 for_each_encoder_on_crtc(dev, crtc, encoder)
3358 if (encoder->pre_enable)
3359 encoder->pre_enable(encoder);
3360
3361 /* Enable panel fitting for LVDS */
3362 if (dev_priv->pch_pf_size &&
3363 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3364 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3365 /* Force use of hard-coded filter coefficients
3366 * as some pre-programmed values are broken,
3367 * e.g. x201.
3368 */
3369 if (IS_IVYBRIDGE(dev))
3370 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3371 PF_PIPE_SEL_IVB(pipe));
3372 else
3373 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3374 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3375 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3376 }
3377
3378 /*
3379 * On ILK+ LUT must be loaded before the pipe is running but with
3380 * clocks enabled
3381 */
3382 intel_crtc_load_lut(crtc);
3383
3384 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3385 intel_enable_plane(dev_priv, plane, pipe);
3386
3387 if (is_pch_port)
3388 ironlake_pch_enable(crtc);
3389
3390 DRM_LOCK(dev);
3391 intel_update_fbc(dev);
3392 DRM_UNLOCK(dev);
3393
3394 intel_crtc_update_cursor(crtc, true);
3395
3396 for_each_encoder_on_crtc(dev, crtc, encoder)
3397 encoder->enable(encoder);
3398
3399 if (HAS_PCH_CPT(dev))
3400 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3401
3402 /*
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happened, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3408 * happening.
3409 */
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3411 }
3412
haswell_crtc_enable(struct drm_crtc * crtc)3413 static void haswell_crtc_enable(struct drm_crtc *crtc)
3414 {
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3418 struct intel_encoder *encoder;
3419 int pipe = intel_crtc->pipe;
3420 int plane = intel_crtc->plane;
3421 bool is_pch_port;
3422
3423 WARN_ON(!crtc->enabled);
3424
3425 if (intel_crtc->active)
3426 return;
3427
3428 intel_crtc->active = true;
3429 intel_update_watermarks(dev);
3430
3431 is_pch_port = haswell_crtc_driving_pch(crtc);
3432
3433 if (is_pch_port)
3434 dev_priv->display.fdi_link_train(crtc);
3435
3436 for_each_encoder_on_crtc(dev, crtc, encoder)
3437 if (encoder->pre_enable)
3438 encoder->pre_enable(encoder);
3439
3440 intel_ddi_enable_pipe_clock(intel_crtc);
3441
3442 /* Enable panel fitting for eDP */
3443 if (dev_priv->pch_pf_size &&
3444 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3445 /* Force use of hard-coded filter coefficients
3446 * as some pre-programmed values are broken,
3447 * e.g. x201.
3448 */
3449 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3450 PF_PIPE_SEL_IVB(pipe));
3451 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3452 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3453 }
3454
3455 /*
3456 * On ILK+ LUT must be loaded before the pipe is running but with
3457 * clocks enabled
3458 */
3459 intel_crtc_load_lut(crtc);
3460
3461 intel_ddi_set_pipe_settings(crtc);
3462 intel_ddi_enable_pipe_func(crtc);
3463
3464 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3465 intel_enable_plane(dev_priv, plane, pipe);
3466
3467 if (is_pch_port)
3468 lpt_pch_enable(crtc);
3469
3470 DRM_LOCK(dev);
3471 intel_update_fbc(dev);
3472 DRM_UNLOCK(dev);
3473
3474 intel_crtc_update_cursor(crtc, true);
3475
3476 for_each_encoder_on_crtc(dev, crtc, encoder)
3477 encoder->enable(encoder);
3478
3479 /*
3480 * There seems to be a race in PCH platform hw (at least on some
3481 * outputs) where an enabled pipe still completes any pageflip right
3482 * away (as if the pipe is off) instead of waiting for vblank. As soon
3483 * as the first vblank happened, everything works as expected. Hence just
3484 * wait for one vblank before returning to avoid strange things
3485 * happening.
3486 */
3487 intel_wait_for_vblank(dev, intel_crtc->pipe);
3488 }
3489
ironlake_crtc_disable(struct drm_crtc * crtc)3490 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3491 {
3492 struct drm_device *dev = crtc->dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3495 struct intel_encoder *encoder;
3496 int pipe = intel_crtc->pipe;
3497 int plane = intel_crtc->plane;
3498 u32 reg, temp;
3499
3500
3501 if (!intel_crtc->active)
3502 return;
3503
3504 for_each_encoder_on_crtc(dev, crtc, encoder)
3505 encoder->disable(encoder);
3506
3507 intel_crtc_wait_for_pending_flips(crtc);
3508 drm_vblank_off(dev, pipe);
3509 intel_crtc_update_cursor(crtc, false);
3510
3511 intel_disable_plane(dev_priv, plane, pipe);
3512
3513 if (dev_priv->cfb_plane == plane)
3514 intel_disable_fbc(dev);
3515
3516 intel_disable_pipe(dev_priv, pipe);
3517
3518 /* Disable PF */
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3521
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 if (encoder->post_disable)
3524 encoder->post_disable(encoder);
3525
3526 ironlake_fdi_disable(crtc);
3527
3528 ironlake_disable_pch_transcoder(dev_priv, pipe);
3529
3530 if (HAS_PCH_CPT(dev)) {
3531 /* disable TRANS_DP_CTL */
3532 reg = TRANS_DP_CTL(pipe);
3533 temp = I915_READ(reg);
3534 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3535 temp |= TRANS_DP_PORT_SEL_NONE;
3536 I915_WRITE(reg, temp);
3537
3538 /* disable DPLL_SEL */
3539 temp = I915_READ(PCH_DPLL_SEL);
3540 switch (pipe) {
3541 case 0:
3542 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3543 break;
3544 case 1:
3545 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3546 break;
3547 case 2:
3548 /* C shares PLL A or B */
3549 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3550 break;
3551 default:
3552 BUG(); /* wtf */
3553 }
3554 I915_WRITE(PCH_DPLL_SEL, temp);
3555 }
3556
3557 /* disable PCH DPLL */
3558 intel_disable_pch_pll(intel_crtc);
3559
3560 ironlake_fdi_pll_disable(intel_crtc);
3561
3562 intel_crtc->active = false;
3563 intel_update_watermarks(dev);
3564
3565 DRM_LOCK(dev);
3566 intel_update_fbc(dev);
3567 DRM_UNLOCK(dev);
3568 }
3569
haswell_crtc_disable(struct drm_crtc * crtc)3570 static void haswell_crtc_disable(struct drm_crtc *crtc)
3571 {
3572 struct drm_device *dev = crtc->dev;
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3575 struct intel_encoder *encoder;
3576 int pipe = intel_crtc->pipe;
3577 int plane = intel_crtc->plane;
3578 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3579 bool is_pch_port;
3580
3581 if (!intel_crtc->active)
3582 return;
3583
3584 is_pch_port = haswell_crtc_driving_pch(crtc);
3585
3586 for_each_encoder_on_crtc(dev, crtc, encoder)
3587 encoder->disable(encoder);
3588
3589 intel_crtc_wait_for_pending_flips(crtc);
3590 drm_vblank_off(dev, pipe);
3591 intel_crtc_update_cursor(crtc, false);
3592
3593 intel_disable_plane(dev_priv, plane, pipe);
3594
3595 if (dev_priv->cfb_plane == plane)
3596 intel_disable_fbc(dev);
3597
3598 intel_disable_pipe(dev_priv, pipe);
3599
3600 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3601
3602 /* Disable PF */
3603 I915_WRITE(PF_CTL(pipe), 0);
3604 I915_WRITE(PF_WIN_SZ(pipe), 0);
3605
3606 intel_ddi_disable_pipe_clock(intel_crtc);
3607
3608 for_each_encoder_on_crtc(dev, crtc, encoder)
3609 if (encoder->post_disable)
3610 encoder->post_disable(encoder);
3611
3612 if (is_pch_port) {
3613 lpt_disable_pch_transcoder(dev_priv);
3614 intel_ddi_fdi_disable(crtc);
3615 }
3616
3617 intel_crtc->active = false;
3618 intel_update_watermarks(dev);
3619
3620 DRM_LOCK(dev);
3621 intel_update_fbc(dev);
3622 DRM_UNLOCK(dev);
3623 }
3624
ironlake_crtc_off(struct drm_crtc * crtc)3625 static void ironlake_crtc_off(struct drm_crtc *crtc)
3626 {
3627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628 intel_put_pch_pll(intel_crtc);
3629 }
3630
haswell_crtc_off(struct drm_crtc * crtc)3631 static void haswell_crtc_off(struct drm_crtc *crtc)
3632 {
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634
3635 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3636 * start using it. */
3637 intel_crtc->cpu_transcoder = (enum transcoder)intel_crtc->pipe;
3638
3639 intel_ddi_put_crtc_pll(crtc);
3640 }
3641
intel_crtc_dpms_overlay(struct intel_crtc * intel_crtc,bool enable)3642 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3643 {
3644 if (!enable && intel_crtc->overlay) {
3645 struct drm_device *dev = intel_crtc->base.dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647
3648 DRM_LOCK(dev);
3649 dev_priv->mm.interruptible = false;
3650 (void) intel_overlay_switch_off(intel_crtc->overlay);
3651 dev_priv->mm.interruptible = true;
3652 DRM_UNLOCK(dev);
3653 }
3654
3655 /* Let userspace switch the overlay on again. In most cases userspace
3656 * has to recompute where to put it anyway.
3657 */
3658 }
3659
i9xx_crtc_enable(struct drm_crtc * crtc)3660 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3661 {
3662 struct drm_device *dev = crtc->dev;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3665 struct intel_encoder *encoder;
3666 int pipe = intel_crtc->pipe;
3667 int plane = intel_crtc->plane;
3668
3669 WARN_ON(!crtc->enabled);
3670
3671 if (intel_crtc->active)
3672 return;
3673
3674 intel_crtc->active = true;
3675 intel_update_watermarks(dev);
3676
3677 intel_enable_pll(dev_priv, pipe);
3678 intel_enable_pipe(dev_priv, pipe, false);
3679 intel_enable_plane(dev_priv, plane, pipe);
3680
3681 intel_crtc_load_lut(crtc);
3682 intel_update_fbc(dev);
3683
3684 /* Give the overlay scaler a chance to enable if it's on this pipe */
3685 intel_crtc_dpms_overlay(intel_crtc, true);
3686 intel_crtc_update_cursor(crtc, true);
3687
3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 encoder->enable(encoder);
3690 }
3691
i9xx_crtc_disable(struct drm_crtc * crtc)3692 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3693 {
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697 struct intel_encoder *encoder;
3698 int pipe = intel_crtc->pipe;
3699 int plane = intel_crtc->plane;
3700 u32 pctl;
3701
3702
3703 if (!intel_crtc->active)
3704 return;
3705
3706 for_each_encoder_on_crtc(dev, crtc, encoder)
3707 encoder->disable(encoder);
3708
3709 /* Give the overlay scaler a chance to disable if it's on this pipe */
3710 intel_crtc_wait_for_pending_flips(crtc);
3711 drm_vblank_off(dev, pipe);
3712 intel_crtc_dpms_overlay(intel_crtc, false);
3713 intel_crtc_update_cursor(crtc, false);
3714
3715 if (dev_priv->cfb_plane == plane)
3716 intel_disable_fbc(dev);
3717
3718 intel_disable_plane(dev_priv, plane, pipe);
3719 intel_disable_pipe(dev_priv, pipe);
3720
3721 /* Disable pannel fitter if it is on this pipe. */
3722 pctl = I915_READ(PFIT_CONTROL);
3723 if ((pctl & PFIT_ENABLE) &&
3724 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3725 I915_WRITE(PFIT_CONTROL, 0);
3726
3727 intel_disable_pll(dev_priv, pipe);
3728
3729 intel_crtc->active = false;
3730 intel_update_fbc(dev);
3731 intel_update_watermarks(dev);
3732 }
3733
i9xx_crtc_off(struct drm_crtc * crtc)3734 static void i9xx_crtc_off(struct drm_crtc *crtc)
3735 {
3736 }
3737
intel_crtc_update_sarea(struct drm_crtc * crtc,bool enabled)3738 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3739 bool enabled)
3740 {
3741 struct drm_device *dev = crtc->dev;
3742 struct drm_i915_master_private *master_priv;
3743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3744 int pipe = intel_crtc->pipe;
3745
3746 if (!dev->primary->master)
3747 return;
3748
3749 master_priv = dev->primary->master->driver_priv;
3750 if (!master_priv->sarea_priv)
3751 return;
3752
3753 switch (pipe) {
3754 case 0:
3755 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3756 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3757 break;
3758 case 1:
3759 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3760 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3761 break;
3762 default:
3763 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3764 break;
3765 }
3766 }
3767
3768 /**
3769 * Sets the power management mode of the pipe and plane.
3770 */
intel_crtc_update_dpms(struct drm_crtc * crtc)3771 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3772 {
3773 struct drm_device *dev = crtc->dev;
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775 struct intel_encoder *intel_encoder;
3776 bool enable = false;
3777
3778 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3779 enable |= intel_encoder->connectors_active;
3780
3781 if (enable)
3782 dev_priv->display.crtc_enable(crtc);
3783 else
3784 dev_priv->display.crtc_disable(crtc);
3785
3786 intel_crtc_update_sarea(crtc, enable);
3787 }
3788
intel_crtc_noop(struct drm_crtc * crtc)3789 static void intel_crtc_noop(struct drm_crtc *crtc)
3790 {
3791 }
3792
intel_crtc_disable(struct drm_crtc * crtc)3793 static void intel_crtc_disable(struct drm_crtc *crtc)
3794 {
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_connector *connector;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798
3799 /* crtc should still be enabled when we disable it. */
3800 WARN_ON(!crtc->enabled);
3801
3802 dev_priv->display.crtc_disable(crtc);
3803 intel_crtc_update_sarea(crtc, false);
3804 dev_priv->display.off(crtc);
3805
3806 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3807 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3808
3809 if (crtc->fb) {
3810 DRM_LOCK(dev);
3811 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3812 DRM_UNLOCK(dev);
3813 crtc->fb = NULL;
3814 }
3815
3816 /* Update computed state. */
3817 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3818 if (!connector->encoder || !connector->encoder->crtc)
3819 continue;
3820
3821 if (connector->encoder->crtc != crtc)
3822 continue;
3823
3824 connector->dpms = DRM_MODE_DPMS_OFF;
3825 to_intel_encoder(connector->encoder)->connectors_active = false;
3826 }
3827 }
3828
intel_modeset_disable(struct drm_device * dev)3829 void intel_modeset_disable(struct drm_device *dev)
3830 {
3831 struct drm_crtc *crtc;
3832
3833 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3834 if (crtc->enabled)
3835 intel_crtc_disable(crtc);
3836 }
3837 }
3838
intel_encoder_noop(struct drm_encoder * encoder)3839 void intel_encoder_noop(struct drm_encoder *encoder)
3840 {
3841 }
3842
intel_encoder_destroy(struct drm_encoder * encoder)3843 void intel_encoder_destroy(struct drm_encoder *encoder)
3844 {
3845 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3846
3847 drm_encoder_cleanup(encoder);
3848 free(intel_encoder, DRM_MEM_KMS);
3849 }
3850
3851 /* Simple dpms helper for encodres with just one connector, no cloning and only
3852 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3853 * state of the entire output pipe. */
intel_encoder_dpms(struct intel_encoder * encoder,int mode)3854 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3855 {
3856 if (mode == DRM_MODE_DPMS_ON) {
3857 encoder->connectors_active = true;
3858
3859 intel_crtc_update_dpms(encoder->base.crtc);
3860 } else {
3861 encoder->connectors_active = false;
3862
3863 intel_crtc_update_dpms(encoder->base.crtc);
3864 }
3865 }
3866
3867 /* Cross check the actual hw state with our own modeset state tracking (and it's
3868 * internal consistency). */
intel_connector_check_state(struct intel_connector * connector)3869 static void intel_connector_check_state(struct intel_connector *connector)
3870 {
3871 if (connector->get_hw_state(connector)) {
3872 struct intel_encoder *encoder = connector->encoder;
3873 struct drm_crtc *crtc;
3874 bool encoder_enabled;
3875 enum pipe pipe;
3876
3877 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3878 connector->base.base.id,
3879 drm_get_connector_name(&connector->base));
3880
3881 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3882 "wrong connector dpms state\n");
3883 WARN(connector->base.encoder != &encoder->base,
3884 "active connector not linked to encoder\n");
3885 WARN(!encoder->connectors_active,
3886 "encoder->connectors_active not set\n");
3887
3888 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3889 WARN(!encoder_enabled, "encoder not enabled\n");
3890 if (WARN_ON(!encoder->base.crtc))
3891 return;
3892
3893 crtc = encoder->base.crtc;
3894
3895 WARN(!crtc->enabled, "crtc not enabled\n");
3896 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3897 WARN(pipe != to_intel_crtc(crtc)->pipe,
3898 "encoder active on the wrong pipe\n");
3899 }
3900 }
3901
3902 /* Even simpler default implementation, if there's really no special case to
3903 * consider. */
intel_connector_dpms(struct drm_connector * connector,int mode)3904 void intel_connector_dpms(struct drm_connector *connector, int mode)
3905 {
3906 struct intel_encoder *encoder = intel_attached_encoder(connector);
3907
3908 /* All the simple cases only support two dpms states. */
3909 if (mode != DRM_MODE_DPMS_ON)
3910 mode = DRM_MODE_DPMS_OFF;
3911
3912 if (mode == connector->dpms)
3913 return;
3914
3915 connector->dpms = mode;
3916
3917 /* Only need to change hw state when actually enabled */
3918 if (encoder->base.crtc)
3919 intel_encoder_dpms(encoder, mode);
3920 else
3921 WARN_ON(encoder->connectors_active != false);
3922
3923 intel_modeset_check_state(connector->dev);
3924 }
3925
3926 /* Simple connector->get_hw_state implementation for encoders that support only
3927 * one connector and no cloning and hence the encoder state determines the state
3928 * of the connector. */
intel_connector_get_hw_state(struct intel_connector * connector)3929 bool intel_connector_get_hw_state(struct intel_connector *connector)
3930 {
3931 enum pipe pipe = 0;
3932 struct intel_encoder *encoder = connector->encoder;
3933
3934 return encoder->get_hw_state(encoder, &pipe);
3935 }
3936
intel_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)3937 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3938 const struct drm_display_mode *mode,
3939 struct drm_display_mode *adjusted_mode)
3940 {
3941 struct drm_device *dev = crtc->dev;
3942
3943 if (HAS_PCH_SPLIT(dev)) {
3944 /* FDI link clock is fixed at 2.7G */
3945 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3946 return false;
3947 }
3948
3949 /* All interlaced capable intel hw wants timings in frames. Note though
3950 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3951 * timings, so we need to be careful not to clobber these.*/
3952 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3953 drm_mode_set_crtcinfo(adjusted_mode, 0);
3954
3955 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3956 * with a hsync front porch of 0.
3957 */
3958 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3959 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3960 return false;
3961
3962 return true;
3963 }
3964
valleyview_get_display_clock_speed(struct drm_device * dev)3965 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3966 {
3967 return 400000; /* FIXME */
3968 }
3969
i945_get_display_clock_speed(struct drm_device * dev)3970 static int i945_get_display_clock_speed(struct drm_device *dev)
3971 {
3972 return 400000;
3973 }
3974
i915_get_display_clock_speed(struct drm_device * dev)3975 static int i915_get_display_clock_speed(struct drm_device *dev)
3976 {
3977 return 333000;
3978 }
3979
i9xx_misc_get_display_clock_speed(struct drm_device * dev)3980 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3981 {
3982 return 200000;
3983 }
3984
i915gm_get_display_clock_speed(struct drm_device * dev)3985 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3986 {
3987 u16 gcfgc = 0;
3988
3989 pci_read_config_word(dev->dev, GCFGC, &gcfgc);
3990
3991 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3992 return 133000;
3993 else {
3994 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3995 case GC_DISPLAY_CLOCK_333_MHZ:
3996 return 333000;
3997 default:
3998 case GC_DISPLAY_CLOCK_190_200_MHZ:
3999 return 190000;
4000 }
4001 }
4002 }
4003
i865_get_display_clock_speed(struct drm_device * dev)4004 static int i865_get_display_clock_speed(struct drm_device *dev)
4005 {
4006 return 266000;
4007 }
4008
i855_get_display_clock_speed(struct drm_device * dev)4009 static int i855_get_display_clock_speed(struct drm_device *dev)
4010 {
4011 u16 hpllcc = 0;
4012 /* Assume that the hardware is in the high speed state. This
4013 * should be the default.
4014 */
4015 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4016 case GC_CLOCK_133_200:
4017 case GC_CLOCK_100_200:
4018 return 200000;
4019 case GC_CLOCK_166_250:
4020 return 250000;
4021 case GC_CLOCK_100_133:
4022 return 133000;
4023 }
4024
4025 /* Shouldn't happen */
4026 return 0;
4027 }
4028
i830_get_display_clock_speed(struct drm_device * dev)4029 static int i830_get_display_clock_speed(struct drm_device *dev)
4030 {
4031 return 133000;
4032 }
4033
4034 struct fdi_m_n {
4035 u32 tu;
4036 u32 gmch_m;
4037 u32 gmch_n;
4038 u32 link_m;
4039 u32 link_n;
4040 };
4041
4042 static void
fdi_reduce_ratio(u32 * num,u32 * den)4043 fdi_reduce_ratio(u32 *num, u32 *den)
4044 {
4045 while (*num > 0xffffff || *den > 0xffffff) {
4046 *num >>= 1;
4047 *den >>= 1;
4048 }
4049 }
4050
4051 static void
ironlake_compute_m_n(int bits_per_pixel,int nlanes,int pixel_clock,int link_clock,struct fdi_m_n * m_n)4052 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4053 int link_clock, struct fdi_m_n *m_n)
4054 {
4055 m_n->tu = 64; /* default size */
4056
4057 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4058 m_n->gmch_m = bits_per_pixel * pixel_clock;
4059 m_n->gmch_n = link_clock * nlanes * 8;
4060 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4061
4062 m_n->link_m = pixel_clock;
4063 m_n->link_n = link_clock;
4064 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4065 }
4066
intel_panel_use_ssc(struct drm_i915_private * dev_priv)4067 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4068 {
4069 if (i915_panel_use_ssc >= 0)
4070 return i915_panel_use_ssc != 0;
4071 return dev_priv->lvds_use_ssc
4072 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4073 }
4074
4075 /**
4076 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4077 * @crtc: CRTC structure
4078 * @mode: requested mode
4079 *
4080 * A pipe may be connected to one or more outputs. Based on the depth of the
4081 * attached framebuffer, choose a good color depth to use on the pipe.
4082 *
4083 * If possible, match the pipe depth to the fb depth. In some cases, this
4084 * isn't ideal, because the connected output supports a lesser or restricted
4085 * set of depths. Resolve that here:
4086 * LVDS typically supports only 6bpc, so clamp down in that case
4087 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4088 * Displays may support a restricted set as well, check EDID and clamp as
4089 * appropriate.
4090 * DP may want to dither down to 6bpc to fit larger modes
4091 *
4092 * RETURNS:
4093 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4094 * true if they don't match).
4095 */
intel_choose_pipe_bpp_dither(struct drm_crtc * crtc,struct drm_framebuffer * fb,unsigned int * pipe_bpp,struct drm_display_mode * mode)4096 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4097 struct drm_framebuffer *fb,
4098 unsigned int *pipe_bpp,
4099 struct drm_display_mode *mode)
4100 {
4101 struct drm_device *dev = crtc->dev;
4102 struct drm_i915_private *dev_priv = dev->dev_private;
4103 struct drm_connector *connector;
4104 struct intel_encoder *intel_encoder;
4105 unsigned int display_bpc = UINT_MAX, bpc;
4106
4107 /* Walk the encoders & connectors on this crtc, get min bpc */
4108 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4109
4110 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4111 unsigned int lvds_bpc;
4112
4113 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4114 LVDS_A3_POWER_UP)
4115 lvds_bpc = 8;
4116 else
4117 lvds_bpc = 6;
4118
4119 if (lvds_bpc < display_bpc) {
4120 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4121 display_bpc = lvds_bpc;
4122 }
4123 continue;
4124 }
4125
4126 /* Not one of the known troublemakers, check the EDID */
4127 list_for_each_entry(connector, &dev->mode_config.connector_list,
4128 head) {
4129 if (connector->encoder != &intel_encoder->base)
4130 continue;
4131
4132 /* Don't use an invalid EDID bpc value */
4133 if (connector->display_info.bpc &&
4134 connector->display_info.bpc < display_bpc) {
4135 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4136 display_bpc = connector->display_info.bpc;
4137 }
4138 }
4139
4140 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4141 /* Use VBT settings if we have an eDP panel */
4142 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4143
4144 if (edp_bpc && edp_bpc < display_bpc) {
4145 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4146 display_bpc = edp_bpc;
4147 }
4148 continue;
4149 }
4150
4151 /*
4152 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4153 * through, clamp it down. (Note: >12bpc will be caught below.)
4154 */
4155 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4156 if (display_bpc > 8 && display_bpc < 12) {
4157 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4158 display_bpc = 12;
4159 } else {
4160 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4161 display_bpc = 8;
4162 }
4163 }
4164 }
4165
4166 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4167 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4168 display_bpc = 6;
4169 }
4170
4171 /*
4172 * We could just drive the pipe at the highest bpc all the time and
4173 * enable dithering as needed, but that costs bandwidth. So choose
4174 * the minimum value that expresses the full color range of the fb but
4175 * also stays within the max display bpc discovered above.
4176 */
4177
4178 switch (fb->depth) {
4179 case 8:
4180 bpc = 8; /* since we go through a colormap */
4181 break;
4182 case 15:
4183 case 16:
4184 bpc = 6; /* min is 18bpp */
4185 break;
4186 case 24:
4187 bpc = 8;
4188 break;
4189 case 30:
4190 bpc = 10;
4191 break;
4192 case 48:
4193 bpc = 12;
4194 break;
4195 default:
4196 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4197 bpc = min((unsigned int)8, display_bpc);
4198 break;
4199 }
4200
4201 display_bpc = min(display_bpc, bpc);
4202
4203 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4204 bpc, display_bpc);
4205
4206 *pipe_bpp = display_bpc * 3;
4207
4208 return display_bpc != bpc;
4209 }
4210
vlv_get_refclk(struct drm_crtc * crtc)4211 static int vlv_get_refclk(struct drm_crtc *crtc)
4212 {
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 int refclk = 27000; /* for DP & HDMI */
4216
4217 return 100000; /* only one validated so far */
4218
4219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4220 refclk = 96000;
4221 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4222 if (intel_panel_use_ssc(dev_priv))
4223 refclk = 100000;
4224 else
4225 refclk = 96000;
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4227 refclk = 100000;
4228 }
4229
4230 return refclk;
4231 }
4232
i9xx_get_refclk(struct drm_crtc * crtc,int num_connectors)4233 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4234 {
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 int refclk;
4238
4239 if (IS_VALLEYVIEW(dev)) {
4240 refclk = vlv_get_refclk(crtc);
4241 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4242 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4243 refclk = dev_priv->lvds_ssc_freq * 1000;
4244 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4245 refclk / 1000);
4246 } else if (!IS_GEN2(dev)) {
4247 refclk = 96000;
4248 } else {
4249 refclk = 48000;
4250 }
4251
4252 return refclk;
4253 }
4254
i9xx_adjust_sdvo_tv_clock(struct drm_display_mode * adjusted_mode,intel_clock_t * clock)4255 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4256 intel_clock_t *clock)
4257 {
4258 /* SDVO TV has fixed PLL values depend on its clock range,
4259 this mirrors vbios setting. */
4260 if (adjusted_mode->clock >= 100000
4261 && adjusted_mode->clock < 140500) {
4262 clock->p1 = 2;
4263 clock->p2 = 10;
4264 clock->n = 3;
4265 clock->m1 = 16;
4266 clock->m2 = 8;
4267 } else if (adjusted_mode->clock >= 140500
4268 && adjusted_mode->clock <= 200000) {
4269 clock->p1 = 1;
4270 clock->p2 = 10;
4271 clock->n = 6;
4272 clock->m1 = 12;
4273 clock->m2 = 8;
4274 }
4275 }
4276
i9xx_update_pll_dividers(struct drm_crtc * crtc,intel_clock_t * clock,intel_clock_t * reduced_clock)4277 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4278 intel_clock_t *clock,
4279 intel_clock_t *reduced_clock)
4280 {
4281 struct drm_device *dev = crtc->dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4284 int pipe = intel_crtc->pipe;
4285 u32 fp, fp2 = 0;
4286
4287 if (IS_PINEVIEW(dev)) {
4288 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4289 if (reduced_clock)
4290 fp2 = (1 << reduced_clock->n) << 16 |
4291 reduced_clock->m1 << 8 | reduced_clock->m2;
4292 } else {
4293 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4294 if (reduced_clock)
4295 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4296 reduced_clock->m2;
4297 }
4298
4299 I915_WRITE(FP0(pipe), fp);
4300
4301 intel_crtc->lowfreq_avail = false;
4302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4303 reduced_clock && i915_powersave) {
4304 I915_WRITE(FP1(pipe), fp2);
4305 intel_crtc->lowfreq_avail = true;
4306 } else {
4307 I915_WRITE(FP1(pipe), fp);
4308 }
4309 }
4310
intel_update_lvds(struct drm_crtc * crtc,intel_clock_t * clock,struct drm_display_mode * adjusted_mode)4311 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4312 struct drm_display_mode *adjusted_mode)
4313 {
4314 struct drm_device *dev = crtc->dev;
4315 struct drm_i915_private *dev_priv = dev->dev_private;
4316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4317 int pipe = intel_crtc->pipe;
4318 u32 temp;
4319
4320 temp = I915_READ(LVDS);
4321 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4322 if (pipe == 1) {
4323 temp |= LVDS_PIPEB_SELECT;
4324 } else {
4325 temp &= ~LVDS_PIPEB_SELECT;
4326 }
4327 /* set the corresponsding LVDS_BORDER bit */
4328 temp |= dev_priv->lvds_border_bits;
4329 /* Set the B0-B3 data pairs corresponding to whether we're going to
4330 * set the DPLLs for dual-channel mode or not.
4331 */
4332 if (clock->p2 == 7)
4333 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4334 else
4335 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4336
4337 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4338 * appropriately here, but we need to look more thoroughly into how
4339 * panels behave in the two modes.
4340 */
4341 /* set the dithering flag on LVDS as needed */
4342 if (INTEL_INFO(dev)->gen >= 4) {
4343 if (dev_priv->lvds_dither)
4344 temp |= LVDS_ENABLE_DITHER;
4345 else
4346 temp &= ~LVDS_ENABLE_DITHER;
4347 }
4348 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4349 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4350 temp |= LVDS_HSYNC_POLARITY;
4351 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4352 temp |= LVDS_VSYNC_POLARITY;
4353 I915_WRITE(LVDS, temp);
4354 }
4355
vlv_update_pll(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,intel_clock_t * clock,intel_clock_t * reduced_clock,int num_connectors)4356 static void vlv_update_pll(struct drm_crtc *crtc,
4357 struct drm_display_mode *mode,
4358 struct drm_display_mode *adjusted_mode,
4359 intel_clock_t *clock, intel_clock_t *reduced_clock,
4360 int num_connectors)
4361 {
4362 struct drm_device *dev = crtc->dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4365 int pipe = intel_crtc->pipe;
4366 u32 dpll, mdiv, pdiv;
4367 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4368 bool is_sdvo;
4369 u32 temp;
4370
4371 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4372 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4373
4374 dpll = DPLL_VGA_MODE_DIS;
4375 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4376 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4377 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4378
4379 I915_WRITE(DPLL(pipe), dpll);
4380 POSTING_READ(DPLL(pipe));
4381
4382 bestn = clock->n;
4383 bestm1 = clock->m1;
4384 bestm2 = clock->m2;
4385 bestp1 = clock->p1;
4386 bestp2 = clock->p2;
4387
4388 /*
4389 * In Valleyview PLL and program lane counter registers are exposed
4390 * through DPIO interface
4391 */
4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
4395 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4396 mdiv |= (1 << DPIO_K_SHIFT);
4397 mdiv |= DPIO_ENABLE_CALIBRATION;
4398 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4399
4400 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4401
4402 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4403 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4404 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4405 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4406 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4407
4408 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4409
4410 dpll |= DPLL_VCO_ENABLE;
4411 I915_WRITE(DPLL(pipe), dpll);
4412 POSTING_READ(DPLL(pipe));
4413 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4414 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4415
4416 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4417
4418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4419 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4420
4421 I915_WRITE(DPLL(pipe), dpll);
4422
4423 /* Wait for the clocks to stabilize. */
4424 POSTING_READ(DPLL(pipe));
4425 udelay(150);
4426
4427 temp = 0;
4428 if (is_sdvo) {
4429 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4430 if (temp > 1)
4431 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4432 else
4433 temp = 0;
4434 }
4435 I915_WRITE(DPLL_MD(pipe), temp);
4436 POSTING_READ(DPLL_MD(pipe));
4437
4438 /* Now program lane control registers */
4439 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4440 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4441 {
4442 temp = 0x1000C4;
4443 if(pipe == 1)
4444 temp |= (1 << 21);
4445 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4446 }
4447 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4448 {
4449 temp = 0x1000C4;
4450 if(pipe == 1)
4451 temp |= (1 << 21);
4452 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4453 }
4454 }
4455
i9xx_update_pll(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,intel_clock_t * clock,intel_clock_t * reduced_clock,int num_connectors)4456 static void i9xx_update_pll(struct drm_crtc *crtc,
4457 struct drm_display_mode *mode,
4458 struct drm_display_mode *adjusted_mode,
4459 intel_clock_t *clock, intel_clock_t *reduced_clock,
4460 int num_connectors)
4461 {
4462 struct drm_device *dev = crtc->dev;
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4465 int pipe = intel_crtc->pipe;
4466 u32 dpll;
4467 bool is_sdvo;
4468
4469 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4470
4471 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4473
4474 dpll = DPLL_VGA_MODE_DIS;
4475
4476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477 dpll |= DPLLB_MODE_LVDS;
4478 else
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4480 if (is_sdvo) {
4481 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482 if (pixel_multiplier > 1) {
4483 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4485 }
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4487 }
4488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490
4491 /* compute bitmask from p1 value */
4492 if (IS_PINEVIEW(dev))
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4494 else {
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496 if (IS_G4X(dev) && reduced_clock)
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4498 }
4499 switch (clock->p2) {
4500 case 5:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4502 break;
4503 case 7:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4505 break;
4506 case 10:
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4508 break;
4509 case 14:
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4511 break;
4512 }
4513 if (INTEL_INFO(dev)->gen >= 4)
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4515
4516 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 /* XXX: just matching BIOS for now */
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521 dpll |= 3;
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525 else
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4531 udelay(150);
4532
4533 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4534 * This is an exception to the general rule that mode_set doesn't turn
4535 * things on.
4536 */
4537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4538 intel_update_lvds(crtc, clock, adjusted_mode);
4539
4540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4541 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4542
4543 I915_WRITE(DPLL(pipe), dpll);
4544
4545 /* Wait for the clocks to stabilize. */
4546 POSTING_READ(DPLL(pipe));
4547 udelay(150);
4548
4549 if (INTEL_INFO(dev)->gen >= 4) {
4550 u32 temp = 0;
4551 if (is_sdvo) {
4552 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4553 if (temp > 1)
4554 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4555 else
4556 temp = 0;
4557 }
4558 I915_WRITE(DPLL_MD(pipe), temp);
4559 } else {
4560 /* The pixel multiplier can only be updated once the
4561 * DPLL is enabled and the clocks are stable.
4562 *
4563 * So write it again.
4564 */
4565 I915_WRITE(DPLL(pipe), dpll);
4566 }
4567 }
4568
i8xx_update_pll(struct drm_crtc * crtc,struct drm_display_mode * adjusted_mode,intel_clock_t * clock,intel_clock_t * reduced_clock,int num_connectors)4569 static void i8xx_update_pll(struct drm_crtc *crtc,
4570 struct drm_display_mode *adjusted_mode,
4571 intel_clock_t *clock, intel_clock_t *reduced_clock,
4572 int num_connectors)
4573 {
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
4578 u32 dpll;
4579
4580 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4581
4582 dpll = DPLL_VGA_MODE_DIS;
4583
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4586 } else {
4587 if (clock->p1 == 2)
4588 dpll |= PLL_P1_DIVIDE_BY_TWO;
4589 else
4590 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 if (clock->p2 == 4)
4592 dpll |= PLL_P2_DIVIDE_BY_4;
4593 }
4594
4595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4596 /* XXX: just matching BIOS for now */
4597 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4598 dpll |= 3;
4599 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4600 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4601 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4602 else
4603 dpll |= PLL_REF_INPUT_DREFCLK;
4604
4605 dpll |= DPLL_VCO_ENABLE;
4606 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4607 POSTING_READ(DPLL(pipe));
4608 udelay(150);
4609
4610 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4611 * This is an exception to the general rule that mode_set doesn't turn
4612 * things on.
4613 */
4614 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4615 intel_update_lvds(crtc, clock, adjusted_mode);
4616
4617 I915_WRITE(DPLL(pipe), dpll);
4618
4619 /* Wait for the clocks to stabilize. */
4620 POSTING_READ(DPLL(pipe));
4621 udelay(150);
4622
4623 /* The pixel multiplier can only be updated once the
4624 * DPLL is enabled and the clocks are stable.
4625 *
4626 * So write it again.
4627 */
4628 I915_WRITE(DPLL(pipe), dpll);
4629 }
4630
intel_set_pipe_timings(struct intel_crtc * intel_crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)4631 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4632 struct drm_display_mode *mode,
4633 struct drm_display_mode *adjusted_mode)
4634 {
4635 struct drm_device *dev = intel_crtc->base.dev;
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 enum pipe pipe = intel_crtc->pipe;
4638 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4639 uint32_t vsyncshift;
4640
4641 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vtotal -= 1;
4644 adjusted_mode->crtc_vblank_end -= 1;
4645 vsyncshift = adjusted_mode->crtc_hsync_start
4646 - adjusted_mode->crtc_htotal / 2;
4647 } else {
4648 vsyncshift = 0;
4649 }
4650
4651 if (INTEL_INFO(dev)->gen > 3)
4652 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4653
4654 I915_WRITE(HTOTAL(cpu_transcoder),
4655 (adjusted_mode->crtc_hdisplay - 1) |
4656 ((adjusted_mode->crtc_htotal - 1) << 16));
4657 I915_WRITE(HBLANK(cpu_transcoder),
4658 (adjusted_mode->crtc_hblank_start - 1) |
4659 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4660 I915_WRITE(HSYNC(cpu_transcoder),
4661 (adjusted_mode->crtc_hsync_start - 1) |
4662 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4663
4664 I915_WRITE(VTOTAL(cpu_transcoder),
4665 (adjusted_mode->crtc_vdisplay - 1) |
4666 ((adjusted_mode->crtc_vtotal - 1) << 16));
4667 I915_WRITE(VBLANK(cpu_transcoder),
4668 (adjusted_mode->crtc_vblank_start - 1) |
4669 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4670 I915_WRITE(VSYNC(cpu_transcoder),
4671 (adjusted_mode->crtc_vsync_start - 1) |
4672 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4673
4674 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4675 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4676 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4677 * bits. */
4678 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4679 (pipe == PIPE_B || pipe == PIPE_C))
4680 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4681
4682 /* pipesrc controls the size that is scaled from, which should
4683 * always be the user's requested size.
4684 */
4685 I915_WRITE(PIPESRC(pipe),
4686 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4687 }
4688
i9xx_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * fb)4689 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4690 struct drm_display_mode *mode,
4691 struct drm_display_mode *adjusted_mode,
4692 int x, int y,
4693 struct drm_framebuffer *fb)
4694 {
4695 struct drm_device *dev = crtc->dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4698 int pipe = intel_crtc->pipe;
4699 int plane = intel_crtc->plane;
4700 int refclk, num_connectors = 0;
4701 intel_clock_t clock, reduced_clock;
4702 u32 dspcntr, pipeconf;
4703 bool ok, has_reduced_clock = false, is_sdvo = false;
4704 bool is_lvds = false, is_tv = false, is_dp = false;
4705 struct intel_encoder *encoder;
4706 const intel_limit_t *limit;
4707 int ret;
4708
4709 for_each_encoder_on_crtc(dev, crtc, encoder) {
4710 switch (encoder->type) {
4711 case INTEL_OUTPUT_LVDS:
4712 is_lvds = true;
4713 break;
4714 case INTEL_OUTPUT_SDVO:
4715 case INTEL_OUTPUT_HDMI:
4716 is_sdvo = true;
4717 if (encoder->needs_tv_clock)
4718 is_tv = true;
4719 break;
4720 case INTEL_OUTPUT_TVOUT:
4721 is_tv = true;
4722 break;
4723 case INTEL_OUTPUT_DISPLAYPORT:
4724 is_dp = true;
4725 break;
4726 }
4727
4728 num_connectors++;
4729 }
4730
4731 refclk = i9xx_get_refclk(crtc, num_connectors);
4732
4733 /*
4734 * Returns a set of divisors for the desired target clock with the given
4735 * refclk, or FALSE. The returned values represent the clock equation:
4736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4737 */
4738 limit = intel_limit(crtc, refclk);
4739 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4740 &clock);
4741 if (!ok) {
4742 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4743 return -EINVAL;
4744 }
4745
4746 /* Ensure that the cursor is valid for the new mode before changing... */
4747 intel_crtc_update_cursor(crtc, true);
4748
4749 if (is_lvds && dev_priv->lvds_downclock_avail) {
4750 /*
4751 * Ensure we match the reduced clock's P to the target clock.
4752 * If the clocks don't match, we can't switch the display clock
4753 * by using the FP0/FP1. In such case we will disable the LVDS
4754 * downclock feature.
4755 */
4756 has_reduced_clock = limit->find_pll(limit, crtc,
4757 dev_priv->lvds_downclock,
4758 refclk,
4759 &clock,
4760 &reduced_clock);
4761 }
4762
4763 if (is_sdvo && is_tv)
4764 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4765
4766 if (IS_GEN2(dev))
4767 i8xx_update_pll(crtc, adjusted_mode, &clock,
4768 has_reduced_clock ? &reduced_clock : NULL,
4769 num_connectors);
4770 else if (IS_VALLEYVIEW(dev))
4771 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4772 has_reduced_clock ? &reduced_clock : NULL,
4773 num_connectors);
4774 else
4775 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4776 has_reduced_clock ? &reduced_clock : NULL,
4777 num_connectors);
4778
4779 /* setup pipeconf */
4780 pipeconf = I915_READ(PIPECONF(pipe));
4781
4782 /* Set up the display plane register */
4783 dspcntr = DISPPLANE_GAMMA_ENABLE;
4784
4785 if (pipe == 0)
4786 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4787 else
4788 dspcntr |= DISPPLANE_SEL_PIPE_B;
4789
4790 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792 * core speed.
4793 *
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4796 */
4797 if (mode->clock >
4798 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799 pipeconf |= PIPECONF_DOUBLE_WIDE;
4800 else
4801 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4802 }
4803
4804 /* default to 8bpc */
4805 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4806 if (is_dp) {
4807 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4808 pipeconf |= PIPECONF_BPP_6 |
4809 PIPECONF_DITHER_EN |
4810 PIPECONF_DITHER_TYPE_SP;
4811 }
4812 }
4813
4814 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4815 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4816 pipeconf |= PIPECONF_BPP_6 |
4817 PIPECONF_ENABLE |
4818 I965_PIPECONF_ACTIVE;
4819 }
4820 }
4821
4822 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4823 drm_mode_debug_printmodeline(mode);
4824
4825 if (HAS_PIPE_CXSR(dev)) {
4826 if (intel_crtc->lowfreq_avail) {
4827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4829 } else {
4830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4831 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4832 }
4833 }
4834
4835 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4836 if (!IS_GEN2(dev) &&
4837 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4838 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4839 else
4840 pipeconf |= PIPECONF_PROGRESSIVE;
4841
4842 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4843
4844 /* pipesrc and dspsize control the size that is scaled from,
4845 * which should always be the user's requested size.
4846 */
4847 I915_WRITE(DSPSIZE(plane),
4848 ((mode->vdisplay - 1) << 16) |
4849 (mode->hdisplay - 1));
4850 I915_WRITE(DSPPOS(plane), 0);
4851
4852 I915_WRITE(PIPECONF(pipe), pipeconf);
4853 POSTING_READ(PIPECONF(pipe));
4854 intel_enable_pipe(dev_priv, pipe, false);
4855
4856 intel_wait_for_vblank(dev, pipe);
4857
4858 I915_WRITE(DSPCNTR(plane), dspcntr);
4859 POSTING_READ(DSPCNTR(plane));
4860
4861 ret = intel_pipe_set_base(crtc, x, y, fb);
4862
4863 intel_update_watermarks(dev);
4864
4865 return ret;
4866 }
4867
ironlake_init_pch_refclk(struct drm_device * dev)4868 static void ironlake_init_pch_refclk(struct drm_device *dev)
4869 {
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct drm_mode_config *mode_config = &dev->mode_config;
4872 struct intel_encoder *encoder;
4873 u32 temp;
4874 bool has_lvds = false;
4875 bool has_cpu_edp = false;
4876 bool has_pch_edp = false;
4877 bool has_panel = false;
4878 bool has_ck505 = false;
4879 bool can_ssc = false;
4880
4881 /* We need to take the global config into account */
4882 list_for_each_entry(encoder, &mode_config->encoder_list,
4883 base.head) {
4884 switch (encoder->type) {
4885 case INTEL_OUTPUT_LVDS:
4886 has_panel = true;
4887 has_lvds = true;
4888 break;
4889 case INTEL_OUTPUT_EDP:
4890 has_panel = true;
4891 if (intel_encoder_is_pch_edp(&encoder->base))
4892 has_pch_edp = true;
4893 else
4894 has_cpu_edp = true;
4895 break;
4896 }
4897 }
4898
4899 if (HAS_PCH_IBX(dev)) {
4900 has_ck505 = dev_priv->display_clock_mode;
4901 can_ssc = has_ck505;
4902 } else {
4903 has_ck505 = false;
4904 can_ssc = true;
4905 }
4906
4907 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4908 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4909 has_ck505);
4910
4911 /* Ironlake: try to setup display ref clock before DPLL
4912 * enabling. This is only under driver's control after
4913 * PCH B stepping, previous chipset stepping should be
4914 * ignoring this setting.
4915 */
4916 temp = I915_READ(PCH_DREF_CONTROL);
4917 /* Always enable nonspread source */
4918 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4919
4920 if (has_ck505)
4921 temp |= DREF_NONSPREAD_CK505_ENABLE;
4922 else
4923 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4924
4925 if (has_panel) {
4926 temp &= ~DREF_SSC_SOURCE_MASK;
4927 temp |= DREF_SSC_SOURCE_ENABLE;
4928
4929 /* SSC must be turned on before enabling the CPU output */
4930 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4931 DRM_DEBUG_KMS("Using SSC on panel\n");
4932 temp |= DREF_SSC1_ENABLE;
4933 } else
4934 temp &= ~DREF_SSC1_ENABLE;
4935
4936 /* Get SSC going before enabling the outputs */
4937 I915_WRITE(PCH_DREF_CONTROL, temp);
4938 POSTING_READ(PCH_DREF_CONTROL);
4939 udelay(200);
4940
4941 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4942
4943 /* Enable CPU source on CPU attached eDP */
4944 if (has_cpu_edp) {
4945 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4946 DRM_DEBUG_KMS("Using SSC on eDP\n");
4947 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4948 }
4949 else
4950 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4951 } else
4952 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4953
4954 I915_WRITE(PCH_DREF_CONTROL, temp);
4955 POSTING_READ(PCH_DREF_CONTROL);
4956 udelay(200);
4957 } else {
4958 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4959
4960 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4961
4962 /* Turn off CPU output */
4963 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4964
4965 I915_WRITE(PCH_DREF_CONTROL, temp);
4966 POSTING_READ(PCH_DREF_CONTROL);
4967 udelay(200);
4968
4969 /* Turn off the SSC source */
4970 temp &= ~DREF_SSC_SOURCE_MASK;
4971 temp |= DREF_SSC_SOURCE_DISABLE;
4972
4973 /* Turn off SSC1 */
4974 temp &= ~ DREF_SSC1_ENABLE;
4975
4976 I915_WRITE(PCH_DREF_CONTROL, temp);
4977 POSTING_READ(PCH_DREF_CONTROL);
4978 udelay(200);
4979 }
4980 }
4981
4982 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
lpt_init_pch_refclk(struct drm_device * dev)4983 static void lpt_init_pch_refclk(struct drm_device *dev)
4984 {
4985 struct drm_i915_private *dev_priv = dev->dev_private;
4986 struct drm_mode_config *mode_config = &dev->mode_config;
4987 struct intel_encoder *encoder;
4988 bool has_vga = false;
4989 bool is_sdv = false;
4990 u32 tmp;
4991
4992 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4993 switch (encoder->type) {
4994 case INTEL_OUTPUT_ANALOG:
4995 has_vga = true;
4996 break;
4997 }
4998 }
4999
5000 if (!has_vga)
5001 return;
5002
5003 /* XXX: Rip out SDV support once Haswell ships for real. */
5004 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5005 is_sdv = true;
5006
5007 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5008 tmp &= ~SBI_SSCCTL_DISABLE;
5009 tmp |= SBI_SSCCTL_PATHALT;
5010 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5011
5012 udelay(24);
5013
5014 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5015 tmp &= ~SBI_SSCCTL_PATHALT;
5016 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5017
5018 if (!is_sdv) {
5019 tmp = I915_READ(SOUTH_CHICKEN2);
5020 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5021 I915_WRITE(SOUTH_CHICKEN2, tmp);
5022
5023 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5024 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5025 DRM_ERROR("FDI mPHY reset assert timeout\n");
5026
5027 tmp = I915_READ(SOUTH_CHICKEN2);
5028 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5029 I915_WRITE(SOUTH_CHICKEN2, tmp);
5030
5031 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5032 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5033 100))
5034 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5035 }
5036
5037 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5038 tmp &= ~(0xFF << 24);
5039 tmp |= (0x12 << 24);
5040 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5041
5042 if (!is_sdv) {
5043 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
5044 tmp &= ~(0x3 << 6);
5045 tmp |= (1 << 6) | (1 << 0);
5046 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
5047 }
5048
5049 if (is_sdv) {
5050 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5051 tmp |= 0x7FFF;
5052 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5053 }
5054
5055 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5056 tmp |= (1 << 11);
5057 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5058
5059 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5060 tmp |= (1 << 11);
5061 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5062
5063 if (is_sdv) {
5064 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5065 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5066 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5067
5068 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5069 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5070 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5071
5072 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5073 tmp |= (0x3F << 8);
5074 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5075
5076 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5077 tmp |= (0x3F << 8);
5078 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5079 }
5080
5081 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5082 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5083 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5084
5085 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5086 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5087 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5088
5089 if (!is_sdv) {
5090 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5091 tmp &= ~(7 << 13);
5092 tmp |= (5 << 13);
5093 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5094
5095 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5096 tmp &= ~(7 << 13);
5097 tmp |= (5 << 13);
5098 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5099 }
5100
5101 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5102 tmp &= ~0xFF;
5103 tmp |= 0x1C;
5104 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5105
5106 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5107 tmp &= ~0xFF;
5108 tmp |= 0x1C;
5109 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5110
5111 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5112 tmp &= ~(0xFF << 16);
5113 tmp |= (0x1C << 16);
5114 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5115
5116 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5117 tmp &= ~(0xFF << 16);
5118 tmp |= (0x1C << 16);
5119 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5120
5121 if (!is_sdv) {
5122 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5123 tmp |= (1 << 27);
5124 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5125
5126 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5127 tmp |= (1 << 27);
5128 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5129
5130 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5131 tmp &= ~(0xF << 28);
5132 tmp |= (4 << 28);
5133 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5134
5135 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5136 tmp &= ~(0xF << 28);
5137 tmp |= (4 << 28);
5138 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5139 }
5140
5141 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5142 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5143 tmp |= SBI_DBUFF0_ENABLE;
5144 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5145 }
5146
5147 /*
5148 * Initialize reference clocks when the driver loads
5149 */
intel_init_pch_refclk(struct drm_device * dev)5150 void intel_init_pch_refclk(struct drm_device *dev)
5151 {
5152 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5153 ironlake_init_pch_refclk(dev);
5154 else if (HAS_PCH_LPT(dev))
5155 lpt_init_pch_refclk(dev);
5156 }
5157
ironlake_get_refclk(struct drm_crtc * crtc)5158 static int ironlake_get_refclk(struct drm_crtc *crtc)
5159 {
5160 struct drm_device *dev = crtc->dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 struct intel_encoder *encoder;
5163 struct intel_encoder *edp_encoder = NULL;
5164 int num_connectors = 0;
5165 bool is_lvds = false;
5166
5167 for_each_encoder_on_crtc(dev, crtc, encoder) {
5168 switch (encoder->type) {
5169 case INTEL_OUTPUT_LVDS:
5170 is_lvds = true;
5171 break;
5172 case INTEL_OUTPUT_EDP:
5173 edp_encoder = encoder;
5174 break;
5175 }
5176 num_connectors++;
5177 }
5178
5179 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5180 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5181 dev_priv->lvds_ssc_freq);
5182 return dev_priv->lvds_ssc_freq * 1000;
5183 }
5184
5185 return 120000;
5186 }
5187
ironlake_set_pipeconf(struct drm_crtc * crtc,struct drm_display_mode * adjusted_mode,bool dither)5188 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5189 struct drm_display_mode *adjusted_mode,
5190 bool dither)
5191 {
5192 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5194 int pipe = intel_crtc->pipe;
5195 uint32_t val;
5196
5197 val = I915_READ(PIPECONF(pipe));
5198
5199 val &= ~PIPE_BPC_MASK;
5200 switch (intel_crtc->bpp) {
5201 case 18:
5202 val |= PIPE_6BPC;
5203 break;
5204 case 24:
5205 val |= PIPE_8BPC;
5206 break;
5207 case 30:
5208 val |= PIPE_10BPC;
5209 break;
5210 case 36:
5211 val |= PIPE_12BPC;
5212 break;
5213 default:
5214 /* Case prevented by intel_choose_pipe_bpp_dither. */
5215 BUG();
5216 }
5217
5218 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5219 if (dither)
5220 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5221
5222 val &= ~PIPECONF_INTERLACE_MASK;
5223 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5224 val |= PIPECONF_INTERLACED_ILK;
5225 else
5226 val |= PIPECONF_PROGRESSIVE;
5227
5228 I915_WRITE(PIPECONF(pipe), val);
5229 POSTING_READ(PIPECONF(pipe));
5230 }
5231
haswell_set_pipeconf(struct drm_crtc * crtc,struct drm_display_mode * adjusted_mode,bool dither)5232 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5233 struct drm_display_mode *adjusted_mode,
5234 bool dither)
5235 {
5236 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5239 uint32_t val;
5240
5241 val = I915_READ(PIPECONF(cpu_transcoder));
5242
5243 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5244 if (dither)
5245 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5246
5247 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5248 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5249 val |= PIPECONF_INTERLACED_ILK;
5250 else
5251 val |= PIPECONF_PROGRESSIVE;
5252
5253 I915_WRITE(PIPECONF(cpu_transcoder), val);
5254 POSTING_READ(PIPECONF(cpu_transcoder));
5255 }
5256
ironlake_compute_clocks(struct drm_crtc * crtc,struct drm_display_mode * adjusted_mode,intel_clock_t * clock,bool * has_reduced_clock,intel_clock_t * reduced_clock)5257 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5258 struct drm_display_mode *adjusted_mode,
5259 intel_clock_t *clock,
5260 bool *has_reduced_clock,
5261 intel_clock_t *reduced_clock)
5262 {
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 struct intel_encoder *intel_encoder;
5266 int refclk;
5267 const intel_limit_t *limit;
5268 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5269
5270 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5271 switch (intel_encoder->type) {
5272 case INTEL_OUTPUT_LVDS:
5273 is_lvds = true;
5274 break;
5275 case INTEL_OUTPUT_SDVO:
5276 case INTEL_OUTPUT_HDMI:
5277 is_sdvo = true;
5278 if (intel_encoder->needs_tv_clock)
5279 is_tv = true;
5280 break;
5281 case INTEL_OUTPUT_TVOUT:
5282 is_tv = true;
5283 break;
5284 }
5285 }
5286
5287 refclk = ironlake_get_refclk(crtc);
5288
5289 /*
5290 * Returns a set of divisors for the desired target clock with the given
5291 * refclk, or FALSE. The returned values represent the clock equation:
5292 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5293 */
5294 limit = intel_limit(crtc, refclk);
5295 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5296 clock);
5297 if (!ret)
5298 return false;
5299
5300 if (is_lvds && dev_priv->lvds_downclock_avail) {
5301 /*
5302 * Ensure we match the reduced clock's P to the target clock.
5303 * If the clocks don't match, we can't switch the display clock
5304 * by using the FP0/FP1. In such case we will disable the LVDS
5305 * downclock feature.
5306 */
5307 *has_reduced_clock = limit->find_pll(limit, crtc,
5308 dev_priv->lvds_downclock,
5309 refclk,
5310 clock,
5311 reduced_clock);
5312 }
5313
5314 if (is_sdvo && is_tv)
5315 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5316
5317 return true;
5318 }
5319
cpt_enable_fdi_bc_bifurcation(struct drm_device * dev)5320 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5321 {
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 uint32_t temp;
5324
5325 temp = I915_READ(SOUTH_CHICKEN1);
5326 if (temp & FDI_BC_BIFURCATION_SELECT)
5327 return;
5328
5329 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5330 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5331
5332 temp |= FDI_BC_BIFURCATION_SELECT;
5333 DRM_DEBUG_KMS("enabling fdi C rx\n");
5334 I915_WRITE(SOUTH_CHICKEN1, temp);
5335 POSTING_READ(SOUTH_CHICKEN1);
5336 }
5337
ironlake_check_fdi_lanes(struct intel_crtc * intel_crtc)5338 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5339 {
5340 struct drm_device *dev = intel_crtc->base.dev;
5341 struct drm_i915_private *dev_priv = dev->dev_private;
5342 struct intel_crtc *pipe_B_crtc =
5343 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5344
5345 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5346 intel_crtc->pipe, intel_crtc->fdi_lanes);
5347 if (intel_crtc->fdi_lanes > 4) {
5348 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5349 intel_crtc->pipe, intel_crtc->fdi_lanes);
5350 /* Clamp lanes to avoid programming the hw with bogus values. */
5351 intel_crtc->fdi_lanes = 4;
5352
5353 return false;
5354 }
5355
5356 if (dev_priv->num_pipe == 2)
5357 return true;
5358
5359 switch (intel_crtc->pipe) {
5360 case PIPE_A:
5361 return true;
5362 case PIPE_B:
5363 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5364 intel_crtc->fdi_lanes > 2) {
5365 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5366 intel_crtc->pipe, intel_crtc->fdi_lanes);
5367 /* Clamp lanes to avoid programming the hw with bogus values. */
5368 intel_crtc->fdi_lanes = 2;
5369
5370 return false;
5371 }
5372
5373 if (intel_crtc->fdi_lanes > 2)
5374 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5375 else
5376 cpt_enable_fdi_bc_bifurcation(dev);
5377
5378 return true;
5379 case PIPE_C:
5380 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5381 if (intel_crtc->fdi_lanes > 2) {
5382 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5383 intel_crtc->pipe, intel_crtc->fdi_lanes);
5384 /* Clamp lanes to avoid programming the hw with bogus values. */
5385 intel_crtc->fdi_lanes = 2;
5386
5387 return false;
5388 }
5389 } else {
5390 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5391 return false;
5392 }
5393
5394 cpt_enable_fdi_bc_bifurcation(dev);
5395
5396 return true;
5397 default:
5398 BUG();
5399 }
5400 }
5401
ironlake_get_lanes_required(int target_clock,int link_bw,int bpp)5402 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5403 {
5404 /*
5405 * Account for spread spectrum to avoid
5406 * oversubscribing the link. Max center spread
5407 * is 2.5%; use 5% for safety's sake.
5408 */
5409 u32 bps = target_clock * bpp * 21 / 20;
5410 return bps / (link_bw * 8) + 1;
5411 }
5412
ironlake_set_m_n(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)5413 static void ironlake_set_m_n(struct drm_crtc *crtc,
5414 struct drm_display_mode *mode,
5415 struct drm_display_mode *adjusted_mode)
5416 {
5417 struct drm_device *dev = crtc->dev;
5418 struct drm_i915_private *dev_priv = dev->dev_private;
5419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5420 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5421 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5422 struct fdi_m_n m_n = {0};
5423 int target_clock, pixel_multiplier, lane, link_bw;
5424 bool is_dp = false, is_cpu_edp = false;
5425
5426 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5427 switch (intel_encoder->type) {
5428 case INTEL_OUTPUT_DISPLAYPORT:
5429 is_dp = true;
5430 break;
5431 case INTEL_OUTPUT_EDP:
5432 is_dp = true;
5433 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5434 is_cpu_edp = true;
5435 edp_encoder = intel_encoder;
5436 break;
5437 }
5438 }
5439
5440 /* FDI link */
5441 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5442 lane = 0;
5443 /* CPU eDP doesn't require FDI link, so just set DP M/N
5444 according to current link config */
5445 if (is_cpu_edp) {
5446 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5447 } else {
5448 /* FDI is a binary signal running at ~2.7GHz, encoding
5449 * each output octet as 10 bits. The actual frequency
5450 * is stored as a divider into a 100MHz clock, and the
5451 * mode pixel clock is stored in units of 1KHz.
5452 * Hence the bw of each lane in terms of the mode signal
5453 * is:
5454 */
5455 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5456 }
5457
5458 /* [e]DP over FDI requires target mode clock instead of link clock. */
5459 if (edp_encoder)
5460 target_clock = intel_edp_target_clock(edp_encoder, mode);
5461 else if (is_dp)
5462 target_clock = mode->clock;
5463 else
5464 target_clock = adjusted_mode->clock;
5465
5466 if (!lane)
5467 lane = ironlake_get_lanes_required(target_clock, link_bw,
5468 intel_crtc->bpp);
5469
5470 intel_crtc->fdi_lanes = lane;
5471
5472 if (pixel_multiplier > 1)
5473 link_bw *= pixel_multiplier;
5474 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5475 &m_n);
5476
5477 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5478 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5479 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5480 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5481 }
5482
ironlake_compute_dpll(struct intel_crtc * intel_crtc,struct drm_display_mode * adjusted_mode,intel_clock_t * clock,u32 fp)5483 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5484 struct drm_display_mode *adjusted_mode,
5485 intel_clock_t *clock, u32 fp)
5486 {
5487 struct drm_crtc *crtc = &intel_crtc->base;
5488 struct drm_device *dev = crtc->dev;
5489 struct drm_i915_private *dev_priv = dev->dev_private;
5490 struct intel_encoder *intel_encoder;
5491 uint32_t dpll;
5492 int factor, pixel_multiplier, num_connectors = 0;
5493 bool is_lvds = false, is_sdvo = false, is_tv = false;
5494 bool is_dp = false, is_cpu_edp = false;
5495
5496 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5497 switch (intel_encoder->type) {
5498 case INTEL_OUTPUT_LVDS:
5499 is_lvds = true;
5500 break;
5501 case INTEL_OUTPUT_SDVO:
5502 case INTEL_OUTPUT_HDMI:
5503 is_sdvo = true;
5504 if (intel_encoder->needs_tv_clock)
5505 is_tv = true;
5506 break;
5507 case INTEL_OUTPUT_TVOUT:
5508 is_tv = true;
5509 break;
5510 case INTEL_OUTPUT_DISPLAYPORT:
5511 is_dp = true;
5512 break;
5513 case INTEL_OUTPUT_EDP:
5514 is_dp = true;
5515 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5516 is_cpu_edp = true;
5517 break;
5518 }
5519
5520 num_connectors++;
5521 }
5522
5523 /* Enable autotuning of the PLL clock (if permissible) */
5524 factor = 21;
5525 if (is_lvds) {
5526 if ((intel_panel_use_ssc(dev_priv) &&
5527 dev_priv->lvds_ssc_freq == 100) ||
5528 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5529 factor = 25;
5530 } else if (is_sdvo && is_tv)
5531 factor = 20;
5532
5533 if (clock->m < factor * clock->n)
5534 fp |= FP_CB_TUNE;
5535
5536 dpll = 0;
5537
5538 if (is_lvds)
5539 dpll |= DPLLB_MODE_LVDS;
5540 else
5541 dpll |= DPLLB_MODE_DAC_SERIAL;
5542 if (is_sdvo) {
5543 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5544 if (pixel_multiplier > 1) {
5545 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5546 }
5547 dpll |= DPLL_DVO_HIGH_SPEED;
5548 }
5549 if (is_dp && !is_cpu_edp)
5550 dpll |= DPLL_DVO_HIGH_SPEED;
5551
5552 /* compute bitmask from p1 value */
5553 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5554 /* also FPA1 */
5555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5556
5557 switch (clock->p2) {
5558 case 5:
5559 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5560 break;
5561 case 7:
5562 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5563 break;
5564 case 10:
5565 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5566 break;
5567 case 14:
5568 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5569 break;
5570 }
5571
5572 if (is_sdvo && is_tv)
5573 dpll |= PLL_REF_INPUT_TVCLKINBC;
5574 else if (is_tv)
5575 /* XXX: just matching BIOS for now */
5576 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5577 dpll |= 3;
5578 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5580 else
5581 dpll |= PLL_REF_INPUT_DREFCLK;
5582
5583 return dpll;
5584 }
5585
ironlake_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * fb)5586 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5587 struct drm_display_mode *mode,
5588 struct drm_display_mode *adjusted_mode,
5589 int x, int y,
5590 struct drm_framebuffer *fb)
5591 {
5592 struct drm_device *dev = crtc->dev;
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5595 int pipe = intel_crtc->pipe;
5596 int plane = intel_crtc->plane;
5597 int num_connectors = 0;
5598 intel_clock_t clock, reduced_clock;
5599 u32 dpll, fp = 0, fp2 = 0;
5600 bool ok, has_reduced_clock = false;
5601 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5602 struct intel_encoder *encoder;
5603 u32 temp;
5604 int ret;
5605 bool dither, fdi_config_ok;
5606
5607 for_each_encoder_on_crtc(dev, crtc, encoder) {
5608 switch (encoder->type) {
5609 case INTEL_OUTPUT_LVDS:
5610 is_lvds = true;
5611 break;
5612 case INTEL_OUTPUT_DISPLAYPORT:
5613 is_dp = true;
5614 break;
5615 case INTEL_OUTPUT_EDP:
5616 is_dp = true;
5617 if (!intel_encoder_is_pch_edp(&encoder->base))
5618 is_cpu_edp = true;
5619 break;
5620 }
5621
5622 num_connectors++;
5623 }
5624
5625 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5626 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5627
5628 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5629 &has_reduced_clock, &reduced_clock);
5630 if (!ok) {
5631 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5632 return -EINVAL;
5633 }
5634
5635 /* Ensure that the cursor is valid for the new mode before changing... */
5636 intel_crtc_update_cursor(crtc, true);
5637
5638 /* determine panel color depth */
5639 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5640 adjusted_mode);
5641 if (is_lvds && dev_priv->lvds_dither)
5642 dither = true;
5643
5644 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5645 if (has_reduced_clock)
5646 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5647 reduced_clock.m2;
5648
5649 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5650
5651 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5652 drm_mode_debug_printmodeline(mode);
5653
5654 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5655 if (!is_cpu_edp) {
5656 struct intel_pch_pll *pll;
5657
5658 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5659 if (pll == NULL) {
5660 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5661 pipe);
5662 return -EINVAL;
5663 }
5664 } else
5665 intel_put_pch_pll(intel_crtc);
5666
5667 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5668 * This is an exception to the general rule that mode_set doesn't turn
5669 * things on.
5670 */
5671 if (is_lvds) {
5672 temp = I915_READ(PCH_LVDS);
5673 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5674 if (HAS_PCH_CPT(dev)) {
5675 temp &= ~PORT_TRANS_SEL_MASK;
5676 temp |= PORT_TRANS_SEL_CPT(pipe);
5677 } else {
5678 if (pipe == 1)
5679 temp |= LVDS_PIPEB_SELECT;
5680 else
5681 temp &= ~LVDS_PIPEB_SELECT;
5682 }
5683
5684 /* set the corresponsding LVDS_BORDER bit */
5685 temp |= dev_priv->lvds_border_bits;
5686 /* Set the B0-B3 data pairs corresponding to whether we're going to
5687 * set the DPLLs for dual-channel mode or not.
5688 */
5689 if (clock.p2 == 7)
5690 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5691 else
5692 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5693
5694 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5695 * appropriately here, but we need to look more thoroughly into how
5696 * panels behave in the two modes.
5697 */
5698 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5699 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5700 temp |= LVDS_HSYNC_POLARITY;
5701 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5702 temp |= LVDS_VSYNC_POLARITY;
5703 I915_WRITE(PCH_LVDS, temp);
5704 }
5705
5706 if (is_dp && !is_cpu_edp) {
5707 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5708 } else {
5709 /* For non-DP output, clear any trans DP clock recovery setting.*/
5710 I915_WRITE(TRANSDATA_M1(pipe), 0);
5711 I915_WRITE(TRANSDATA_N1(pipe), 0);
5712 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5713 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5714 }
5715
5716 if (intel_crtc->pch_pll) {
5717 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5718
5719 /* Wait for the clocks to stabilize. */
5720 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5721 udelay(150);
5722
5723 /* The pixel multiplier can only be updated once the
5724 * DPLL is enabled and the clocks are stable.
5725 *
5726 * So write it again.
5727 */
5728 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5729 }
5730
5731 intel_crtc->lowfreq_avail = false;
5732 if (intel_crtc->pch_pll) {
5733 if (is_lvds && has_reduced_clock && i915_powersave) {
5734 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5735 intel_crtc->lowfreq_avail = true;
5736 } else {
5737 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5738 }
5739 }
5740
5741 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5742
5743 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5744 * ironlake_check_fdi_lanes. */
5745 ironlake_set_m_n(crtc, mode, adjusted_mode);
5746
5747 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5748
5749 if (is_cpu_edp)
5750 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5751
5752 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5753
5754 intel_wait_for_vblank(dev, pipe);
5755
5756 /* Set up the display plane register */
5757 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5758 POSTING_READ(DSPCNTR(plane));
5759
5760 ret = intel_pipe_set_base(crtc, x, y, fb);
5761
5762 intel_update_watermarks(dev);
5763
5764 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5765
5766 return fdi_config_ok ? ret : -EINVAL;
5767 }
5768
haswell_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * fb)5769 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5770 struct drm_display_mode *mode,
5771 struct drm_display_mode *adjusted_mode,
5772 int x, int y,
5773 struct drm_framebuffer *fb)
5774 {
5775 struct drm_device *dev = crtc->dev;
5776 struct drm_i915_private *dev_priv = dev->dev_private;
5777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5778 int pipe = intel_crtc->pipe;
5779 int plane = intel_crtc->plane;
5780 int num_connectors = 0;
5781 intel_clock_t clock, reduced_clock;
5782 u32 dpll = 0, fp = 0, fp2 = 0;
5783 bool ok, has_reduced_clock = false;
5784 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5785 struct intel_encoder *encoder;
5786 u32 temp;
5787 int ret;
5788 bool dither;
5789
5790 for_each_encoder_on_crtc(dev, crtc, encoder) {
5791 switch (encoder->type) {
5792 case INTEL_OUTPUT_LVDS:
5793 is_lvds = true;
5794 break;
5795 case INTEL_OUTPUT_DISPLAYPORT:
5796 is_dp = true;
5797 break;
5798 case INTEL_OUTPUT_EDP:
5799 is_dp = true;
5800 if (!intel_encoder_is_pch_edp(&encoder->base))
5801 is_cpu_edp = true;
5802 break;
5803 }
5804
5805 num_connectors++;
5806 }
5807
5808 if (is_cpu_edp)
5809 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5810 else
5811 intel_crtc->cpu_transcoder = pipe;
5812
5813 /* We are not sure yet this won't happen. */
5814 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5815 INTEL_PCH_TYPE(dev));
5816
5817 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5818 num_connectors, pipe_name(pipe));
5819
5820 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5821 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5822
5823 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5824
5825 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5826 return -EINVAL;
5827
5828 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5829 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5830 &has_reduced_clock,
5831 &reduced_clock);
5832 if (!ok) {
5833 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5834 return -EINVAL;
5835 }
5836 }
5837
5838 /* Ensure that the cursor is valid for the new mode before changing... */
5839 intel_crtc_update_cursor(crtc, true);
5840
5841 /* determine panel color depth */
5842 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5843 adjusted_mode);
5844 if (is_lvds && dev_priv->lvds_dither)
5845 dither = true;
5846
5847 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5848 drm_mode_debug_printmodeline(mode);
5849
5850 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5851 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5852 if (has_reduced_clock)
5853 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5854 reduced_clock.m2;
5855
5856 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5857 fp);
5858
5859 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5860 * own on pre-Haswell/LPT generation */
5861 if (!is_cpu_edp) {
5862 struct intel_pch_pll *pll;
5863
5864 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5865 if (pll == NULL) {
5866 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5867 pipe);
5868 return -EINVAL;
5869 }
5870 } else
5871 intel_put_pch_pll(intel_crtc);
5872
5873 /* The LVDS pin pair needs to be on before the DPLLs are
5874 * enabled. This is an exception to the general rule that
5875 * mode_set doesn't turn things on.
5876 */
5877 if (is_lvds) {
5878 temp = I915_READ(PCH_LVDS);
5879 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5880 if (HAS_PCH_CPT(dev)) {
5881 temp &= ~PORT_TRANS_SEL_MASK;
5882 temp |= PORT_TRANS_SEL_CPT(pipe);
5883 } else {
5884 if (pipe == 1)
5885 temp |= LVDS_PIPEB_SELECT;
5886 else
5887 temp &= ~LVDS_PIPEB_SELECT;
5888 }
5889
5890 /* set the corresponsding LVDS_BORDER bit */
5891 temp |= dev_priv->lvds_border_bits;
5892 /* Set the B0-B3 data pairs corresponding to whether
5893 * we're going to set the DPLLs for dual-channel mode or
5894 * not.
5895 */
5896 if (clock.p2 == 7)
5897 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5898 else
5899 temp &= ~(LVDS_B0B3_POWER_UP |
5900 LVDS_CLKB_POWER_UP);
5901
5902 /* It would be nice to set 24 vs 18-bit mode
5903 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5904 * look more thoroughly into how panels behave in the
5905 * two modes.
5906 */
5907 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5908 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5909 temp |= LVDS_HSYNC_POLARITY;
5910 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5911 temp |= LVDS_VSYNC_POLARITY;
5912 I915_WRITE(PCH_LVDS, temp);
5913 }
5914 }
5915
5916 if (is_dp && !is_cpu_edp) {
5917 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5918 } else {
5919 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5920 /* For non-DP output, clear any trans DP clock recovery
5921 * setting.*/
5922 I915_WRITE(TRANSDATA_M1(pipe), 0);
5923 I915_WRITE(TRANSDATA_N1(pipe), 0);
5924 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5925 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5926 }
5927 }
5928
5929 intel_crtc->lowfreq_avail = false;
5930 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5931 if (intel_crtc->pch_pll) {
5932 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5933
5934 /* Wait for the clocks to stabilize. */
5935 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5936 udelay(150);
5937
5938 /* The pixel multiplier can only be updated once the
5939 * DPLL is enabled and the clocks are stable.
5940 *
5941 * So write it again.
5942 */
5943 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5944 }
5945
5946 if (intel_crtc->pch_pll) {
5947 if (is_lvds && has_reduced_clock && i915_powersave) {
5948 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5949 intel_crtc->lowfreq_avail = true;
5950 } else {
5951 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5952 }
5953 }
5954 }
5955
5956 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5957
5958 if (!is_dp || is_cpu_edp)
5959 ironlake_set_m_n(crtc, mode, adjusted_mode);
5960
5961 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5962 if (is_cpu_edp)
5963 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5964
5965 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5966
5967 /* Set up the display plane register */
5968 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5969 POSTING_READ(DSPCNTR(plane));
5970
5971 ret = intel_pipe_set_base(crtc, x, y, fb);
5972
5973 intel_update_watermarks(dev);
5974
5975 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5976
5977 return ret;
5978 }
5979
intel_crtc_mode_set(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode,int x,int y,struct drm_framebuffer * fb)5980 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5981 struct drm_display_mode *mode,
5982 struct drm_display_mode *adjusted_mode,
5983 int x, int y,
5984 struct drm_framebuffer *fb)
5985 {
5986 struct drm_device *dev = crtc->dev;
5987 struct drm_i915_private *dev_priv = dev->dev_private;
5988 struct drm_encoder_helper_funcs *encoder_funcs;
5989 struct intel_encoder *encoder;
5990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991 int pipe = intel_crtc->pipe;
5992 int ret;
5993
5994 drm_vblank_pre_modeset(dev, pipe);
5995
5996 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5997 x, y, fb);
5998 drm_vblank_post_modeset(dev, pipe);
5999
6000 if (ret != 0)
6001 return ret;
6002
6003 for_each_encoder_on_crtc(dev, crtc, encoder) {
6004 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6005 encoder->base.base.id,
6006 drm_get_encoder_name(&encoder->base),
6007 mode->base.id, mode->name);
6008 encoder_funcs = encoder->base.helper_private;
6009 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6010 }
6011
6012 return 0;
6013 }
6014
intel_eld_uptodate(struct drm_connector * connector,int reg_eldv,uint32_t bits_eldv,int reg_elda,uint32_t bits_elda,int reg_edid)6015 static bool intel_eld_uptodate(struct drm_connector *connector,
6016 int reg_eldv, uint32_t bits_eldv,
6017 int reg_elda, uint32_t bits_elda,
6018 int reg_edid)
6019 {
6020 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6021 uint8_t *eld = connector->eld;
6022 uint32_t i;
6023
6024 i = I915_READ(reg_eldv);
6025 i &= bits_eldv;
6026
6027 if (!eld[0])
6028 return !i;
6029
6030 if (!i)
6031 return false;
6032
6033 i = I915_READ(reg_elda);
6034 i &= ~bits_elda;
6035 I915_WRITE(reg_elda, i);
6036
6037 for (i = 0; i < eld[2]; i++)
6038 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6039 return false;
6040
6041 return true;
6042 }
6043
g4x_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6044 static void g4x_write_eld(struct drm_connector *connector,
6045 struct drm_crtc *crtc)
6046 {
6047 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6048 uint8_t *eld = connector->eld;
6049 uint32_t eldv;
6050 uint32_t len;
6051 uint32_t i;
6052
6053 i = I915_READ(G4X_AUD_VID_DID);
6054
6055 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6056 eldv = G4X_ELDV_DEVCL_DEVBLC;
6057 else
6058 eldv = G4X_ELDV_DEVCTG;
6059
6060 if (intel_eld_uptodate(connector,
6061 G4X_AUD_CNTL_ST, eldv,
6062 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6063 G4X_HDMIW_HDMIEDID))
6064 return;
6065
6066 i = I915_READ(G4X_AUD_CNTL_ST);
6067 i &= ~(eldv | G4X_ELD_ADDR);
6068 len = (i >> 9) & 0x1f; /* ELD buffer size */
6069 I915_WRITE(G4X_AUD_CNTL_ST, i);
6070
6071 if (!eld[0])
6072 return;
6073
6074 len = min_t(uint8_t, eld[2], len);
6075 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6076 for (i = 0; i < len; i++)
6077 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6078
6079 i = I915_READ(G4X_AUD_CNTL_ST);
6080 i |= eldv;
6081 I915_WRITE(G4X_AUD_CNTL_ST, i);
6082 }
6083
haswell_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6084 static void haswell_write_eld(struct drm_connector *connector,
6085 struct drm_crtc *crtc)
6086 {
6087 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6088 uint8_t *eld = connector->eld;
6089 struct drm_device *dev = crtc->dev;
6090 uint32_t eldv;
6091 uint32_t i;
6092 int len;
6093 int pipe = to_intel_crtc(crtc)->pipe;
6094 int tmp;
6095
6096 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6097 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6098 int aud_config = HSW_AUD_CFG(pipe);
6099 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6100
6101
6102 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6103
6104 /* Audio output enable */
6105 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6106 tmp = I915_READ(aud_cntrl_st2);
6107 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6108 I915_WRITE(aud_cntrl_st2, tmp);
6109
6110 /* Wait for 1 vertical blank */
6111 intel_wait_for_vblank(dev, pipe);
6112
6113 /* Set ELD valid state */
6114 tmp = I915_READ(aud_cntrl_st2);
6115 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6116 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6117 I915_WRITE(aud_cntrl_st2, tmp);
6118 tmp = I915_READ(aud_cntrl_st2);
6119 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6120
6121 /* Enable HDMI mode */
6122 tmp = I915_READ(aud_config);
6123 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6124 /* clear N_programing_enable and N_value_index */
6125 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6126 I915_WRITE(aud_config, tmp);
6127
6128 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6129
6130 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6131
6132 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6133 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6134 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6135 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6136 } else
6137 I915_WRITE(aud_config, 0);
6138
6139 if (intel_eld_uptodate(connector,
6140 aud_cntrl_st2, eldv,
6141 aud_cntl_st, IBX_ELD_ADDRESS,
6142 hdmiw_hdmiedid))
6143 return;
6144
6145 i = I915_READ(aud_cntrl_st2);
6146 i &= ~eldv;
6147 I915_WRITE(aud_cntrl_st2, i);
6148
6149 if (!eld[0])
6150 return;
6151
6152 i = I915_READ(aud_cntl_st);
6153 i &= ~IBX_ELD_ADDRESS;
6154 I915_WRITE(aud_cntl_st, i);
6155 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6156 DRM_DEBUG_DRIVER("port num:%d\n", i);
6157
6158 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6159 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6160 for (i = 0; i < len; i++)
6161 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6162
6163 i = I915_READ(aud_cntrl_st2);
6164 i |= eldv;
6165 I915_WRITE(aud_cntrl_st2, i);
6166
6167 }
6168
ironlake_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6169 static void ironlake_write_eld(struct drm_connector *connector,
6170 struct drm_crtc *crtc)
6171 {
6172 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6173 uint8_t *eld = connector->eld;
6174 uint32_t eldv;
6175 uint32_t i;
6176 int len;
6177 int hdmiw_hdmiedid;
6178 int aud_config;
6179 int aud_cntl_st;
6180 int aud_cntrl_st2;
6181 int pipe = to_intel_crtc(crtc)->pipe;
6182
6183 if (HAS_PCH_IBX(connector->dev)) {
6184 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6185 aud_config = IBX_AUD_CFG(pipe);
6186 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6187 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6188 } else {
6189 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6190 aud_config = CPT_AUD_CFG(pipe);
6191 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6192 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6193 }
6194
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6196
6197 i = I915_READ(aud_cntl_st);
6198 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6199 if (!i) {
6200 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6201 /* operate blindly on all ports */
6202 eldv = IBX_ELD_VALIDB;
6203 eldv |= IBX_ELD_VALIDB << 4;
6204 eldv |= IBX_ELD_VALIDB << 8;
6205 } else {
6206 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6207 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6208 }
6209
6210 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6211 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6212 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6213 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6214 } else
6215 I915_WRITE(aud_config, 0);
6216
6217 if (intel_eld_uptodate(connector,
6218 aud_cntrl_st2, eldv,
6219 aud_cntl_st, IBX_ELD_ADDRESS,
6220 hdmiw_hdmiedid))
6221 return;
6222
6223 i = I915_READ(aud_cntrl_st2);
6224 i &= ~eldv;
6225 I915_WRITE(aud_cntrl_st2, i);
6226
6227 if (!eld[0])
6228 return;
6229
6230 i = I915_READ(aud_cntl_st);
6231 i &= ~IBX_ELD_ADDRESS;
6232 I915_WRITE(aud_cntl_st, i);
6233
6234 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6235 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6236 for (i = 0; i < len; i++)
6237 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6238
6239 i = I915_READ(aud_cntrl_st2);
6240 i |= eldv;
6241 I915_WRITE(aud_cntrl_st2, i);
6242 }
6243
intel_write_eld(struct drm_encoder * encoder,struct drm_display_mode * mode)6244 void intel_write_eld(struct drm_encoder *encoder,
6245 struct drm_display_mode *mode)
6246 {
6247 struct drm_crtc *crtc = encoder->crtc;
6248 struct drm_connector *connector;
6249 struct drm_device *dev = encoder->dev;
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251
6252 connector = drm_select_eld(encoder, mode);
6253 if (!connector)
6254 return;
6255
6256 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6257 connector->base.id,
6258 drm_get_connector_name(connector),
6259 connector->encoder->base.id,
6260 drm_get_encoder_name(connector->encoder));
6261
6262 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6263
6264 if (dev_priv->display.write_eld)
6265 dev_priv->display.write_eld(connector, crtc);
6266 }
6267
6268 /** Loads the palette/gamma unit for the CRTC with the prepared values */
intel_crtc_load_lut(struct drm_crtc * crtc)6269 void intel_crtc_load_lut(struct drm_crtc *crtc)
6270 {
6271 struct drm_device *dev = crtc->dev;
6272 struct drm_i915_private *dev_priv = dev->dev_private;
6273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6274 int palreg = PALETTE(intel_crtc->pipe);
6275 int i;
6276
6277 /* The clocks have to be on to load the palette. */
6278 if (!crtc->enabled || !intel_crtc->active)
6279 return;
6280
6281 /* use legacy palette for Ironlake */
6282 if (HAS_PCH_SPLIT(dev))
6283 palreg = LGC_PALETTE(intel_crtc->pipe);
6284
6285 for (i = 0; i < 256; i++) {
6286 I915_WRITE(palreg + 4 * i,
6287 (intel_crtc->lut_r[i] << 16) |
6288 (intel_crtc->lut_g[i] << 8) |
6289 intel_crtc->lut_b[i]);
6290 }
6291 }
6292
i845_update_cursor(struct drm_crtc * crtc,u32 base)6293 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6294 {
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6298 bool visible = base != 0;
6299 u32 cntl;
6300
6301 if (intel_crtc->cursor_visible == visible)
6302 return;
6303
6304 cntl = I915_READ(_CURACNTR);
6305 if (visible) {
6306 /* On these chipsets we can only modify the base whilst
6307 * the cursor is disabled.
6308 */
6309 I915_WRITE(_CURABASE, base);
6310
6311 cntl &= ~(CURSOR_FORMAT_MASK);
6312 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6313 cntl |= CURSOR_ENABLE |
6314 CURSOR_GAMMA_ENABLE |
6315 CURSOR_FORMAT_ARGB;
6316 } else
6317 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6318 I915_WRITE(_CURACNTR, cntl);
6319
6320 intel_crtc->cursor_visible = visible;
6321 }
6322
i9xx_update_cursor(struct drm_crtc * crtc,u32 base)6323 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6324 {
6325 struct drm_device *dev = crtc->dev;
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6328 int pipe = intel_crtc->pipe;
6329 bool visible = base != 0;
6330
6331 if (intel_crtc->cursor_visible != visible) {
6332 uint32_t cntl = I915_READ(CURCNTR(pipe));
6333 if (base) {
6334 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6335 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6336 cntl |= pipe << 28; /* Connect to correct pipe */
6337 } else {
6338 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6339 cntl |= CURSOR_MODE_DISABLE;
6340 }
6341 I915_WRITE(CURCNTR(pipe), cntl);
6342
6343 intel_crtc->cursor_visible = visible;
6344 }
6345 /* and commit changes on next vblank */
6346 I915_WRITE(CURBASE(pipe), base);
6347 }
6348
ivb_update_cursor(struct drm_crtc * crtc,u32 base)6349 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6350 {
6351 struct drm_device *dev = crtc->dev;
6352 struct drm_i915_private *dev_priv = dev->dev_private;
6353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6354 int pipe = intel_crtc->pipe;
6355 bool visible = base != 0;
6356
6357 if (intel_crtc->cursor_visible != visible) {
6358 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6359 if (base) {
6360 cntl &= ~CURSOR_MODE;
6361 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6362 } else {
6363 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6364 cntl |= CURSOR_MODE_DISABLE;
6365 }
6366 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6367
6368 intel_crtc->cursor_visible = visible;
6369 }
6370 /* and commit changes on next vblank */
6371 I915_WRITE(CURBASE_IVB(pipe), base);
6372 }
6373
6374 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
intel_crtc_update_cursor(struct drm_crtc * crtc,bool on)6375 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6376 bool on)
6377 {
6378 struct drm_device *dev = crtc->dev;
6379 struct drm_i915_private *dev_priv = dev->dev_private;
6380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381 int pipe = intel_crtc->pipe;
6382 int x = intel_crtc->cursor_x;
6383 int y = intel_crtc->cursor_y;
6384 u32 base, pos;
6385 bool visible;
6386
6387 pos = 0;
6388
6389 if (on && crtc->enabled && crtc->fb) {
6390 base = intel_crtc->cursor_addr;
6391 if (x > (int) crtc->fb->width)
6392 base = 0;
6393
6394 if (y > (int) crtc->fb->height)
6395 base = 0;
6396 } else
6397 base = 0;
6398
6399 if (x < 0) {
6400 if (x + intel_crtc->cursor_width < 0)
6401 base = 0;
6402
6403 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6404 x = -x;
6405 }
6406 pos |= x << CURSOR_X_SHIFT;
6407
6408 if (y < 0) {
6409 if (y + intel_crtc->cursor_height < 0)
6410 base = 0;
6411
6412 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6413 y = -y;
6414 }
6415 pos |= y << CURSOR_Y_SHIFT;
6416
6417 visible = base != 0;
6418 if (!visible && !intel_crtc->cursor_visible)
6419 return;
6420
6421 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6422 I915_WRITE(CURPOS_IVB(pipe), pos);
6423 ivb_update_cursor(crtc, base);
6424 } else {
6425 I915_WRITE(CURPOS(pipe), pos);
6426 if (IS_845G(dev) || IS_I865G(dev))
6427 i845_update_cursor(crtc, base);
6428 else
6429 i9xx_update_cursor(crtc, base);
6430 }
6431 }
6432
intel_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file,uint32_t handle,uint32_t width,uint32_t height)6433 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6434 struct drm_file *file,
6435 uint32_t handle,
6436 uint32_t width, uint32_t height)
6437 {
6438 struct drm_device *dev = crtc->dev;
6439 struct drm_i915_private *dev_priv = dev->dev_private;
6440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6441 struct drm_i915_gem_object *obj;
6442 uint32_t addr;
6443 int ret;
6444
6445 /* if we want to turn off the cursor ignore width and height */
6446 if (!handle) {
6447 DRM_DEBUG_KMS("cursor off\n");
6448 addr = 0;
6449 obj = NULL;
6450 DRM_LOCK(dev);
6451 goto finish;
6452 }
6453
6454 /* Currently we only support 64x64 cursors */
6455 if (width != 64 || height != 64) {
6456 DRM_ERROR("we currently only support 64x64 cursors\n");
6457 return -EINVAL;
6458 }
6459
6460 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6461 if (&obj->base == NULL)
6462 return -ENOENT;
6463
6464 if (obj->base.size < width * height * 4) {
6465 DRM_ERROR("buffer is to small\n");
6466 ret = -ENOMEM;
6467 goto fail;
6468 }
6469
6470 /* we only need to pin inside GTT if cursor is non-phy */
6471 DRM_LOCK(dev);
6472 if (!dev_priv->info->cursor_needs_physical) {
6473 if (obj->tiling_mode) {
6474 DRM_ERROR("cursor cannot be tiled\n");
6475 ret = -EINVAL;
6476 goto fail_locked;
6477 }
6478
6479 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6480 if (ret) {
6481 DRM_ERROR("failed to move cursor bo into the GTT\n");
6482 goto fail_locked;
6483 }
6484
6485 ret = i915_gem_object_put_fence(obj);
6486 if (ret) {
6487 DRM_ERROR("failed to release fence for cursor");
6488 goto fail_unpin;
6489 }
6490
6491 addr = obj->gtt_offset;
6492 } else {
6493 int align = IS_I830(dev) ? 16 * 1024 : 256;
6494 ret = i915_gem_attach_phys_object(dev, obj,
6495 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6496 align);
6497 if (ret) {
6498 DRM_ERROR("failed to attach phys object\n");
6499 goto fail_locked;
6500 }
6501 addr = obj->phys_obj->handle->busaddr;
6502 }
6503
6504 if (IS_GEN2(dev))
6505 I915_WRITE(CURSIZE, (height << 12) | width);
6506
6507 finish:
6508 if (intel_crtc->cursor_bo) {
6509 if (dev_priv->info->cursor_needs_physical) {
6510 if (intel_crtc->cursor_bo != obj)
6511 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6512 } else
6513 i915_gem_object_unpin(intel_crtc->cursor_bo);
6514 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6515 }
6516
6517 DRM_UNLOCK(dev);
6518
6519 intel_crtc->cursor_addr = addr;
6520 intel_crtc->cursor_bo = obj;
6521 intel_crtc->cursor_width = width;
6522 intel_crtc->cursor_height = height;
6523
6524 intel_crtc_update_cursor(crtc, true);
6525
6526 return 0;
6527 fail_unpin:
6528 i915_gem_object_unpin(obj);
6529 fail_locked:
6530 DRM_UNLOCK(dev);
6531 fail:
6532 drm_gem_object_unreference_unlocked(&obj->base);
6533 return ret;
6534 }
6535
intel_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)6536 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6537 {
6538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6539
6540 intel_crtc->cursor_x = x;
6541 intel_crtc->cursor_y = y;
6542
6543 intel_crtc_update_cursor(crtc, true);
6544
6545 return 0;
6546 }
6547
6548 /** Sets the color ramps on behalf of RandR */
intel_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)6549 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6550 u16 blue, int regno)
6551 {
6552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6553
6554 intel_crtc->lut_r[regno] = red >> 8;
6555 intel_crtc->lut_g[regno] = green >> 8;
6556 intel_crtc->lut_b[regno] = blue >> 8;
6557 }
6558
intel_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)6559 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6560 u16 *blue, int regno)
6561 {
6562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6563
6564 *red = intel_crtc->lut_r[regno] << 8;
6565 *green = intel_crtc->lut_g[regno] << 8;
6566 *blue = intel_crtc->lut_b[regno] << 8;
6567 }
6568
intel_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)6569 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6570 u16 *blue, uint32_t start, uint32_t size)
6571 {
6572 int end = (start + size > 256) ? 256 : start + size, i;
6573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6574
6575 for (i = start; i < end; i++) {
6576 intel_crtc->lut_r[i] = red[i] >> 8;
6577 intel_crtc->lut_g[i] = green[i] >> 8;
6578 intel_crtc->lut_b[i] = blue[i] >> 8;
6579 }
6580
6581 intel_crtc_load_lut(crtc);
6582 }
6583
6584 /**
6585 * Get a pipe with a simple mode set on it for doing load-based monitor
6586 * detection.
6587 *
6588 * It will be up to the load-detect code to adjust the pipe as appropriate for
6589 * its requirements. The pipe will be connected to no other encoders.
6590 *
6591 * Currently this code will only succeed if there is a pipe with no encoders
6592 * configured for it. In the future, it could choose to temporarily disable
6593 * some outputs to free up a pipe for its use.
6594 *
6595 * \return crtc, or NULL if no pipes are available.
6596 */
6597
6598 /* VESA 640x480x72Hz mode to set on the pipe */
6599 static struct drm_display_mode load_detect_mode = {
6600 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6601 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6602 };
6603
6604 static int
intel_framebuffer_create(struct drm_device * dev,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj,struct drm_framebuffer ** res)6605 intel_framebuffer_create(struct drm_device *dev,
6606 struct drm_mode_fb_cmd2 *mode_cmd,
6607 struct drm_i915_gem_object *obj,
6608 struct drm_framebuffer **res)
6609 {
6610 struct intel_framebuffer *intel_fb;
6611 int ret;
6612
6613 intel_fb = malloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
6614 if (!intel_fb) {
6615 drm_gem_object_unreference_unlocked(&obj->base);
6616 return -ENOMEM;
6617 }
6618
6619 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6620 if (ret) {
6621 drm_gem_object_unreference_unlocked(&obj->base);
6622 free(intel_fb, DRM_MEM_KMS);
6623 return ret;
6624 }
6625
6626 *res = &intel_fb->base;
6627 return 0;
6628 }
6629
6630 static u32
intel_framebuffer_pitch_for_width(int width,int bpp)6631 intel_framebuffer_pitch_for_width(int width, int bpp)
6632 {
6633 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6634 return roundup2(pitch, 64);
6635 }
6636
6637 static u32
intel_framebuffer_size_for_mode(struct drm_display_mode * mode,int bpp)6638 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6639 {
6640 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6641 return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
6642 }
6643
6644 static int
intel_framebuffer_create_for_mode(struct drm_device * dev,struct drm_display_mode * mode,int depth,int bpp,struct drm_framebuffer ** res)6645 intel_framebuffer_create_for_mode(struct drm_device *dev,
6646 struct drm_display_mode *mode,
6647 int depth, int bpp,
6648 struct drm_framebuffer **res)
6649 {
6650 struct drm_i915_gem_object *obj;
6651 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6652
6653 obj = i915_gem_alloc_object(dev,
6654 intel_framebuffer_size_for_mode(mode, bpp));
6655 if (obj == NULL)
6656 return -ENOMEM;
6657
6658 mode_cmd.width = mode->hdisplay;
6659 mode_cmd.height = mode->vdisplay;
6660 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6661 bpp);
6662 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6663
6664 return intel_framebuffer_create(dev, &mode_cmd, obj, res);
6665 }
6666
6667 static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device * dev,struct drm_display_mode * mode)6668 mode_fits_in_fbdev(struct drm_device *dev,
6669 struct drm_display_mode *mode)
6670 {
6671 struct drm_i915_private *dev_priv = dev->dev_private;
6672 struct drm_i915_gem_object *obj;
6673 struct drm_framebuffer *fb;
6674
6675 if (dev_priv->fbdev == NULL)
6676 return NULL;
6677
6678 obj = dev_priv->fbdev->ifb.obj;
6679 if (obj == NULL)
6680 return NULL;
6681
6682 fb = &dev_priv->fbdev->ifb.base;
6683 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6684 fb->bits_per_pixel))
6685 return NULL;
6686
6687 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6688 return NULL;
6689
6690 return fb;
6691 }
6692
intel_get_load_detect_pipe(struct drm_connector * connector,struct drm_display_mode * mode,struct intel_load_detect_pipe * old)6693 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6694 struct drm_display_mode *mode,
6695 struct intel_load_detect_pipe *old)
6696 {
6697 struct intel_crtc *intel_crtc;
6698 struct intel_encoder *intel_encoder =
6699 intel_attached_encoder(connector);
6700 struct drm_crtc *possible_crtc;
6701 struct drm_encoder *encoder = &intel_encoder->base;
6702 struct drm_crtc *crtc = NULL;
6703 struct drm_device *dev = encoder->dev;
6704 struct drm_framebuffer *fb;
6705 int i = -1;
6706 int ret;
6707
6708 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6709 connector->base.id, drm_get_connector_name(connector),
6710 encoder->base.id, drm_get_encoder_name(encoder));
6711
6712 /*
6713 * Algorithm gets a little messy:
6714 *
6715 * - if the connector already has an assigned crtc, use it (but make
6716 * sure it's on first)
6717 *
6718 * - try to find the first unused crtc that can drive this connector,
6719 * and use that if we find one
6720 */
6721
6722 /* See if we already have a CRTC for this connector */
6723 if (encoder->crtc) {
6724 crtc = encoder->crtc;
6725
6726 old->dpms_mode = connector->dpms;
6727 old->load_detect_temp = false;
6728
6729 /* Make sure the crtc and connector are running */
6730 if (connector->dpms != DRM_MODE_DPMS_ON)
6731 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6732
6733 return true;
6734 }
6735
6736 /* Find an unused one (if possible) */
6737 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6738 i++;
6739 if (!(encoder->possible_crtcs & (1 << i)))
6740 continue;
6741 if (!possible_crtc->enabled) {
6742 crtc = possible_crtc;
6743 break;
6744 }
6745 }
6746
6747 /*
6748 * If we didn't find an unused CRTC, don't use any.
6749 */
6750 if (!crtc) {
6751 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6752 return false;
6753 }
6754
6755 intel_encoder->new_crtc = to_intel_crtc(crtc);
6756 to_intel_connector(connector)->new_encoder = intel_encoder;
6757
6758 intel_crtc = to_intel_crtc(crtc);
6759 old->dpms_mode = connector->dpms;
6760 old->load_detect_temp = true;
6761 old->release_fb = NULL;
6762
6763 if (!mode)
6764 mode = &load_detect_mode;
6765
6766 /* We need a framebuffer large enough to accommodate all accesses
6767 * that the plane may generate whilst we perform load detection.
6768 * We can not rely on the fbcon either being present (we get called
6769 * during its initialisation to detect all boot displays, or it may
6770 * not even exist) or that it is large enough to satisfy the
6771 * requested mode.
6772 */
6773 ret = 0;
6774 fb = mode_fits_in_fbdev(dev, mode);
6775 if (fb == NULL) {
6776 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6777 ret = intel_framebuffer_create_for_mode(dev, mode, 24, 32, &fb);
6778 old->release_fb = fb;
6779 } else
6780 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6781 if (ret) {
6782 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6783 return false;
6784 }
6785
6786 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6787 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6788 if (old->release_fb)
6789 old->release_fb->funcs->destroy(old->release_fb);
6790 return false;
6791 }
6792
6793 /* let the connector get through one full cycle before testing */
6794 intel_wait_for_vblank(dev, intel_crtc->pipe);
6795 return true;
6796 }
6797
intel_release_load_detect_pipe(struct drm_connector * connector,struct intel_load_detect_pipe * old)6798 void intel_release_load_detect_pipe(struct drm_connector *connector,
6799 struct intel_load_detect_pipe *old)
6800 {
6801 struct intel_encoder *intel_encoder =
6802 intel_attached_encoder(connector);
6803 struct drm_encoder *encoder = &intel_encoder->base;
6804
6805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6806 connector->base.id, drm_get_connector_name(connector),
6807 encoder->base.id, drm_get_encoder_name(encoder));
6808
6809 if (old->load_detect_temp) {
6810 struct drm_crtc *crtc = encoder->crtc;
6811
6812 to_intel_connector(connector)->new_encoder = NULL;
6813 intel_encoder->new_crtc = NULL;
6814 intel_set_mode(crtc, NULL, 0, 0, NULL);
6815
6816 if (old->release_fb)
6817 old->release_fb->funcs->destroy(old->release_fb);
6818
6819 return;
6820 }
6821
6822 /* Switch crtc and encoder back off if necessary */
6823 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6824 connector->funcs->dpms(connector, old->dpms_mode);
6825 }
6826
6827 /* Returns the clock of the currently programmed mode of the given pipe. */
intel_crtc_clock_get(struct drm_device * dev,struct drm_crtc * crtc)6828 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6829 {
6830 struct drm_i915_private *dev_priv = dev->dev_private;
6831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6832 int pipe = intel_crtc->pipe;
6833 u32 dpll = I915_READ(DPLL(pipe));
6834 u32 fp;
6835 intel_clock_t clock;
6836
6837 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6838 fp = I915_READ(FP0(pipe));
6839 else
6840 fp = I915_READ(FP1(pipe));
6841
6842 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6843 if (IS_PINEVIEW(dev)) {
6844 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6845 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6846 } else {
6847 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6848 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6849 }
6850
6851 if (!IS_GEN2(dev)) {
6852 if (IS_PINEVIEW(dev))
6853 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6854 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6855 else
6856 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6857 DPLL_FPA01_P1_POST_DIV_SHIFT);
6858
6859 switch (dpll & DPLL_MODE_MASK) {
6860 case DPLLB_MODE_DAC_SERIAL:
6861 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6862 5 : 10;
6863 break;
6864 case DPLLB_MODE_LVDS:
6865 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6866 7 : 14;
6867 break;
6868 default:
6869 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6870 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6871 return 0;
6872 }
6873
6874 /* XXX: Handle the 100Mhz refclk */
6875 intel_clock(dev, 96000, &clock);
6876 } else {
6877 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6878
6879 if (is_lvds) {
6880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6881 DPLL_FPA01_P1_POST_DIV_SHIFT);
6882 clock.p2 = 14;
6883
6884 if ((dpll & PLL_REF_INPUT_MASK) ==
6885 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6886 /* XXX: might not be 66MHz */
6887 intel_clock(dev, 66000, &clock);
6888 } else
6889 intel_clock(dev, 48000, &clock);
6890 } else {
6891 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6892 clock.p1 = 2;
6893 else {
6894 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6895 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6896 }
6897 if (dpll & PLL_P2_DIVIDE_BY_4)
6898 clock.p2 = 4;
6899 else
6900 clock.p2 = 2;
6901
6902 intel_clock(dev, 48000, &clock);
6903 }
6904 }
6905
6906 /* XXX: It would be nice to validate the clocks, but we can't reuse
6907 * i830PllIsValid() because it relies on the xf86_config connector
6908 * configuration being accurate, which it isn't necessarily.
6909 */
6910
6911 return clock.dot;
6912 }
6913
6914 /** Returns the currently programmed mode of the given pipe. */
intel_crtc_mode_get(struct drm_device * dev,struct drm_crtc * crtc)6915 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6916 struct drm_crtc *crtc)
6917 {
6918 struct drm_i915_private *dev_priv = dev->dev_private;
6919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6920 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6921 struct drm_display_mode *mode;
6922 int htot = I915_READ(HTOTAL(cpu_transcoder));
6923 int hsync = I915_READ(HSYNC(cpu_transcoder));
6924 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6925 int vsync = I915_READ(VSYNC(cpu_transcoder));
6926
6927 mode = malloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
6928 if (!mode)
6929 return NULL;
6930
6931 mode->clock = intel_crtc_clock_get(dev, crtc);
6932 mode->hdisplay = (htot & 0xffff) + 1;
6933 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6934 mode->hsync_start = (hsync & 0xffff) + 1;
6935 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6936 mode->vdisplay = (vtot & 0xffff) + 1;
6937 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6938 mode->vsync_start = (vsync & 0xffff) + 1;
6939 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6940
6941 drm_mode_set_name(mode);
6942
6943 return mode;
6944 }
6945
intel_increase_pllclock(struct drm_crtc * crtc)6946 static void intel_increase_pllclock(struct drm_crtc *crtc)
6947 {
6948 struct drm_device *dev = crtc->dev;
6949 drm_i915_private_t *dev_priv = dev->dev_private;
6950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6951 int pipe = intel_crtc->pipe;
6952 int dpll_reg = DPLL(pipe);
6953 int dpll;
6954
6955 if (HAS_PCH_SPLIT(dev))
6956 return;
6957
6958 if (!dev_priv->lvds_downclock_avail)
6959 return;
6960
6961 dpll = I915_READ(dpll_reg);
6962 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6963 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6964
6965 assert_panel_unlocked(dev_priv, pipe);
6966
6967 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6968 I915_WRITE(dpll_reg, dpll);
6969 intel_wait_for_vblank(dev, pipe);
6970
6971 dpll = I915_READ(dpll_reg);
6972 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6973 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6974 }
6975 }
6976
intel_decrease_pllclock(struct drm_crtc * crtc)6977 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6978 {
6979 struct drm_device *dev = crtc->dev;
6980 drm_i915_private_t *dev_priv = dev->dev_private;
6981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6982
6983 if (HAS_PCH_SPLIT(dev))
6984 return;
6985
6986 if (!dev_priv->lvds_downclock_avail)
6987 return;
6988
6989 /*
6990 * Since this is called by a timer, we should never get here in
6991 * the manual case.
6992 */
6993 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6994 int pipe = intel_crtc->pipe;
6995 int dpll_reg = DPLL(pipe);
6996 int dpll;
6997
6998 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6999
7000 assert_panel_unlocked(dev_priv, pipe);
7001
7002 dpll = I915_READ(dpll_reg);
7003 dpll |= DISPLAY_RATE_SELECT_FPA1;
7004 I915_WRITE(dpll_reg, dpll);
7005 intel_wait_for_vblank(dev, pipe);
7006 dpll = I915_READ(dpll_reg);
7007 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7008 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7009 }
7010
7011 }
7012
intel_mark_busy(struct drm_device * dev)7013 void intel_mark_busy(struct drm_device *dev)
7014 {
7015 i915_update_gfx_val(dev->dev_private);
7016 }
7017
intel_mark_idle(struct drm_device * dev)7018 void intel_mark_idle(struct drm_device *dev)
7019 {
7020 struct drm_crtc *crtc;
7021
7022 if (!i915_powersave)
7023 return;
7024
7025 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7026 if (!crtc->fb)
7027 continue;
7028
7029 intel_decrease_pllclock(crtc);
7030 }
7031 }
7032
intel_mark_fb_busy(struct drm_i915_gem_object * obj)7033 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7034 {
7035 struct drm_device *dev = obj->base.dev;
7036 struct drm_crtc *crtc;
7037
7038 if (!i915_powersave)
7039 return;
7040
7041 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7042 if (!crtc->fb)
7043 continue;
7044
7045 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7046 intel_increase_pllclock(crtc);
7047 }
7048 }
7049
intel_crtc_destroy(struct drm_crtc * crtc)7050 static void intel_crtc_destroy(struct drm_crtc *crtc)
7051 {
7052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7053 struct drm_device *dev = crtc->dev;
7054 struct drm_i915_private *dev_priv = dev->dev_private;
7055 struct intel_unpin_work *work;
7056
7057 mtx_lock(&dev->event_lock);
7058 work = intel_crtc->unpin_work;
7059 intel_crtc->unpin_work = NULL;
7060 mtx_unlock(&dev->event_lock);
7061
7062 if (work) {
7063 taskqueue_cancel(dev_priv->wq, &work->work, NULL);
7064 taskqueue_drain(dev_priv->wq, &work->work);
7065 free(work, DRM_MEM_KMS);
7066 }
7067
7068 drm_crtc_cleanup(crtc);
7069
7070 free(intel_crtc, DRM_MEM_KMS);
7071 }
7072
intel_unpin_work_fn(void * arg,int pending)7073 static void intel_unpin_work_fn(void *arg, int pending)
7074 {
7075 struct intel_unpin_work *work =
7076 arg;
7077 struct drm_device *dev = work->crtc->dev;
7078
7079 DRM_LOCK(dev);
7080 intel_unpin_fb_obj(work->old_fb_obj);
7081 drm_gem_object_unreference(&work->pending_flip_obj->base);
7082 drm_gem_object_unreference(&work->old_fb_obj->base);
7083
7084 intel_update_fbc(dev);
7085 DRM_UNLOCK(dev);
7086
7087 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7088 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7089
7090 free(work, DRM_MEM_KMS);
7091 }
7092
do_intel_finish_page_flip(struct drm_device * dev,struct drm_crtc * crtc)7093 static void do_intel_finish_page_flip(struct drm_device *dev,
7094 struct drm_crtc *crtc)
7095 {
7096 drm_i915_private_t *dev_priv = dev->dev_private;
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098 struct intel_unpin_work *work;
7099 struct drm_i915_gem_object *obj;
7100
7101 /* Ignore early vblank irqs */
7102 if (intel_crtc == NULL)
7103 return;
7104
7105 mtx_lock(&dev->event_lock);
7106 work = intel_crtc->unpin_work;
7107
7108 /* Ensure we don't miss a work->pending update ... */
7109 smp_rmb();
7110
7111 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7112 mtx_unlock(&dev->event_lock);
7113 return;
7114 }
7115
7116 /* and that the unpin work is consistent wrt ->pending. */
7117 smp_rmb();
7118
7119 intel_crtc->unpin_work = NULL;
7120
7121 if (work->event)
7122 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7123
7124 drm_vblank_put(dev, intel_crtc->pipe);
7125
7126 mtx_unlock(&dev->event_lock);
7127
7128 obj = work->old_fb_obj;
7129
7130 atomic_clear_mask(1 << intel_crtc->plane,
7131 &obj->pending_flip);
7132 wake_up(&dev_priv->pending_flip_queue);
7133
7134 taskqueue_enqueue(dev_priv->wq, &work->work);
7135
7136 CTR2(KTR_DRM, "i915_flip_complete %d %p", intel_crtc->plane,
7137 work->pending_flip_obj);
7138 }
7139
intel_finish_page_flip(struct drm_device * dev,int pipe)7140 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7141 {
7142 drm_i915_private_t *dev_priv = dev->dev_private;
7143 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7144
7145 do_intel_finish_page_flip(dev, crtc);
7146 }
7147
intel_finish_page_flip_plane(struct drm_device * dev,int plane)7148 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7149 {
7150 drm_i915_private_t *dev_priv = dev->dev_private;
7151 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7152
7153 do_intel_finish_page_flip(dev, crtc);
7154 }
7155
intel_prepare_page_flip(struct drm_device * dev,int plane)7156 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7157 {
7158 drm_i915_private_t *dev_priv = dev->dev_private;
7159 struct intel_crtc *intel_crtc =
7160 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7161
7162 /* NB: An MMIO update of the plane base pointer will also
7163 * generate a page-flip completion irq, i.e. every modeset
7164 * is also accompanied by a spurious intel_prepare_page_flip().
7165 */
7166 mtx_lock(&dev->event_lock);
7167 if (intel_crtc->unpin_work)
7168 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7169 mtx_unlock(&dev->event_lock);
7170 }
7171
intel_mark_page_flip_active(struct intel_crtc * intel_crtc)7172 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7173 {
7174 /* Ensure that the work item is consistent when activating it ... */
7175 smp_wmb();
7176 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7177 /* and that it is marked active as soon as the irq could fire. */
7178 smp_wmb();
7179 }
7180
intel_gen2_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7181 static int intel_gen2_queue_flip(struct drm_device *dev,
7182 struct drm_crtc *crtc,
7183 struct drm_framebuffer *fb,
7184 struct drm_i915_gem_object *obj)
7185 {
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 u32 flip_mask;
7189 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7190 int ret;
7191
7192 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7193 if (ret)
7194 goto err;
7195
7196 ret = intel_ring_begin(ring, 6);
7197 if (ret)
7198 goto err_unpin;
7199
7200 /* Can't queue multiple flips, so wait for the previous
7201 * one to finish before executing the next.
7202 */
7203 if (intel_crtc->plane)
7204 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7205 else
7206 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7207 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7208 intel_ring_emit(ring, MI_NOOP);
7209 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7210 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7211 intel_ring_emit(ring, fb->pitches[0]);
7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7213 intel_ring_emit(ring, 0); /* aux display base address, unused */
7214
7215 intel_mark_page_flip_active(intel_crtc);
7216 intel_ring_advance(ring);
7217 return 0;
7218
7219 err_unpin:
7220 intel_unpin_fb_obj(obj);
7221 err:
7222 return ret;
7223 }
7224
intel_gen3_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7225 static int intel_gen3_queue_flip(struct drm_device *dev,
7226 struct drm_crtc *crtc,
7227 struct drm_framebuffer *fb,
7228 struct drm_i915_gem_object *obj)
7229 {
7230 struct drm_i915_private *dev_priv = dev->dev_private;
7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7232 u32 flip_mask;
7233 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7234 int ret;
7235
7236 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7237 if (ret)
7238 goto err;
7239
7240 ret = intel_ring_begin(ring, 6);
7241 if (ret)
7242 goto err_unpin;
7243
7244 if (intel_crtc->plane)
7245 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7246 else
7247 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7248 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7249 intel_ring_emit(ring, MI_NOOP);
7250 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7251 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7252 intel_ring_emit(ring, fb->pitches[0]);
7253 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7254 intel_ring_emit(ring, MI_NOOP);
7255
7256 intel_mark_page_flip_active(intel_crtc);
7257 intel_ring_advance(ring);
7258 return 0;
7259
7260 err_unpin:
7261 intel_unpin_fb_obj(obj);
7262 err:
7263 return ret;
7264 }
7265
intel_gen4_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7266 static int intel_gen4_queue_flip(struct drm_device *dev,
7267 struct drm_crtc *crtc,
7268 struct drm_framebuffer *fb,
7269 struct drm_i915_gem_object *obj)
7270 {
7271 struct drm_i915_private *dev_priv = dev->dev_private;
7272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7273 uint32_t pf, pipesrc;
7274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7275 int ret;
7276
7277 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7278 if (ret)
7279 goto err;
7280
7281 ret = intel_ring_begin(ring, 4);
7282 if (ret)
7283 goto err_unpin;
7284
7285 /* i965+ uses the linear or tiled offsets from the
7286 * Display Registers (which do not change across a page-flip)
7287 * so we need only reprogram the base address.
7288 */
7289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7291 intel_ring_emit(ring, fb->pitches[0]);
7292 intel_ring_emit(ring,
7293 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7294 obj->tiling_mode);
7295
7296 /* XXX Enabling the panel-fitter across page-flip is so far
7297 * untested on non-native modes, so ignore it for now.
7298 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7299 */
7300 pf = 0;
7301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7302 intel_ring_emit(ring, pf | pipesrc);
7303
7304 intel_mark_page_flip_active(intel_crtc);
7305 intel_ring_advance(ring);
7306 return 0;
7307
7308 err_unpin:
7309 intel_unpin_fb_obj(obj);
7310 err:
7311 return ret;
7312 }
7313
intel_gen6_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7314 static int intel_gen6_queue_flip(struct drm_device *dev,
7315 struct drm_crtc *crtc,
7316 struct drm_framebuffer *fb,
7317 struct drm_i915_gem_object *obj)
7318 {
7319 struct drm_i915_private *dev_priv = dev->dev_private;
7320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7321 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7322 uint32_t pf, pipesrc;
7323 int ret;
7324
7325 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7326 if (ret)
7327 goto err;
7328
7329 ret = intel_ring_begin(ring, 4);
7330 if (ret)
7331 goto err_unpin;
7332
7333 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7334 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7335 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7336 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7337
7338 /* Contrary to the suggestions in the documentation,
7339 * "Enable Panel Fitter" does not seem to be required when page
7340 * flipping with a non-native mode, and worse causes a normal
7341 * modeset to fail.
7342 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7343 */
7344 pf = 0;
7345 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7346 intel_ring_emit(ring, pf | pipesrc);
7347
7348 intel_mark_page_flip_active(intel_crtc);
7349 intel_ring_advance(ring);
7350 return 0;
7351
7352 err_unpin:
7353 intel_unpin_fb_obj(obj);
7354 err:
7355 return ret;
7356 }
7357
7358 /*
7359 * On gen7 we currently use the blit ring because (in early silicon at least)
7360 * the render ring doesn't give us interrpts for page flip completion, which
7361 * means clients will hang after the first flip is queued. Fortunately the
7362 * blit ring generates interrupts properly, so use it instead.
7363 */
intel_gen7_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7364 static int intel_gen7_queue_flip(struct drm_device *dev,
7365 struct drm_crtc *crtc,
7366 struct drm_framebuffer *fb,
7367 struct drm_i915_gem_object *obj)
7368 {
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7372 uint32_t plane_bit = 0;
7373 int ret;
7374
7375 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7376 if (ret)
7377 goto err;
7378
7379 switch(intel_crtc->plane) {
7380 case PLANE_A:
7381 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7382 break;
7383 case PLANE_B:
7384 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7385 break;
7386 case PLANE_C:
7387 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7388 break;
7389 default:
7390 WARN_ONCE(1, "unknown plane in flip command\n");
7391 ret = -ENODEV;
7392 goto err_unpin;
7393 }
7394
7395 ret = intel_ring_begin(ring, 4);
7396 if (ret)
7397 goto err_unpin;
7398
7399 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7400 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7401 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7402 intel_ring_emit(ring, (MI_NOOP));
7403
7404 intel_mark_page_flip_active(intel_crtc);
7405 intel_ring_advance(ring);
7406 return 0;
7407
7408 err_unpin:
7409 intel_unpin_fb_obj(obj);
7410 err:
7411 return ret;
7412 }
7413
intel_default_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7414 static int intel_default_queue_flip(struct drm_device *dev,
7415 struct drm_crtc *crtc,
7416 struct drm_framebuffer *fb,
7417 struct drm_i915_gem_object *obj)
7418 {
7419 return -ENODEV;
7420 }
7421
intel_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event)7422 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7423 struct drm_framebuffer *fb,
7424 struct drm_pending_vblank_event *event)
7425 {
7426 struct drm_device *dev = crtc->dev;
7427 struct drm_i915_private *dev_priv = dev->dev_private;
7428 struct drm_framebuffer *old_fb = crtc->fb;
7429 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7431 struct intel_unpin_work *work;
7432 int ret;
7433
7434 /* Can't change pixel format via MI display flips. */
7435 if (fb->pixel_format != crtc->fb->pixel_format)
7436 return -EINVAL;
7437
7438 /*
7439 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7440 * Note that pitch changes could also affect these register.
7441 */
7442 if (INTEL_INFO(dev)->gen > 3 &&
7443 (fb->offsets[0] != crtc->fb->offsets[0] ||
7444 fb->pitches[0] != crtc->fb->pitches[0]))
7445 return -EINVAL;
7446
7447 work = malloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
7448 if (work == NULL)
7449 return -ENOMEM;
7450
7451 work->event = event;
7452 work->crtc = crtc;
7453 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7454 TASK_INIT(&work->work, 0, intel_unpin_work_fn, work);
7455
7456 ret = drm_vblank_get(dev, intel_crtc->pipe);
7457 if (ret)
7458 goto free_work;
7459
7460 /* We borrow the event spin lock for protecting unpin_work */
7461 mtx_lock(&dev->event_lock);
7462 if (intel_crtc->unpin_work) {
7463 mtx_unlock(&dev->event_lock);
7464 free(work, DRM_MEM_KMS);
7465 drm_vblank_put(dev, intel_crtc->pipe);
7466
7467 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7468 return -EBUSY;
7469 }
7470 intel_crtc->unpin_work = work;
7471 mtx_unlock(&dev->event_lock);
7472
7473 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7474 taskqueue_drain_all(dev_priv->wq);
7475
7476 ret = i915_mutex_lock_interruptible(dev);
7477 if (ret)
7478 goto cleanup;
7479
7480 /* Reference the objects for the scheduled work. */
7481 drm_gem_object_reference(&work->old_fb_obj->base);
7482 drm_gem_object_reference(&obj->base);
7483
7484 crtc->fb = fb;
7485
7486 work->pending_flip_obj = obj;
7487
7488 work->enable_stall_check = true;
7489
7490 /* Block clients from rendering to the new back buffer until
7491 * the flip occurs and the object is no longer visible.
7492 */
7493 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7494 atomic_inc(&intel_crtc->unpin_work_count);
7495
7496 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7497 if (ret)
7498 goto cleanup_pending;
7499
7500 intel_disable_fbc(dev);
7501 intel_mark_fb_busy(obj);
7502 DRM_UNLOCK(dev);
7503
7504 CTR2(KTR_DRM, "i915_flip_request %d %p", intel_crtc->plane, obj);
7505
7506 return 0;
7507
7508 cleanup_pending:
7509 atomic_dec(&intel_crtc->unpin_work_count);
7510 crtc->fb = old_fb;
7511 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7512 drm_gem_object_unreference(&work->old_fb_obj->base);
7513 drm_gem_object_unreference(&obj->base);
7514 DRM_UNLOCK(dev);
7515
7516 cleanup:
7517 mtx_lock(&dev->event_lock);
7518 intel_crtc->unpin_work = NULL;
7519 mtx_unlock(&dev->event_lock);
7520
7521 drm_vblank_put(dev, intel_crtc->pipe);
7522 free_work:
7523 free(work, DRM_MEM_KMS);
7524
7525 return ret;
7526 }
7527
7528 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7529 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7530 .load_lut = intel_crtc_load_lut,
7531 .disable = intel_crtc_noop,
7532 };
7533
intel_encoder_check_is_cloned(struct intel_encoder * encoder)7534 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7535 {
7536 struct intel_encoder *other_encoder;
7537 struct drm_crtc *crtc = &encoder->new_crtc->base;
7538
7539 if (WARN_ON(!crtc))
7540 return false;
7541
7542 list_for_each_entry(other_encoder,
7543 &crtc->dev->mode_config.encoder_list,
7544 base.head) {
7545
7546 if (&other_encoder->new_crtc->base != crtc ||
7547 encoder == other_encoder)
7548 continue;
7549 else
7550 return true;
7551 }
7552
7553 return false;
7554 }
7555
intel_encoder_crtc_ok(struct drm_encoder * encoder,struct drm_crtc * crtc)7556 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7557 struct drm_crtc *crtc)
7558 {
7559 struct drm_device *dev;
7560 struct drm_crtc *tmp;
7561 int crtc_mask = 1;
7562
7563 WARN(!crtc, "checking null crtc?\n");
7564
7565 dev = crtc->dev;
7566
7567 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7568 if (tmp == crtc)
7569 break;
7570 crtc_mask <<= 1;
7571 }
7572
7573 if (encoder->possible_crtcs & crtc_mask)
7574 return true;
7575 return false;
7576 }
7577
7578 /**
7579 * intel_modeset_update_staged_output_state
7580 *
7581 * Updates the staged output configuration state, e.g. after we've read out the
7582 * current hw state.
7583 */
intel_modeset_update_staged_output_state(struct drm_device * dev)7584 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7585 {
7586 struct intel_encoder *encoder;
7587 struct intel_connector *connector;
7588
7589 list_for_each_entry(connector, &dev->mode_config.connector_list,
7590 base.head) {
7591 connector->new_encoder =
7592 to_intel_encoder(connector->base.encoder);
7593 }
7594
7595 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7596 base.head) {
7597 encoder->new_crtc =
7598 to_intel_crtc(encoder->base.crtc);
7599 }
7600 }
7601
7602 /**
7603 * intel_modeset_commit_output_state
7604 *
7605 * This function copies the stage display pipe configuration to the real one.
7606 */
intel_modeset_commit_output_state(struct drm_device * dev)7607 static void intel_modeset_commit_output_state(struct drm_device *dev)
7608 {
7609 struct intel_encoder *encoder;
7610 struct intel_connector *connector;
7611
7612 list_for_each_entry(connector, &dev->mode_config.connector_list,
7613 base.head) {
7614 connector->base.encoder = &connector->new_encoder->base;
7615 }
7616
7617 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7618 base.head) {
7619 encoder->base.crtc = &encoder->new_crtc->base;
7620 }
7621 }
7622
7623 static int
intel_modeset_adjusted_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,struct drm_display_mode ** res)7624 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7625 struct drm_display_mode *mode,
7626 struct drm_display_mode **res)
7627 {
7628 struct drm_device *dev = crtc->dev;
7629 struct drm_display_mode *adjusted_mode;
7630 struct drm_encoder_helper_funcs *encoder_funcs;
7631 struct intel_encoder *encoder;
7632
7633 adjusted_mode = drm_mode_duplicate(dev, mode);
7634 if (!adjusted_mode)
7635 return -ENOMEM;
7636
7637 /* Pass our mode to the connectors and the CRTC to give them a chance to
7638 * adjust it according to limitations or connector properties, and also
7639 * a chance to reject the mode entirely.
7640 */
7641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7642 base.head) {
7643
7644 if (&encoder->new_crtc->base != crtc)
7645 continue;
7646 encoder_funcs = encoder->base.helper_private;
7647 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7648 adjusted_mode))) {
7649 DRM_DEBUG_KMS("Encoder fixup failed\n");
7650 goto fail;
7651 }
7652 }
7653
7654 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7655 DRM_DEBUG_KMS("CRTC fixup failed\n");
7656 goto fail;
7657 }
7658 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7659
7660 *res = adjusted_mode;
7661 return 0;
7662 fail:
7663 drm_mode_destroy(dev, adjusted_mode);
7664 return -EINVAL;
7665 }
7666
7667 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7668 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7669 static void
intel_modeset_affected_pipes(struct drm_crtc * crtc,unsigned * modeset_pipes,unsigned * prepare_pipes,unsigned * disable_pipes)7670 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7671 unsigned *prepare_pipes, unsigned *disable_pipes)
7672 {
7673 struct intel_crtc *intel_crtc;
7674 struct drm_device *dev = crtc->dev;
7675 struct intel_encoder *encoder;
7676 struct intel_connector *connector;
7677 struct drm_crtc *tmp_crtc;
7678
7679 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7680
7681 /* Check which crtcs have changed outputs connected to them, these need
7682 * to be part of the prepare_pipes mask. We don't (yet) support global
7683 * modeset across multiple crtcs, so modeset_pipes will only have one
7684 * bit set at most. */
7685 list_for_each_entry(connector, &dev->mode_config.connector_list,
7686 base.head) {
7687 if (connector->base.encoder == &connector->new_encoder->base)
7688 continue;
7689
7690 if (connector->base.encoder) {
7691 tmp_crtc = connector->base.encoder->crtc;
7692
7693 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7694 }
7695
7696 if (connector->new_encoder)
7697 *prepare_pipes |=
7698 1 << connector->new_encoder->new_crtc->pipe;
7699 }
7700
7701 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7702 base.head) {
7703 if (encoder->base.crtc == &encoder->new_crtc->base)
7704 continue;
7705
7706 if (encoder->base.crtc) {
7707 tmp_crtc = encoder->base.crtc;
7708
7709 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7710 }
7711
7712 if (encoder->new_crtc)
7713 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7714 }
7715
7716 /* Check for any pipes that will be fully disabled ... */
7717 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7718 base.head) {
7719 bool used = false;
7720
7721 /* Don't try to disable disabled crtcs. */
7722 if (!intel_crtc->base.enabled)
7723 continue;
7724
7725 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7726 base.head) {
7727 if (encoder->new_crtc == intel_crtc)
7728 used = true;
7729 }
7730
7731 if (!used)
7732 *disable_pipes |= 1 << intel_crtc->pipe;
7733 }
7734
7735
7736 /* set_mode is also used to update properties on life display pipes. */
7737 intel_crtc = to_intel_crtc(crtc);
7738 if (crtc->enabled)
7739 *prepare_pipes |= 1 << intel_crtc->pipe;
7740
7741 /*
7742 * For simplicity do a full modeset on any pipe where the output routing
7743 * changed. We could be more clever, but that would require us to be
7744 * more careful with calling the relevant encoder->mode_set functions.
7745 */
7746 if (*prepare_pipes)
7747 *modeset_pipes = *prepare_pipes;
7748
7749 /* ... and mask these out. */
7750 *modeset_pipes &= ~(*disable_pipes);
7751 *prepare_pipes &= ~(*disable_pipes);
7752
7753 /*
7754 * HACK: We don't (yet) fully support global modesets. intel_set_config
7755 * obies this rule, but the modeset restore mode of
7756 * intel_modeset_setup_hw_state does not.
7757 */
7758 *modeset_pipes &= 1 << intel_crtc->pipe;
7759 *prepare_pipes &= 1 << intel_crtc->pipe;
7760 }
7761
intel_crtc_in_use(struct drm_crtc * crtc)7762 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7763 {
7764 struct drm_encoder *encoder;
7765 struct drm_device *dev = crtc->dev;
7766
7767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7768 if (encoder->crtc == crtc)
7769 return true;
7770
7771 return false;
7772 }
7773
7774 static void
intel_modeset_update_state(struct drm_device * dev,unsigned prepare_pipes)7775 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7776 {
7777 struct intel_encoder *intel_encoder;
7778 struct intel_crtc *intel_crtc;
7779 struct drm_connector *connector;
7780
7781 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7782 base.head) {
7783 if (!intel_encoder->base.crtc)
7784 continue;
7785
7786 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7787
7788 if (prepare_pipes & (1 << intel_crtc->pipe))
7789 intel_encoder->connectors_active = false;
7790 }
7791
7792 intel_modeset_commit_output_state(dev);
7793
7794 /* Update computed state. */
7795 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7796 base.head) {
7797 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7798 }
7799
7800 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7801 if (!connector->encoder || !connector->encoder->crtc)
7802 continue;
7803
7804 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7805
7806 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7807 struct drm_property *dpms_property =
7808 dev->mode_config.dpms_property;
7809
7810 connector->dpms = DRM_MODE_DPMS_ON;
7811 drm_object_property_set_value(&connector->base,
7812 dpms_property,
7813 DRM_MODE_DPMS_ON);
7814
7815 intel_encoder = to_intel_encoder(connector->encoder);
7816 intel_encoder->connectors_active = true;
7817 }
7818 }
7819
7820 }
7821
7822 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7823 list_for_each_entry((intel_crtc), \
7824 &(dev)->mode_config.crtc_list, \
7825 base.head) \
7826 if (mask & (1 <<(intel_crtc)->pipe)) \
7827
7828 void
intel_modeset_check_state(struct drm_device * dev)7829 intel_modeset_check_state(struct drm_device *dev)
7830 {
7831 struct intel_crtc *crtc;
7832 struct intel_encoder *encoder;
7833 struct intel_connector *connector;
7834
7835 list_for_each_entry(connector, &dev->mode_config.connector_list,
7836 base.head) {
7837 /* This also checks the encoder/connector hw state with the
7838 * ->get_hw_state callbacks. */
7839 intel_connector_check_state(connector);
7840
7841 WARN(&connector->new_encoder->base != connector->base.encoder,
7842 "connector's staged encoder doesn't match current encoder\n");
7843 }
7844
7845 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7846 base.head) {
7847 bool enabled = false;
7848 bool active = false;
7849 enum pipe pipe, tracked_pipe;
7850
7851 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7852 encoder->base.base.id,
7853 drm_get_encoder_name(&encoder->base));
7854
7855 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7856 "encoder's stage crtc doesn't match current crtc\n");
7857 WARN(encoder->connectors_active && !encoder->base.crtc,
7858 "encoder's active_connectors set, but no crtc\n");
7859
7860 list_for_each_entry(connector, &dev->mode_config.connector_list,
7861 base.head) {
7862 if (connector->base.encoder != &encoder->base)
7863 continue;
7864 enabled = true;
7865 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7866 active = true;
7867 }
7868 WARN(!!encoder->base.crtc != enabled,
7869 "encoder's enabled state mismatch "
7870 "(expected %i, found %i)\n",
7871 !!encoder->base.crtc, enabled);
7872 WARN(active && !encoder->base.crtc,
7873 "active encoder with no crtc\n");
7874
7875 WARN(encoder->connectors_active != active,
7876 "encoder's computed active state doesn't match tracked active state "
7877 "(expected %i, found %i)\n", active, encoder->connectors_active);
7878
7879 active = encoder->get_hw_state(encoder, &pipe);
7880 WARN(active != encoder->connectors_active,
7881 "encoder's hw state doesn't match sw tracking "
7882 "(expected %i, found %i)\n",
7883 encoder->connectors_active, active);
7884
7885 if (!encoder->base.crtc)
7886 continue;
7887
7888 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7889 WARN(active && pipe != tracked_pipe,
7890 "active encoder's pipe doesn't match"
7891 "(expected %i, found %i)\n",
7892 tracked_pipe, pipe);
7893
7894 }
7895
7896 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7897 base.head) {
7898 bool enabled = false;
7899 bool active = false;
7900
7901 DRM_DEBUG_KMS("[CRTC:%d]\n",
7902 crtc->base.base.id);
7903
7904 WARN(crtc->active && !crtc->base.enabled,
7905 "active crtc, but not enabled in sw tracking\n");
7906
7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7908 base.head) {
7909 if (encoder->base.crtc != &crtc->base)
7910 continue;
7911 enabled = true;
7912 if (encoder->connectors_active)
7913 active = true;
7914 }
7915 WARN(active != crtc->active,
7916 "crtc's computed active state doesn't match tracked active state "
7917 "(expected %i, found %i)\n", active, crtc->active);
7918 WARN(enabled != crtc->base.enabled,
7919 "crtc's computed enabled state doesn't match tracked enabled state "
7920 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7921
7922 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7923 }
7924 }
7925
intel_set_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,int x,int y,struct drm_framebuffer * fb)7926 bool intel_set_mode(struct drm_crtc *crtc,
7927 struct drm_display_mode *mode,
7928 int x, int y, struct drm_framebuffer *fb)
7929 {
7930 struct drm_device *dev = crtc->dev;
7931 drm_i915_private_t *dev_priv = dev->dev_private;
7932 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7933 struct intel_crtc *intel_crtc;
7934 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7935 bool ret = true;
7936
7937 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7938 &prepare_pipes, &disable_pipes);
7939
7940 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7941 modeset_pipes, prepare_pipes, disable_pipes);
7942
7943 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7944 intel_crtc_disable(&intel_crtc->base);
7945
7946 saved_hwmode = crtc->hwmode;
7947 saved_mode = crtc->mode;
7948
7949 /* Hack: Because we don't (yet) support global modeset on multiple
7950 * crtcs, we don't keep track of the new mode for more than one crtc.
7951 * Hence simply check whether any bit is set in modeset_pipes in all the
7952 * pieces of code that are not yet converted to deal with mutliple crtcs
7953 * changing their mode at the same time. */
7954 adjusted_mode = NULL;
7955 if (modeset_pipes) {
7956 int err = intel_modeset_adjusted_mode(crtc, mode, &adjusted_mode);
7957 if (err) {
7958 return false;
7959 }
7960 }
7961
7962 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7963 if (intel_crtc->base.enabled)
7964 dev_priv->display.crtc_disable(&intel_crtc->base);
7965 }
7966
7967 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7968 * to set it here already despite that we pass it down the callchain.
7969 */
7970 if (modeset_pipes)
7971 crtc->mode = *mode;
7972
7973 /* Only after disabling all output pipelines that will be changed can we
7974 * update the output configuration. */
7975 intel_modeset_update_state(dev, prepare_pipes);
7976
7977 if (dev_priv->display.modeset_global_resources)
7978 dev_priv->display.modeset_global_resources(dev);
7979
7980 /* Set up the DPLL and any encoders state that needs to adjust or depend
7981 * on the DPLL.
7982 */
7983 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7984 ret = !intel_crtc_mode_set(&intel_crtc->base,
7985 mode, adjusted_mode,
7986 x, y, fb);
7987 if (!ret)
7988 goto done;
7989 }
7990
7991 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7992 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7993 dev_priv->display.crtc_enable(&intel_crtc->base);
7994
7995 if (modeset_pipes) {
7996 /* Store real post-adjustment hardware mode. */
7997 crtc->hwmode = *adjusted_mode;
7998
7999 /* Calculate and store various constants which
8000 * are later needed by vblank and swap-completion
8001 * timestamping. They are derived from true hwmode.
8002 */
8003 drm_calc_timestamping_constants(crtc);
8004 }
8005
8006 /* FIXME: add subpixel order */
8007 done:
8008 drm_mode_destroy(dev, adjusted_mode);
8009 if (!ret && crtc->enabled) {
8010 crtc->hwmode = saved_hwmode;
8011 crtc->mode = saved_mode;
8012 } else {
8013 intel_modeset_check_state(dev);
8014 }
8015
8016 return ret;
8017 }
8018
8019 #undef for_each_intel_crtc_masked
8020
intel_set_config_free(struct intel_set_config * config)8021 static void intel_set_config_free(struct intel_set_config *config)
8022 {
8023 if (!config)
8024 return;
8025
8026 free(config->save_connector_encoders, DRM_MEM_KMS);
8027 free(config->save_encoder_crtcs, DRM_MEM_KMS);
8028 free(config, DRM_MEM_KMS);
8029 }
8030
intel_set_config_save_state(struct drm_device * dev,struct intel_set_config * config)8031 static int intel_set_config_save_state(struct drm_device *dev,
8032 struct intel_set_config *config)
8033 {
8034 struct drm_encoder *encoder;
8035 struct drm_connector *connector;
8036 int count;
8037
8038 config->save_encoder_crtcs =
8039 malloc(dev->mode_config.num_encoder *
8040 sizeof(struct drm_crtc *), DRM_MEM_KMS, M_NOWAIT | M_ZERO);
8041 if (!config->save_encoder_crtcs)
8042 return -ENOMEM;
8043
8044 config->save_connector_encoders =
8045 malloc(dev->mode_config.num_connector *
8046 sizeof(struct drm_encoder *), DRM_MEM_KMS, M_NOWAIT | M_ZERO);
8047 if (!config->save_connector_encoders)
8048 return -ENOMEM;
8049
8050 /* Copy data. Note that driver private data is not affected.
8051 * Should anything bad happen only the expected state is
8052 * restored, not the drivers personal bookkeeping.
8053 */
8054 count = 0;
8055 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8056 config->save_encoder_crtcs[count++] = encoder->crtc;
8057 }
8058
8059 count = 0;
8060 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8061 config->save_connector_encoders[count++] = connector->encoder;
8062 }
8063
8064 return 0;
8065 }
8066
intel_set_config_restore_state(struct drm_device * dev,struct intel_set_config * config)8067 static void intel_set_config_restore_state(struct drm_device *dev,
8068 struct intel_set_config *config)
8069 {
8070 struct intel_encoder *encoder;
8071 struct intel_connector *connector;
8072 int count;
8073
8074 count = 0;
8075 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8076 encoder->new_crtc =
8077 to_intel_crtc(config->save_encoder_crtcs[count++]);
8078 }
8079
8080 count = 0;
8081 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8082 connector->new_encoder =
8083 to_intel_encoder(config->save_connector_encoders[count++]);
8084 }
8085 }
8086
8087 static void
intel_set_config_compute_mode_changes(struct drm_mode_set * set,struct intel_set_config * config)8088 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8089 struct intel_set_config *config)
8090 {
8091
8092 /* We should be able to check here if the fb has the same properties
8093 * and then just flip_or_move it */
8094 if (set->crtc->fb != set->fb) {
8095 /* If we have no fb then treat it as a full mode set */
8096 if (set->crtc->fb == NULL) {
8097 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8098 config->mode_changed = true;
8099 } else if (set->fb == NULL) {
8100 config->mode_changed = true;
8101 } else if (set->fb->depth != set->crtc->fb->depth) {
8102 config->mode_changed = true;
8103 } else if (set->fb->bits_per_pixel !=
8104 set->crtc->fb->bits_per_pixel) {
8105 config->mode_changed = true;
8106 } else
8107 config->fb_changed = true;
8108 }
8109
8110 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8111 config->fb_changed = true;
8112
8113 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8114 DRM_DEBUG_KMS("modes are different, full mode set\n");
8115 drm_mode_debug_printmodeline(&set->crtc->mode);
8116 drm_mode_debug_printmodeline(set->mode);
8117 config->mode_changed = true;
8118 }
8119 }
8120
8121 static int
intel_modeset_stage_output_state(struct drm_device * dev,struct drm_mode_set * set,struct intel_set_config * config)8122 intel_modeset_stage_output_state(struct drm_device *dev,
8123 struct drm_mode_set *set,
8124 struct intel_set_config *config)
8125 {
8126 struct drm_crtc *new_crtc;
8127 struct intel_connector *connector;
8128 struct intel_encoder *encoder;
8129 int count, ro;
8130
8131 /* The upper layers ensure that we either disabl a crtc or have a list
8132 * of connectors. For paranoia, double-check this. */
8133 WARN_ON(!set->fb && (set->num_connectors != 0));
8134 WARN_ON(set->fb && (set->num_connectors == 0));
8135
8136 count = 0;
8137 list_for_each_entry(connector, &dev->mode_config.connector_list,
8138 base.head) {
8139 /* Otherwise traverse passed in connector list and get encoders
8140 * for them. */
8141 for (ro = 0; ro < set->num_connectors; ro++) {
8142 if (set->connectors[ro] == &connector->base) {
8143 connector->new_encoder = connector->encoder;
8144 break;
8145 }
8146 }
8147
8148 /* If we disable the crtc, disable all its connectors. Also, if
8149 * the connector is on the changing crtc but not on the new
8150 * connector list, disable it. */
8151 if ((!set->fb || ro == set->num_connectors) &&
8152 connector->base.encoder &&
8153 connector->base.encoder->crtc == set->crtc) {
8154 connector->new_encoder = NULL;
8155
8156 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8157 connector->base.base.id,
8158 drm_get_connector_name(&connector->base));
8159 }
8160
8161
8162 if (&connector->new_encoder->base != connector->base.encoder) {
8163 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8164 config->mode_changed = true;
8165 }
8166 }
8167 /* connector->new_encoder is now updated for all connectors. */
8168
8169 /* Update crtc of enabled connectors. */
8170 count = 0;
8171 list_for_each_entry(connector, &dev->mode_config.connector_list,
8172 base.head) {
8173 if (!connector->new_encoder)
8174 continue;
8175
8176 new_crtc = connector->new_encoder->base.crtc;
8177
8178 for (ro = 0; ro < set->num_connectors; ro++) {
8179 if (set->connectors[ro] == &connector->base)
8180 new_crtc = set->crtc;
8181 }
8182
8183 /* Make sure the new CRTC will work with the encoder */
8184 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8185 new_crtc)) {
8186 return -EINVAL;
8187 }
8188 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8189
8190 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8191 connector->base.base.id,
8192 drm_get_connector_name(&connector->base),
8193 new_crtc->base.id);
8194 }
8195
8196 /* Check for any encoders that needs to be disabled. */
8197 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8198 base.head) {
8199 list_for_each_entry(connector,
8200 &dev->mode_config.connector_list,
8201 base.head) {
8202 if (connector->new_encoder == encoder) {
8203 WARN_ON(!connector->new_encoder->new_crtc);
8204
8205 goto next_encoder;
8206 }
8207 }
8208 encoder->new_crtc = NULL;
8209 next_encoder:
8210 /* Only now check for crtc changes so we don't miss encoders
8211 * that will be disabled. */
8212 if (&encoder->new_crtc->base != encoder->base.crtc) {
8213 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8214 config->mode_changed = true;
8215 }
8216 }
8217 /* Now we've also updated encoder->new_crtc for all encoders. */
8218
8219 return 0;
8220 }
8221
intel_crtc_set_config(struct drm_mode_set * set)8222 static int intel_crtc_set_config(struct drm_mode_set *set)
8223 {
8224 struct drm_device *dev;
8225 struct drm_mode_set save_set;
8226 struct intel_set_config *config;
8227 int ret;
8228
8229 BUG_ON(!set);
8230 BUG_ON(!set->crtc);
8231 BUG_ON(!set->crtc->helper_private);
8232
8233 if (!set->mode)
8234 set->fb = NULL;
8235
8236 /* The fb helper likes to play gross jokes with ->mode_set_config.
8237 * Unfortunately the crtc helper doesn't do much at all for this case,
8238 * so we have to cope with this madness until the fb helper is fixed up. */
8239 if (set->fb && set->num_connectors == 0)
8240 return 0;
8241
8242 if (set->fb) {
8243 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8244 set->crtc->base.id, set->fb->base.id,
8245 (int)set->num_connectors, set->x, set->y);
8246 } else {
8247 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8248 }
8249
8250 dev = set->crtc->dev;
8251
8252 ret = -ENOMEM;
8253 config = malloc(sizeof(*config), DRM_MEM_KMS, M_NOWAIT | M_ZERO);
8254 if (!config)
8255 goto out_config;
8256
8257 ret = intel_set_config_save_state(dev, config);
8258 if (ret)
8259 goto out_config;
8260
8261 save_set.crtc = set->crtc;
8262 save_set.mode = &set->crtc->mode;
8263 save_set.x = set->crtc->x;
8264 save_set.y = set->crtc->y;
8265 save_set.fb = set->crtc->fb;
8266
8267 /* Compute whether we need a full modeset, only an fb base update or no
8268 * change at all. In the future we might also check whether only the
8269 * mode changed, e.g. for LVDS where we only change the panel fitter in
8270 * such cases. */
8271 intel_set_config_compute_mode_changes(set, config);
8272
8273 ret = intel_modeset_stage_output_state(dev, set, config);
8274 if (ret)
8275 goto fail;
8276
8277 if (config->mode_changed) {
8278 if (set->mode) {
8279 DRM_DEBUG_KMS("attempting to set mode from"
8280 " userspace\n");
8281 drm_mode_debug_printmodeline(set->mode);
8282 }
8283
8284 if (!intel_set_mode(set->crtc, set->mode,
8285 set->x, set->y, set->fb)) {
8286 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8287 set->crtc->base.id);
8288 ret = -EINVAL;
8289 goto fail;
8290 }
8291 } else if (config->fb_changed) {
8292 ret = intel_pipe_set_base(set->crtc,
8293 set->x, set->y, set->fb);
8294 }
8295
8296 intel_set_config_free(config);
8297
8298 return 0;
8299
8300 fail:
8301 intel_set_config_restore_state(dev, config);
8302
8303 /* Try to restore the config */
8304 if (config->mode_changed &&
8305 !intel_set_mode(save_set.crtc, save_set.mode,
8306 save_set.x, save_set.y, save_set.fb))
8307 DRM_ERROR("failed to restore config after modeset failure\n");
8308
8309 out_config:
8310 intel_set_config_free(config);
8311 return ret;
8312 }
8313
8314 static const struct drm_crtc_funcs intel_crtc_funcs = {
8315 .cursor_set = intel_crtc_cursor_set,
8316 .cursor_move = intel_crtc_cursor_move,
8317 .gamma_set = intel_crtc_gamma_set,
8318 .set_config = intel_crtc_set_config,
8319 .destroy = intel_crtc_destroy,
8320 .page_flip = intel_crtc_page_flip,
8321 };
8322
intel_cpu_pll_init(struct drm_device * dev)8323 static void intel_cpu_pll_init(struct drm_device *dev)
8324 {
8325 if (IS_HASWELL(dev))
8326 intel_ddi_pll_init(dev);
8327 }
8328
intel_pch_pll_init(struct drm_device * dev)8329 static void intel_pch_pll_init(struct drm_device *dev)
8330 {
8331 drm_i915_private_t *dev_priv = dev->dev_private;
8332 int i;
8333
8334 if (dev_priv->num_pch_pll == 0) {
8335 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8336 return;
8337 }
8338
8339 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8340 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8341 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8342 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8343 }
8344 }
8345
intel_crtc_init(struct drm_device * dev,int pipe)8346 static void intel_crtc_init(struct drm_device *dev, int pipe)
8347 {
8348 drm_i915_private_t *dev_priv = dev->dev_private;
8349 struct intel_crtc *intel_crtc;
8350 int i;
8351
8352 intel_crtc = malloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), DRM_MEM_KMS, M_WAITOK | M_ZERO);
8353 if (intel_crtc == NULL)
8354 return;
8355
8356 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8357
8358 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8359 for (i = 0; i < 256; i++) {
8360 intel_crtc->lut_r[i] = i;
8361 intel_crtc->lut_g[i] = i;
8362 intel_crtc->lut_b[i] = i;
8363 }
8364
8365 /* Swap pipes & planes for FBC on pre-965 */
8366 intel_crtc->pipe = pipe;
8367 intel_crtc->plane = pipe;
8368 intel_crtc->cpu_transcoder = pipe;
8369 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8370 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8371 intel_crtc->plane = !pipe;
8372 }
8373
8374 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8375 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8376 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8377 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8378
8379 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8380
8381 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8382 }
8383
intel_get_pipe_from_crtc_id(struct drm_device * dev,void * data,struct drm_file * file)8384 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8385 struct drm_file *file)
8386 {
8387 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8388 struct drm_mode_object *drmmode_obj;
8389 struct intel_crtc *crtc;
8390
8391 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8392 return -ENODEV;
8393
8394 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8395 DRM_MODE_OBJECT_CRTC);
8396
8397 if (!drmmode_obj) {
8398 DRM_ERROR("no such CRTC id\n");
8399 return -EINVAL;
8400 }
8401
8402 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8403 pipe_from_crtc_id->pipe = crtc->pipe;
8404
8405 return 0;
8406 }
8407
intel_encoder_clones(struct intel_encoder * encoder)8408 static int intel_encoder_clones(struct intel_encoder *encoder)
8409 {
8410 struct drm_device *dev = encoder->base.dev;
8411 struct intel_encoder *source_encoder;
8412 int index_mask = 0;
8413 int entry = 0;
8414
8415 list_for_each_entry(source_encoder,
8416 &dev->mode_config.encoder_list, base.head) {
8417
8418 if (encoder == source_encoder)
8419 index_mask |= (1 << entry);
8420
8421 /* Intel hw has only one MUX where enocoders could be cloned. */
8422 if (encoder->cloneable && source_encoder->cloneable)
8423 index_mask |= (1 << entry);
8424
8425 entry++;
8426 }
8427
8428 return index_mask;
8429 }
8430
has_edp_a(struct drm_device * dev)8431 static bool has_edp_a(struct drm_device *dev)
8432 {
8433 struct drm_i915_private *dev_priv = dev->dev_private;
8434
8435 if (!IS_MOBILE(dev))
8436 return false;
8437
8438 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8439 return false;
8440
8441 if (IS_GEN5(dev) &&
8442 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8443 return false;
8444
8445 return true;
8446 }
8447
intel_setup_outputs(struct drm_device * dev)8448 static void intel_setup_outputs(struct drm_device *dev)
8449 {
8450 struct drm_i915_private *dev_priv = dev->dev_private;
8451 struct intel_encoder *encoder;
8452 bool dpd_is_edp = false;
8453 bool has_lvds;
8454
8455 has_lvds = intel_lvds_init(dev);
8456 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8457 /* disable the panel fitter on everything but LVDS */
8458 I915_WRITE(PFIT_CONTROL, 0);
8459 }
8460
8461 if (!(IS_HASWELL(dev) &&
8462 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8463 intel_crt_init(dev);
8464
8465 if (IS_HASWELL(dev)) {
8466 int found;
8467
8468 /* Haswell uses DDI functions to detect digital outputs */
8469 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8470 /* DDI A only supports eDP */
8471 if (found)
8472 intel_ddi_init(dev, PORT_A);
8473
8474 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8475 * register */
8476 found = I915_READ(SFUSE_STRAP);
8477
8478 if (found & SFUSE_STRAP_DDIB_DETECTED)
8479 intel_ddi_init(dev, PORT_B);
8480 if (found & SFUSE_STRAP_DDIC_DETECTED)
8481 intel_ddi_init(dev, PORT_C);
8482 if (found & SFUSE_STRAP_DDID_DETECTED)
8483 intel_ddi_init(dev, PORT_D);
8484 } else if (HAS_PCH_SPLIT(dev)) {
8485 int found;
8486 dpd_is_edp = intel_dpd_is_edp(dev);
8487
8488 if (has_edp_a(dev))
8489 intel_dp_init(dev, DP_A, PORT_A);
8490
8491 if (I915_READ(HDMIB) & PORT_DETECTED) {
8492 /* PCH SDVOB multiplex with HDMIB */
8493 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8494 if (!found)
8495 intel_hdmi_init(dev, HDMIB, PORT_B);
8496 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8497 intel_dp_init(dev, PCH_DP_B, PORT_B);
8498 }
8499
8500 if (I915_READ(HDMIC) & PORT_DETECTED)
8501 intel_hdmi_init(dev, HDMIC, PORT_C);
8502
8503 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8504 intel_hdmi_init(dev, HDMID, PORT_D);
8505
8506 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8507 intel_dp_init(dev, PCH_DP_C, PORT_C);
8508
8509 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8510 intel_dp_init(dev, PCH_DP_D, PORT_D);
8511 } else if (IS_VALLEYVIEW(dev)) {
8512 int found;
8513
8514 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8515 if (I915_READ(DP_C) & DP_DETECTED)
8516 intel_dp_init(dev, DP_C, PORT_C);
8517
8518 if (I915_READ(SDVOB) & PORT_DETECTED) {
8519 /* SDVOB multiplex with HDMIB */
8520 found = intel_sdvo_init(dev, SDVOB, true);
8521 if (!found)
8522 intel_hdmi_init(dev, SDVOB, PORT_B);
8523 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8524 intel_dp_init(dev, DP_B, PORT_B);
8525 }
8526
8527 if (I915_READ(SDVOC) & PORT_DETECTED)
8528 intel_hdmi_init(dev, SDVOC, PORT_C);
8529
8530 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8531 bool found = false;
8532
8533 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8534 DRM_DEBUG_KMS("probing SDVOB\n");
8535 found = intel_sdvo_init(dev, SDVOB, true);
8536 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8537 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8538 intel_hdmi_init(dev, SDVOB, PORT_B);
8539 }
8540
8541 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8542 DRM_DEBUG_KMS("probing DP_B\n");
8543 intel_dp_init(dev, DP_B, PORT_B);
8544 }
8545 }
8546
8547 /* Before G4X SDVOC doesn't have its own detect register */
8548
8549 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8550 DRM_DEBUG_KMS("probing SDVOC\n");
8551 found = intel_sdvo_init(dev, SDVOC, false);
8552 }
8553
8554 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8555
8556 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8557 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8558 intel_hdmi_init(dev, SDVOC, PORT_C);
8559 }
8560 if (SUPPORTS_INTEGRATED_DP(dev)) {
8561 DRM_DEBUG_KMS("probing DP_C\n");
8562 intel_dp_init(dev, DP_C, PORT_C);
8563 }
8564 }
8565
8566 if (SUPPORTS_INTEGRATED_DP(dev) &&
8567 (I915_READ(DP_D) & DP_DETECTED)) {
8568 DRM_DEBUG_KMS("probing DP_D\n");
8569 intel_dp_init(dev, DP_D, PORT_D);
8570 }
8571 } else if (IS_GEN2(dev))
8572 intel_dvo_init(dev);
8573
8574 if (SUPPORTS_TV(dev))
8575 intel_tv_init(dev);
8576
8577 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8578 encoder->base.possible_crtcs = encoder->crtc_mask;
8579 encoder->base.possible_clones =
8580 intel_encoder_clones(encoder);
8581 }
8582
8583 intel_init_pch_refclk(dev);
8584
8585 drm_helper_move_panel_connectors_to_head(dev);
8586 }
8587
intel_user_framebuffer_destroy(struct drm_framebuffer * fb)8588 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8589 {
8590 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8591
8592 drm_framebuffer_cleanup(fb);
8593 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8594
8595 free(intel_fb, DRM_MEM_KMS);
8596 }
8597
intel_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file,unsigned int * handle)8598 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8599 struct drm_file *file,
8600 unsigned int *handle)
8601 {
8602 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8603 struct drm_i915_gem_object *obj = intel_fb->obj;
8604
8605 return drm_gem_handle_create(file, &obj->base, handle);
8606 }
8607
8608 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8609 .destroy = intel_user_framebuffer_destroy,
8610 .create_handle = intel_user_framebuffer_create_handle,
8611 };
8612
intel_framebuffer_init(struct drm_device * dev,struct intel_framebuffer * intel_fb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj)8613 int intel_framebuffer_init(struct drm_device *dev,
8614 struct intel_framebuffer *intel_fb,
8615 struct drm_mode_fb_cmd2 *mode_cmd,
8616 struct drm_i915_gem_object *obj)
8617 {
8618 int ret;
8619
8620 if (obj->tiling_mode == I915_TILING_Y) {
8621 DRM_DEBUG("hardware does not support tiling Y\n");
8622 return -EINVAL;
8623 }
8624
8625 if (mode_cmd->pitches[0] & 63) {
8626 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8627 mode_cmd->pitches[0]);
8628 return -EINVAL;
8629 }
8630
8631 /* FIXME <= Gen4 stride limits are bit unclear */
8632 if (mode_cmd->pitches[0] > 32768) {
8633 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8634 mode_cmd->pitches[0]);
8635 return -EINVAL;
8636 }
8637
8638 if (obj->tiling_mode != I915_TILING_NONE &&
8639 mode_cmd->pitches[0] != obj->stride) {
8640 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8641 mode_cmd->pitches[0], obj->stride);
8642 return -EINVAL;
8643 }
8644
8645 /* Reject formats not supported by any plane early. */
8646 switch (mode_cmd->pixel_format) {
8647 case DRM_FORMAT_C8:
8648 case DRM_FORMAT_RGB565:
8649 case DRM_FORMAT_XRGB8888:
8650 case DRM_FORMAT_ARGB8888:
8651 break;
8652 case DRM_FORMAT_XRGB1555:
8653 case DRM_FORMAT_ARGB1555:
8654 if (INTEL_INFO(dev)->gen > 3) {
8655 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8656 return -EINVAL;
8657 }
8658 break;
8659 case DRM_FORMAT_XBGR8888:
8660 case DRM_FORMAT_ABGR8888:
8661 case DRM_FORMAT_XRGB2101010:
8662 case DRM_FORMAT_ARGB2101010:
8663 case DRM_FORMAT_XBGR2101010:
8664 case DRM_FORMAT_ABGR2101010:
8665 if (INTEL_INFO(dev)->gen < 4) {
8666 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8667 return -EINVAL;
8668 }
8669 break;
8670 case DRM_FORMAT_YUYV:
8671 case DRM_FORMAT_UYVY:
8672 case DRM_FORMAT_YVYU:
8673 case DRM_FORMAT_VYUY:
8674 if (INTEL_INFO(dev)->gen < 5) {
8675 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8676 return -EINVAL;
8677 }
8678 break;
8679 default:
8680 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8681 return -EINVAL;
8682 }
8683
8684 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8685 if (mode_cmd->offsets[0] != 0)
8686 return -EINVAL;
8687
8688 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8689 if (ret) {
8690 DRM_ERROR("framebuffer init failed %d\n", ret);
8691 return ret;
8692 }
8693
8694 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8695 intel_fb->obj = obj;
8696 return 0;
8697 }
8698
8699 static int
intel_user_framebuffer_create(struct drm_device * dev,struct drm_file * filp,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_framebuffer ** res)8700 intel_user_framebuffer_create(struct drm_device *dev,
8701 struct drm_file *filp,
8702 struct drm_mode_fb_cmd2 *mode_cmd,
8703 struct drm_framebuffer **res)
8704 {
8705 struct drm_i915_gem_object *obj;
8706
8707 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8708 mode_cmd->handles[0]));
8709 if (&obj->base == NULL)
8710 return -ENOENT;
8711
8712 return intel_framebuffer_create(dev, mode_cmd, obj, res);
8713 }
8714
8715 static const struct drm_mode_config_funcs intel_mode_funcs = {
8716 .fb_create = intel_user_framebuffer_create,
8717 .output_poll_changed = intel_fb_output_poll_changed,
8718 };
8719
8720 /* Set up chip specific display functions */
intel_init_display(struct drm_device * dev)8721 static void intel_init_display(struct drm_device *dev)
8722 {
8723 struct drm_i915_private *dev_priv = dev->dev_private;
8724
8725 /* We always want a DPMS function */
8726 if (IS_HASWELL(dev)) {
8727 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8728 dev_priv->display.crtc_enable = haswell_crtc_enable;
8729 dev_priv->display.crtc_disable = haswell_crtc_disable;
8730 dev_priv->display.off = haswell_crtc_off;
8731 dev_priv->display.update_plane = ironlake_update_plane;
8732 } else if (HAS_PCH_SPLIT(dev)) {
8733 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8734 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8735 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8736 dev_priv->display.off = ironlake_crtc_off;
8737 dev_priv->display.update_plane = ironlake_update_plane;
8738 } else {
8739 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8740 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8741 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8742 dev_priv->display.off = i9xx_crtc_off;
8743 dev_priv->display.update_plane = i9xx_update_plane;
8744 }
8745
8746 /* Returns the core display clock speed */
8747 if (IS_VALLEYVIEW(dev))
8748 dev_priv->display.get_display_clock_speed =
8749 valleyview_get_display_clock_speed;
8750 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8751 dev_priv->display.get_display_clock_speed =
8752 i945_get_display_clock_speed;
8753 else if (IS_I915G(dev))
8754 dev_priv->display.get_display_clock_speed =
8755 i915_get_display_clock_speed;
8756 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8757 dev_priv->display.get_display_clock_speed =
8758 i9xx_misc_get_display_clock_speed;
8759 else if (IS_I915GM(dev))
8760 dev_priv->display.get_display_clock_speed =
8761 i915gm_get_display_clock_speed;
8762 else if (IS_I865G(dev))
8763 dev_priv->display.get_display_clock_speed =
8764 i865_get_display_clock_speed;
8765 else if (IS_I85X(dev))
8766 dev_priv->display.get_display_clock_speed =
8767 i855_get_display_clock_speed;
8768 else /* 852, 830 */
8769 dev_priv->display.get_display_clock_speed =
8770 i830_get_display_clock_speed;
8771
8772 if (HAS_PCH_SPLIT(dev)) {
8773 if (IS_GEN5(dev)) {
8774 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8775 dev_priv->display.write_eld = ironlake_write_eld;
8776 } else if (IS_GEN6(dev)) {
8777 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8778 dev_priv->display.write_eld = ironlake_write_eld;
8779 } else if (IS_IVYBRIDGE(dev)) {
8780 /* FIXME: detect B0+ stepping and use auto training */
8781 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8782 dev_priv->display.write_eld = ironlake_write_eld;
8783 dev_priv->display.modeset_global_resources =
8784 ivb_modeset_global_resources;
8785 } else if (IS_HASWELL(dev)) {
8786 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8787 dev_priv->display.write_eld = haswell_write_eld;
8788 } else
8789 dev_priv->display.update_wm = NULL;
8790 } else if (IS_G4X(dev)) {
8791 dev_priv->display.write_eld = g4x_write_eld;
8792 }
8793
8794 /* Default just returns -ENODEV to indicate unsupported */
8795 dev_priv->display.queue_flip = intel_default_queue_flip;
8796
8797 switch (INTEL_INFO(dev)->gen) {
8798 case 2:
8799 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8800 break;
8801
8802 case 3:
8803 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8804 break;
8805
8806 case 4:
8807 case 5:
8808 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8809 break;
8810
8811 case 6:
8812 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8813 break;
8814 case 7:
8815 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8816 break;
8817 }
8818 }
8819
8820 /*
8821 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8822 * resume, or other times. This quirk makes sure that's the case for
8823 * affected systems.
8824 */
quirk_pipea_force(struct drm_device * dev)8825 static void quirk_pipea_force(struct drm_device *dev)
8826 {
8827 struct drm_i915_private *dev_priv = dev->dev_private;
8828
8829 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8830 DRM_INFO("applying pipe a force quirk\n");
8831 }
8832
8833 /*
8834 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8835 */
quirk_ssc_force_disable(struct drm_device * dev)8836 static void quirk_ssc_force_disable(struct drm_device *dev)
8837 {
8838 struct drm_i915_private *dev_priv = dev->dev_private;
8839 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8840 DRM_INFO("applying lvds SSC disable quirk\n");
8841 }
8842
8843 /*
8844 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8845 * brightness value
8846 */
quirk_invert_brightness(struct drm_device * dev)8847 static void quirk_invert_brightness(struct drm_device *dev)
8848 {
8849 struct drm_i915_private *dev_priv = dev->dev_private;
8850 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8851 DRM_INFO("applying inverted panel brightness quirk\n");
8852 }
8853
8854 struct intel_quirk {
8855 int device;
8856 int subsystem_vendor;
8857 int subsystem_device;
8858 void (*hook)(struct drm_device *dev);
8859 };
8860
8861 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8862 struct intel_dmi_quirk {
8863 void (*hook)(struct drm_device *dev);
8864 const struct dmi_system_id (*dmi_id_list)[];
8865 };
8866
intel_dmi_reverse_brightness(const struct dmi_system_id * id)8867 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8868 {
8869 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8870 return 1;
8871 }
8872
8873 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8874 {
8875 .dmi_id_list =
8876 #if !defined(__clang__) && !__GNUC_PREREQ__(4, 3)
8877 /* gcc 4.2 needs an additional cast, to avoid a bogus
8878 * "initialization from incompatible pointer type" warning.
8879 * see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=36432
8880 */
8881 (const struct dmi_system_id (*)[])
8882 #endif
8883 &(const struct dmi_system_id[]) {
8884 {
8885 .callback = intel_dmi_reverse_brightness,
8886 .ident = "NCR Corporation",
8887 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8888 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8889 },
8890 },
8891 { } /* terminating entry */
8892 },
8893 .hook = quirk_invert_brightness,
8894 },
8895 };
8896
8897 #define PCI_ANY_ID (~0u)
8898
8899 static struct intel_quirk intel_quirks[] = {
8900 /* HP Mini needs pipe A force quirk (LP: #322104) */
8901 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8902
8903 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8904 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8905
8906 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8907 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8908
8909 /* 830/845 need to leave pipe A & dpll A up */
8910 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8911 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8912
8913 /* Lenovo U160 cannot use SSC on LVDS */
8914 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8915
8916 /* Sony Vaio Y cannot use SSC on LVDS */
8917 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8918
8919 /* Acer Aspire 5734Z must invert backlight brightness */
8920 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8921
8922 /* Acer Aspire 4736Z */
8923 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
8924
8925 /* Acer/eMachines G725 */
8926 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
8927
8928 /* Acer/eMachines e725 */
8929 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
8930
8931 /* Acer/Packard Bell NCL20 */
8932 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
8933 };
8934
intel_init_quirks(struct drm_device * dev)8935 static void intel_init_quirks(struct drm_device *dev)
8936 {
8937 int i;
8938
8939 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8940 struct intel_quirk *q = &intel_quirks[i];
8941
8942 if (pci_get_device(dev->dev) == q->device &&
8943 (pci_get_subvendor(dev->dev) == q->subsystem_vendor ||
8944 q->subsystem_vendor == PCI_ANY_ID) &&
8945 (pci_get_subdevice(dev->dev) == q->subsystem_device ||
8946 q->subsystem_device == PCI_ANY_ID))
8947 q->hook(dev);
8948 }
8949 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8950 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8951 intel_dmi_quirks[i].hook(dev);
8952 }
8953 }
8954
8955 /* Disable the VGA plane that we never use */
i915_disable_vga(struct drm_device * dev)8956 static void i915_disable_vga(struct drm_device *dev)
8957 {
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959 u8 sr1;
8960 u32 vga_reg;
8961
8962 if (HAS_PCH_SPLIT(dev))
8963 vga_reg = CPU_VGACNTRL;
8964 else
8965 vga_reg = VGACNTRL;
8966
8967 #ifdef FREEBSD_WIP
8968 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8969 #endif /* FREEBSD_WIP */
8970 outb(VGA_SR_INDEX, SR01);
8971 sr1 = inb(VGA_SR_DATA);
8972 outb(VGA_SR_DATA, sr1 | 1<<5);
8973 #ifdef FREEBSD_WIP
8974 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8975 #endif /* FREEBSD_WIP */
8976 udelay(300);
8977
8978 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8979 POSTING_READ(vga_reg);
8980 }
8981
intel_modeset_init_hw(struct drm_device * dev)8982 void intel_modeset_init_hw(struct drm_device *dev)
8983 {
8984 /* We attempt to init the necessary power wells early in the initialization
8985 * time, so the subsystems that expect power to be enabled can work.
8986 */
8987 intel_init_power_wells(dev);
8988
8989 intel_prepare_ddi(dev);
8990
8991 intel_init_clock_gating(dev);
8992
8993 DRM_LOCK(dev);
8994 intel_enable_gt_powersave(dev);
8995 DRM_UNLOCK(dev);
8996 }
8997
intel_modeset_init(struct drm_device * dev)8998 void intel_modeset_init(struct drm_device *dev)
8999 {
9000 struct drm_i915_private *dev_priv = dev->dev_private;
9001 int i, ret;
9002
9003 drm_mode_config_init(dev);
9004
9005 dev->mode_config.min_width = 0;
9006 dev->mode_config.min_height = 0;
9007
9008 dev->mode_config.preferred_depth = 24;
9009 dev->mode_config.prefer_shadow = 1;
9010
9011 dev->mode_config.funcs = &intel_mode_funcs;
9012
9013 intel_init_quirks(dev);
9014
9015 intel_init_pm(dev);
9016
9017 intel_init_display(dev);
9018
9019 if (IS_GEN2(dev)) {
9020 dev->mode_config.max_width = 2048;
9021 dev->mode_config.max_height = 2048;
9022 } else if (IS_GEN3(dev)) {
9023 dev->mode_config.max_width = 4096;
9024 dev->mode_config.max_height = 4096;
9025 } else {
9026 dev->mode_config.max_width = 8192;
9027 dev->mode_config.max_height = 8192;
9028 }
9029 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
9030
9031 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9032 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9033
9034 for (i = 0; i < dev_priv->num_pipe; i++) {
9035 intel_crtc_init(dev, i);
9036 ret = intel_plane_init(dev, i);
9037 if (ret)
9038 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
9039 }
9040
9041 intel_cpu_pll_init(dev);
9042 intel_pch_pll_init(dev);
9043
9044 /* Just disable it once at startup */
9045 i915_disable_vga(dev);
9046 intel_setup_outputs(dev);
9047 }
9048
9049 static void
intel_connector_break_all_links(struct intel_connector * connector)9050 intel_connector_break_all_links(struct intel_connector *connector)
9051 {
9052 connector->base.dpms = DRM_MODE_DPMS_OFF;
9053 connector->base.encoder = NULL;
9054 connector->encoder->connectors_active = false;
9055 connector->encoder->base.crtc = NULL;
9056 }
9057
intel_enable_pipe_a(struct drm_device * dev)9058 static void intel_enable_pipe_a(struct drm_device *dev)
9059 {
9060 struct intel_connector *connector;
9061 struct drm_connector *crt = NULL;
9062 struct intel_load_detect_pipe load_detect_temp;
9063
9064 /* We can't just switch on the pipe A, we need to set things up with a
9065 * proper mode and output configuration. As a gross hack, enable pipe A
9066 * by enabling the load detect pipe once. */
9067 list_for_each_entry(connector,
9068 &dev->mode_config.connector_list,
9069 base.head) {
9070 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9071 crt = &connector->base;
9072 break;
9073 }
9074 }
9075
9076 if (!crt)
9077 return;
9078
9079 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9080 intel_release_load_detect_pipe(crt, &load_detect_temp);
9081
9082
9083 }
9084
9085 static bool
intel_check_plane_mapping(struct intel_crtc * crtc)9086 intel_check_plane_mapping(struct intel_crtc *crtc)
9087 {
9088 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
9089 u32 reg, val;
9090
9091 if (dev_priv->num_pipe == 1)
9092 return true;
9093
9094 reg = DSPCNTR(!crtc->plane);
9095 val = I915_READ(reg);
9096
9097 if ((val & DISPLAY_PLANE_ENABLE) &&
9098 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9099 return false;
9100
9101 return true;
9102 }
9103
intel_sanitize_crtc(struct intel_crtc * crtc)9104 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9105 {
9106 struct drm_device *dev = crtc->base.dev;
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108 u32 reg;
9109
9110 /* Clear any frame start delays used for debugging left by the BIOS */
9111 reg = PIPECONF(crtc->cpu_transcoder);
9112 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9113
9114 /* We need to sanitize the plane -> pipe mapping first because this will
9115 * disable the crtc (and hence change the state) if it is wrong. Note
9116 * that gen4+ has a fixed plane -> pipe mapping. */
9117 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9118 struct intel_connector *connector;
9119 bool plane;
9120
9121 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9122 crtc->base.base.id);
9123
9124 /* Pipe has the wrong plane attached and the plane is active.
9125 * Temporarily change the plane mapping and disable everything
9126 * ... */
9127 plane = crtc->plane;
9128 crtc->plane = !plane;
9129 dev_priv->display.crtc_disable(&crtc->base);
9130 crtc->plane = plane;
9131
9132 /* ... and break all links. */
9133 list_for_each_entry(connector, &dev->mode_config.connector_list,
9134 base.head) {
9135 if (connector->encoder->base.crtc != &crtc->base)
9136 continue;
9137
9138 intel_connector_break_all_links(connector);
9139 }
9140
9141 WARN_ON(crtc->active);
9142 crtc->base.enabled = false;
9143 }
9144
9145 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9146 crtc->pipe == PIPE_A && !crtc->active) {
9147 /* BIOS forgot to enable pipe A, this mostly happens after
9148 * resume. Force-enable the pipe to fix this, the update_dpms
9149 * call below we restore the pipe to the right state, but leave
9150 * the required bits on. */
9151 intel_enable_pipe_a(dev);
9152 }
9153
9154 /* Adjust the state of the output pipe according to whether we
9155 * have active connectors/encoders. */
9156 intel_crtc_update_dpms(&crtc->base);
9157
9158 if (crtc->active != crtc->base.enabled) {
9159 struct intel_encoder *encoder;
9160
9161 /* This can happen either due to bugs in the get_hw_state
9162 * functions or because the pipe is force-enabled due to the
9163 * pipe A quirk. */
9164 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9165 crtc->base.base.id,
9166 crtc->base.enabled ? "enabled" : "disabled",
9167 crtc->active ? "enabled" : "disabled");
9168
9169 crtc->base.enabled = crtc->active;
9170
9171 /* Because we only establish the connector -> encoder ->
9172 * crtc links if something is active, this means the
9173 * crtc is now deactivated. Break the links. connector
9174 * -> encoder links are only establish when things are
9175 * actually up, hence no need to break them. */
9176 WARN_ON(crtc->active);
9177
9178 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9179 WARN_ON(encoder->connectors_active);
9180 encoder->base.crtc = NULL;
9181 }
9182 }
9183 }
9184
intel_sanitize_encoder(struct intel_encoder * encoder)9185 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9186 {
9187 struct intel_connector *connector;
9188 struct drm_device *dev = encoder->base.dev;
9189
9190 /* We need to check both for a crtc link (meaning that the
9191 * encoder is active and trying to read from a pipe) and the
9192 * pipe itself being active. */
9193 bool has_active_crtc = encoder->base.crtc &&
9194 to_intel_crtc(encoder->base.crtc)->active;
9195
9196 if (encoder->connectors_active && !has_active_crtc) {
9197 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9198 encoder->base.base.id,
9199 drm_get_encoder_name(&encoder->base));
9200
9201 /* Connector is active, but has no active pipe. This is
9202 * fallout from our resume register restoring. Disable
9203 * the encoder manually again. */
9204 if (encoder->base.crtc) {
9205 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9206 encoder->base.base.id,
9207 drm_get_encoder_name(&encoder->base));
9208 encoder->disable(encoder);
9209 }
9210
9211 /* Inconsistent output/port/pipe state happens presumably due to
9212 * a bug in one of the get_hw_state functions. Or someplace else
9213 * in our code, like the register restore mess on resume. Clamp
9214 * things to off as a safer default. */
9215 list_for_each_entry(connector,
9216 &dev->mode_config.connector_list,
9217 base.head) {
9218 if (connector->encoder != encoder)
9219 continue;
9220
9221 intel_connector_break_all_links(connector);
9222 }
9223 }
9224 /* Enabled encoders without active connectors will be fixed in
9225 * the crtc fixup. */
9226 }
9227
i915_redisable_vga(struct drm_device * dev)9228 static void i915_redisable_vga(struct drm_device *dev)
9229 {
9230 struct drm_i915_private *dev_priv = dev->dev_private;
9231 u32 vga_reg;
9232
9233 if (HAS_PCH_SPLIT(dev))
9234 vga_reg = CPU_VGACNTRL;
9235 else
9236 vga_reg = VGACNTRL;
9237
9238 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9239 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9240 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9241 POSTING_READ(vga_reg);
9242 }
9243 }
9244
9245 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9246 * and i915 state tracking structures. */
intel_modeset_setup_hw_state(struct drm_device * dev,bool force_restore)9247 void intel_modeset_setup_hw_state(struct drm_device *dev,
9248 bool force_restore)
9249 {
9250 struct drm_i915_private *dev_priv = dev->dev_private;
9251 enum pipe pipe;
9252 u32 tmp;
9253 struct intel_crtc *crtc;
9254 struct intel_encoder *encoder;
9255 struct intel_connector *connector;
9256
9257 if (IS_HASWELL(dev)) {
9258 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9259
9260 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9261 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9262 case TRANS_DDI_EDP_INPUT_A_ON:
9263 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9264 pipe = PIPE_A;
9265 break;
9266 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9267 pipe = PIPE_B;
9268 break;
9269 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9270 pipe = PIPE_C;
9271 break;
9272 }
9273
9274 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9275 crtc->cpu_transcoder = TRANSCODER_EDP;
9276
9277 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9278 pipe_name(pipe));
9279 }
9280 }
9281
9282 for_each_pipe(pipe) {
9283 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9284
9285 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9286 if (tmp & PIPECONF_ENABLE)
9287 crtc->active = true;
9288 else
9289 crtc->active = false;
9290
9291 crtc->base.enabled = crtc->active;
9292
9293 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9294 crtc->base.base.id,
9295 crtc->active ? "enabled" : "disabled");
9296 }
9297
9298 if (IS_HASWELL(dev))
9299 intel_ddi_setup_hw_pll_state(dev);
9300
9301 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9302 base.head) {
9303 pipe = 0;
9304
9305 if (encoder->get_hw_state(encoder, &pipe)) {
9306 encoder->base.crtc =
9307 dev_priv->pipe_to_crtc_mapping[pipe];
9308 } else {
9309 encoder->base.crtc = NULL;
9310 }
9311
9312 encoder->connectors_active = false;
9313 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9314 encoder->base.base.id,
9315 drm_get_encoder_name(&encoder->base),
9316 encoder->base.crtc ? "enabled" : "disabled",
9317 pipe);
9318 }
9319
9320 list_for_each_entry(connector, &dev->mode_config.connector_list,
9321 base.head) {
9322 if (connector->get_hw_state(connector)) {
9323 connector->base.dpms = DRM_MODE_DPMS_ON;
9324 connector->encoder->connectors_active = true;
9325 connector->base.encoder = &connector->encoder->base;
9326 } else {
9327 connector->base.dpms = DRM_MODE_DPMS_OFF;
9328 connector->base.encoder = NULL;
9329 }
9330 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9331 connector->base.base.id,
9332 drm_get_connector_name(&connector->base),
9333 connector->base.encoder ? "enabled" : "disabled");
9334 }
9335
9336 /* HW state is read out, now we need to sanitize this mess. */
9337 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9338 base.head) {
9339 intel_sanitize_encoder(encoder);
9340 }
9341
9342 for_each_pipe(pipe) {
9343 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9344 intel_sanitize_crtc(crtc);
9345 }
9346
9347 if (force_restore) {
9348 for_each_pipe(pipe) {
9349 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9350 intel_set_mode(&crtc->base, &crtc->base.mode,
9351 crtc->base.x, crtc->base.y, crtc->base.fb);
9352 }
9353
9354 i915_redisable_vga(dev);
9355 } else {
9356 intel_modeset_update_staged_output_state(dev);
9357 }
9358
9359 intel_modeset_check_state(dev);
9360
9361 drm_mode_config_reset(dev);
9362 }
9363
intel_modeset_gem_init(struct drm_device * dev)9364 void intel_modeset_gem_init(struct drm_device *dev)
9365 {
9366 intel_modeset_init_hw(dev);
9367
9368 intel_setup_overlay(dev);
9369
9370 intel_modeset_setup_hw_state(dev, false);
9371 }
9372
intel_modeset_cleanup(struct drm_device * dev)9373 void intel_modeset_cleanup(struct drm_device *dev)
9374 {
9375 struct drm_i915_private *dev_priv = dev->dev_private;
9376 struct drm_crtc *crtc;
9377 struct intel_crtc *intel_crtc;
9378
9379 drm_kms_helper_poll_fini(dev);
9380 DRM_LOCK(dev);
9381
9382 intel_unregister_dsm_handler();
9383
9384
9385 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9386 /* Skip inactive CRTCs */
9387 if (!crtc->fb)
9388 continue;
9389
9390 intel_crtc = to_intel_crtc(crtc);
9391 intel_increase_pllclock(crtc);
9392 }
9393
9394 intel_disable_fbc(dev);
9395
9396 intel_disable_gt_powersave(dev);
9397
9398 ironlake_teardown_rc6(dev);
9399
9400 if (IS_VALLEYVIEW(dev))
9401 vlv_init_dpio(dev);
9402
9403 DRM_UNLOCK(dev);
9404
9405 /* Disable the irq before mode object teardown, for the irq might
9406 * enqueue unpin/hotplug work. */
9407 drm_irq_uninstall(dev);
9408 if (taskqueue_cancel(dev_priv->wq, &dev_priv->hotplug_work, NULL))
9409 taskqueue_drain(dev_priv->wq, &dev_priv->hotplug_work);
9410 if (taskqueue_cancel(dev_priv->wq, &dev_priv->rps.work, NULL))
9411 taskqueue_drain(dev_priv->wq, &dev_priv->rps.work);
9412
9413 /* flush any delayed tasks or pending work */
9414 taskqueue_drain_all(dev_priv->wq);
9415
9416 /* destroy backlight, if any, before the connectors */
9417 intel_panel_destroy_backlight(dev);
9418
9419 drm_mode_config_cleanup(dev);
9420 }
9421
9422 /*
9423 * Return which encoder is currently attached for connector.
9424 */
intel_best_encoder(struct drm_connector * connector)9425 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9426 {
9427 return &intel_attached_encoder(connector)->base;
9428 }
9429
intel_connector_attach_encoder(struct intel_connector * connector,struct intel_encoder * encoder)9430 void intel_connector_attach_encoder(struct intel_connector *connector,
9431 struct intel_encoder *encoder)
9432 {
9433 connector->encoder = encoder;
9434 drm_mode_connector_attach_encoder(&connector->base,
9435 &encoder->base);
9436 }
9437
9438 /*
9439 * set vga decode state - true == enable VGA decode
9440 */
intel_modeset_vga_set_state(struct drm_device * dev,bool state)9441 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9442 {
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9444 u16 gmch_ctrl;
9445
9446 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9447 if (state)
9448 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9449 else
9450 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9451 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9452 return 0;
9453 }
9454
9455 //#ifdef CONFIG_DEBUG_FS
9456 #define seq_printf(m, fmt, ...) sbuf_printf((m), (fmt), ##__VA_ARGS__)
9457
9458 struct intel_display_error_state {
9459 struct intel_cursor_error_state {
9460 u32 control;
9461 u32 position;
9462 u32 base;
9463 u32 size;
9464 } cursor[I915_MAX_PIPES];
9465
9466 struct intel_pipe_error_state {
9467 u32 conf;
9468 u32 source;
9469
9470 u32 htotal;
9471 u32 hblank;
9472 u32 hsync;
9473 u32 vtotal;
9474 u32 vblank;
9475 u32 vsync;
9476 } pipe[I915_MAX_PIPES];
9477
9478 struct intel_plane_error_state {
9479 u32 control;
9480 u32 stride;
9481 u32 size;
9482 u32 pos;
9483 u32 addr;
9484 u32 surface;
9485 u32 tile_offset;
9486 } plane[I915_MAX_PIPES];
9487 };
9488
9489 struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device * dev)9490 intel_display_capture_error_state(struct drm_device *dev)
9491 {
9492 drm_i915_private_t *dev_priv = dev->dev_private;
9493 struct intel_display_error_state *error;
9494 enum transcoder cpu_transcoder;
9495 int i;
9496
9497 error = malloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
9498 if (error == NULL)
9499 return NULL;
9500
9501 for_each_pipe(i) {
9502 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9503
9504 error->cursor[i].control = I915_READ(CURCNTR(i));
9505 error->cursor[i].position = I915_READ(CURPOS(i));
9506 error->cursor[i].base = I915_READ(CURBASE(i));
9507
9508 error->plane[i].control = I915_READ(DSPCNTR(i));
9509 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9510 error->plane[i].size = I915_READ(DSPSIZE(i));
9511 error->plane[i].pos = I915_READ(DSPPOS(i));
9512 error->plane[i].addr = I915_READ(DSPADDR(i));
9513 if (INTEL_INFO(dev)->gen >= 4) {
9514 error->plane[i].surface = I915_READ(DSPSURF(i));
9515 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9516 }
9517
9518 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9519 error->pipe[i].source = I915_READ(PIPESRC(i));
9520 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9521 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9522 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9523 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9524 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9525 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9526 }
9527
9528 return error;
9529 }
9530
9531 void
intel_display_print_error_state(struct sbuf * m,struct drm_device * dev,struct intel_display_error_state * error)9532 intel_display_print_error_state(struct sbuf *m,
9533 struct drm_device *dev,
9534 struct intel_display_error_state *error)
9535 {
9536 drm_i915_private_t *dev_priv = dev->dev_private;
9537 int i;
9538
9539 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9540 for_each_pipe(i) {
9541 seq_printf(m, "Pipe [%d]:\n", i);
9542 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9543 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9544 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9545 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9546 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9547 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9548 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9549 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9550
9551 seq_printf(m, "Plane [%d]:\n", i);
9552 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9553 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9554 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9555 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9556 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9557 if (INTEL_INFO(dev)->gen >= 4) {
9558 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9559 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9560 }
9561
9562 seq_printf(m, "Cursor [%d]:\n", i);
9563 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9564 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9565 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9566 }
9567 }
9568 //#endif
9569