1 /*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/i915/i915_drm.h>
32 #include <dev/drm2/i915/intel_drv.h>
33 #include <dev/drm2/i915/i915_reg.h>
34
i915_pipe_enabled(struct drm_device * dev,enum pipe pipe)35 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
36 {
37 struct drm_i915_private *dev_priv = dev->dev_private;
38 u32 dpll_reg;
39
40 /* On IVB, 3rd pipe shares PLL with another one */
41 if (pipe > 1)
42 return false;
43
44 if (HAS_PCH_SPLIT(dev))
45 dpll_reg = _PCH_DPLL(pipe);
46 else
47 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
48
49 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
50 }
51
i915_save_palette(struct drm_device * dev,enum pipe pipe)52 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
53 {
54 struct drm_i915_private *dev_priv = dev->dev_private;
55 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
56 u32 *array;
57 int i;
58
59 if (!i915_pipe_enabled(dev, pipe))
60 return;
61
62 if (HAS_PCH_SPLIT(dev))
63 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
64
65 if (pipe == PIPE_A)
66 array = dev_priv->regfile.save_palette_a;
67 else
68 array = dev_priv->regfile.save_palette_b;
69
70 for (i = 0; i < 256; i++)
71 array[i] = I915_READ(reg + (i << 2));
72 }
73
i915_restore_palette(struct drm_device * dev,enum pipe pipe)74 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
75 {
76 struct drm_i915_private *dev_priv = dev->dev_private;
77 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
78 u32 *array;
79 int i;
80
81 if (!i915_pipe_enabled(dev, pipe))
82 return;
83
84 if (HAS_PCH_SPLIT(dev))
85 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
86
87 if (pipe == PIPE_A)
88 array = dev_priv->regfile.save_palette_a;
89 else
90 array = dev_priv->regfile.save_palette_b;
91
92 for (i = 0; i < 256; i++)
93 I915_WRITE(reg + (i << 2), array[i]);
94 }
95
i915_read_indexed(struct drm_device * dev,u16 index_port,u16 data_port,u8 reg)96 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
97 {
98 struct drm_i915_private *dev_priv = dev->dev_private;
99
100 I915_WRITE8(index_port, reg);
101 return I915_READ8(data_port);
102 }
103
i915_read_ar(struct drm_device * dev,u16 st01,u8 reg,u16 palette_enable)104 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
105 {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107
108 I915_READ8(st01);
109 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
110 return I915_READ8(VGA_AR_DATA_READ);
111 }
112
i915_write_ar(struct drm_device * dev,u16 st01,u8 reg,u8 val,u16 palette_enable)113 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
114 {
115 struct drm_i915_private *dev_priv = dev->dev_private;
116
117 I915_READ8(st01);
118 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
119 I915_WRITE8(VGA_AR_DATA_WRITE, val);
120 }
121
i915_write_indexed(struct drm_device * dev,u16 index_port,u16 data_port,u8 reg,u8 val)122 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
123 {
124 struct drm_i915_private *dev_priv = dev->dev_private;
125
126 I915_WRITE8(index_port, reg);
127 I915_WRITE8(data_port, val);
128 }
129
i915_save_vga(struct drm_device * dev)130 static void i915_save_vga(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 int i;
134 u16 cr_index, cr_data, st01;
135
136 /* VGA color palette registers */
137 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
138
139 /* MSR bits */
140 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
141 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
142 cr_index = VGA_CR_INDEX_CGA;
143 cr_data = VGA_CR_DATA_CGA;
144 st01 = VGA_ST01_CGA;
145 } else {
146 cr_index = VGA_CR_INDEX_MDA;
147 cr_data = VGA_CR_DATA_MDA;
148 st01 = VGA_ST01_MDA;
149 }
150
151 /* CRT controller regs */
152 i915_write_indexed(dev, cr_index, cr_data, 0x11,
153 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
154 (~0x80));
155 for (i = 0; i <= 0x24; i++)
156 dev_priv->regfile.saveCR[i] =
157 i915_read_indexed(dev, cr_index, cr_data, i);
158 /* Make sure we don't turn off CR group 0 writes */
159 dev_priv->regfile.saveCR[0x11] &= ~0x80;
160
161 /* Attribute controller registers */
162 I915_READ8(st01);
163 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
164 for (i = 0; i <= 0x14; i++)
165 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
166 I915_READ8(st01);
167 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
168 I915_READ8(st01);
169
170 /* Graphics controller registers */
171 for (i = 0; i < 9; i++)
172 dev_priv->regfile.saveGR[i] =
173 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
174
175 dev_priv->regfile.saveGR[0x10] =
176 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
177 dev_priv->regfile.saveGR[0x11] =
178 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
179 dev_priv->regfile.saveGR[0x18] =
180 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
181
182 /* Sequencer registers */
183 for (i = 0; i < 8; i++)
184 dev_priv->regfile.saveSR[i] =
185 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
186 }
187
i915_restore_vga(struct drm_device * dev)188 static void i915_restore_vga(struct drm_device *dev)
189 {
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 int i;
192 u16 cr_index, cr_data, st01;
193
194 /* MSR bits */
195 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
196 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
197 cr_index = VGA_CR_INDEX_CGA;
198 cr_data = VGA_CR_DATA_CGA;
199 st01 = VGA_ST01_CGA;
200 } else {
201 cr_index = VGA_CR_INDEX_MDA;
202 cr_data = VGA_CR_DATA_MDA;
203 st01 = VGA_ST01_MDA;
204 }
205
206 /* Sequencer registers, don't write SR07 */
207 for (i = 0; i < 7; i++)
208 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
209 dev_priv->regfile.saveSR[i]);
210
211 /* CRT controller regs */
212 /* Enable CR group 0 writes */
213 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
214 for (i = 0; i <= 0x24; i++)
215 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
216
217 /* Graphics controller regs */
218 for (i = 0; i < 9; i++)
219 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
220 dev_priv->regfile.saveGR[i]);
221
222 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
223 dev_priv->regfile.saveGR[0x10]);
224 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
225 dev_priv->regfile.saveGR[0x11]);
226 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
227 dev_priv->regfile.saveGR[0x18]);
228
229 /* Attribute controller registers */
230 I915_READ8(st01); /* switch back to index mode */
231 for (i = 0; i <= 0x14; i++)
232 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
233 I915_READ8(st01); /* switch back to index mode */
234 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
235 I915_READ8(st01);
236
237 /* VGA color palette registers */
238 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
239 }
240
i915_save_modeset_reg(struct drm_device * dev)241 static void i915_save_modeset_reg(struct drm_device *dev)
242 {
243 struct drm_i915_private *dev_priv = dev->dev_private;
244 int i;
245
246 if (drm_core_check_feature(dev, DRIVER_MODESET))
247 return;
248
249 /* Cursor state */
250 dev_priv->regfile.saveCURACNTR = I915_READ(_CURACNTR);
251 dev_priv->regfile.saveCURAPOS = I915_READ(_CURAPOS);
252 dev_priv->regfile.saveCURABASE = I915_READ(_CURABASE);
253 dev_priv->regfile.saveCURBCNTR = I915_READ(_CURBCNTR);
254 dev_priv->regfile.saveCURBPOS = I915_READ(_CURBPOS);
255 dev_priv->regfile.saveCURBBASE = I915_READ(_CURBBASE);
256 if (IS_GEN2(dev))
257 dev_priv->regfile.saveCURSIZE = I915_READ(CURSIZE);
258
259 if (HAS_PCH_SPLIT(dev)) {
260 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
261 dev_priv->regfile.saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
262 }
263
264 /* Pipe & plane A info */
265 dev_priv->regfile.savePIPEACONF = I915_READ(_PIPEACONF);
266 dev_priv->regfile.savePIPEASRC = I915_READ(_PIPEASRC);
267 if (HAS_PCH_SPLIT(dev)) {
268 dev_priv->regfile.saveFPA0 = I915_READ(_PCH_FPA0);
269 dev_priv->regfile.saveFPA1 = I915_READ(_PCH_FPA1);
270 dev_priv->regfile.saveDPLL_A = I915_READ(_PCH_DPLL_A);
271 } else {
272 dev_priv->regfile.saveFPA0 = I915_READ(_FPA0);
273 dev_priv->regfile.saveFPA1 = I915_READ(_FPA1);
274 dev_priv->regfile.saveDPLL_A = I915_READ(_DPLL_A);
275 }
276 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
277 dev_priv->regfile.saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
278 dev_priv->regfile.saveHTOTAL_A = I915_READ(_HTOTAL_A);
279 dev_priv->regfile.saveHBLANK_A = I915_READ(_HBLANK_A);
280 dev_priv->regfile.saveHSYNC_A = I915_READ(_HSYNC_A);
281 dev_priv->regfile.saveVTOTAL_A = I915_READ(_VTOTAL_A);
282 dev_priv->regfile.saveVBLANK_A = I915_READ(_VBLANK_A);
283 dev_priv->regfile.saveVSYNC_A = I915_READ(_VSYNC_A);
284 if (!HAS_PCH_SPLIT(dev))
285 dev_priv->regfile.saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
286
287 if (HAS_PCH_SPLIT(dev)) {
288 dev_priv->regfile.savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
289 dev_priv->regfile.savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
290 dev_priv->regfile.savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
291 dev_priv->regfile.savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
292
293 dev_priv->regfile.saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
294 dev_priv->regfile.saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
295
296 dev_priv->regfile.savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
297 dev_priv->regfile.savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
298 dev_priv->regfile.savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
299
300 dev_priv->regfile.saveTRANSACONF = I915_READ(_TRANSACONF);
301 dev_priv->regfile.saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
302 dev_priv->regfile.saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
303 dev_priv->regfile.saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
304 dev_priv->regfile.saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
305 dev_priv->regfile.saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
306 dev_priv->regfile.saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
307 }
308
309 dev_priv->regfile.saveDSPACNTR = I915_READ(_DSPACNTR);
310 dev_priv->regfile.saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
311 dev_priv->regfile.saveDSPASIZE = I915_READ(_DSPASIZE);
312 dev_priv->regfile.saveDSPAPOS = I915_READ(_DSPAPOS);
313 dev_priv->regfile.saveDSPAADDR = I915_READ(_DSPAADDR);
314 if (INTEL_INFO(dev)->gen >= 4) {
315 dev_priv->regfile.saveDSPASURF = I915_READ(_DSPASURF);
316 dev_priv->regfile.saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
317 }
318 i915_save_palette(dev, PIPE_A);
319 dev_priv->regfile.savePIPEASTAT = I915_READ(_PIPEASTAT);
320
321 /* Pipe & plane B info */
322 dev_priv->regfile.savePIPEBCONF = I915_READ(_PIPEBCONF);
323 dev_priv->regfile.savePIPEBSRC = I915_READ(_PIPEBSRC);
324 if (HAS_PCH_SPLIT(dev)) {
325 dev_priv->regfile.saveFPB0 = I915_READ(_PCH_FPB0);
326 dev_priv->regfile.saveFPB1 = I915_READ(_PCH_FPB1);
327 dev_priv->regfile.saveDPLL_B = I915_READ(_PCH_DPLL_B);
328 } else {
329 dev_priv->regfile.saveFPB0 = I915_READ(_FPB0);
330 dev_priv->regfile.saveFPB1 = I915_READ(_FPB1);
331 dev_priv->regfile.saveDPLL_B = I915_READ(_DPLL_B);
332 }
333 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
334 dev_priv->regfile.saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
335 dev_priv->regfile.saveHTOTAL_B = I915_READ(_HTOTAL_B);
336 dev_priv->regfile.saveHBLANK_B = I915_READ(_HBLANK_B);
337 dev_priv->regfile.saveHSYNC_B = I915_READ(_HSYNC_B);
338 dev_priv->regfile.saveVTOTAL_B = I915_READ(_VTOTAL_B);
339 dev_priv->regfile.saveVBLANK_B = I915_READ(_VBLANK_B);
340 dev_priv->regfile.saveVSYNC_B = I915_READ(_VSYNC_B);
341 if (!HAS_PCH_SPLIT(dev))
342 dev_priv->regfile.saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
343
344 if (HAS_PCH_SPLIT(dev)) {
345 dev_priv->regfile.savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
346 dev_priv->regfile.savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
347 dev_priv->regfile.savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
348 dev_priv->regfile.savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
349
350 dev_priv->regfile.saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
351 dev_priv->regfile.saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
352
353 dev_priv->regfile.savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
354 dev_priv->regfile.savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
355 dev_priv->regfile.savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
356
357 dev_priv->regfile.saveTRANSBCONF = I915_READ(_TRANSBCONF);
358 dev_priv->regfile.saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
359 dev_priv->regfile.saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
360 dev_priv->regfile.saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
361 dev_priv->regfile.saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
362 dev_priv->regfile.saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
363 dev_priv->regfile.saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
364 }
365
366 dev_priv->regfile.saveDSPBCNTR = I915_READ(_DSPBCNTR);
367 dev_priv->regfile.saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
368 dev_priv->regfile.saveDSPBSIZE = I915_READ(_DSPBSIZE);
369 dev_priv->regfile.saveDSPBPOS = I915_READ(_DSPBPOS);
370 dev_priv->regfile.saveDSPBADDR = I915_READ(_DSPBADDR);
371 if (INTEL_INFO(dev)->gen >= 4) {
372 dev_priv->regfile.saveDSPBSURF = I915_READ(_DSPBSURF);
373 dev_priv->regfile.saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
374 }
375 i915_save_palette(dev, PIPE_B);
376 dev_priv->regfile.savePIPEBSTAT = I915_READ(_PIPEBSTAT);
377
378 /* Fences */
379 switch (INTEL_INFO(dev)->gen) {
380 case 7:
381 case 6:
382 for (i = 0; i < 16; i++)
383 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
384 break;
385 case 5:
386 case 4:
387 for (i = 0; i < 16; i++)
388 dev_priv->regfile.saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
389 break;
390 case 3:
391 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
392 for (i = 0; i < 8; i++)
393 dev_priv->regfile.saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
394 case 2:
395 for (i = 0; i < 8; i++)
396 dev_priv->regfile.saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
397 break;
398 }
399
400 /* CRT state */
401 if (HAS_PCH_SPLIT(dev))
402 dev_priv->regfile.saveADPA = I915_READ(PCH_ADPA);
403 else
404 dev_priv->regfile.saveADPA = I915_READ(ADPA);
405
406 return;
407 }
408
i915_restore_modeset_reg(struct drm_device * dev)409 static void i915_restore_modeset_reg(struct drm_device *dev)
410 {
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 int dpll_a_reg, fpa0_reg, fpa1_reg;
413 int dpll_b_reg, fpb0_reg, fpb1_reg;
414 int i;
415
416 if (drm_core_check_feature(dev, DRIVER_MODESET))
417 return;
418
419 /* Fences */
420 switch (INTEL_INFO(dev)->gen) {
421 case 7:
422 case 6:
423 for (i = 0; i < 16; i++)
424 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
425 break;
426 case 5:
427 case 4:
428 for (i = 0; i < 16; i++)
429 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->regfile.saveFENCE[i]);
430 break;
431 case 3:
432 case 2:
433 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
434 for (i = 0; i < 8; i++)
435 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->regfile.saveFENCE[i+8]);
436 for (i = 0; i < 8; i++)
437 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->regfile.saveFENCE[i]);
438 break;
439 }
440
441
442 if (HAS_PCH_SPLIT(dev)) {
443 dpll_a_reg = _PCH_DPLL_A;
444 dpll_b_reg = _PCH_DPLL_B;
445 fpa0_reg = _PCH_FPA0;
446 fpb0_reg = _PCH_FPB0;
447 fpa1_reg = _PCH_FPA1;
448 fpb1_reg = _PCH_FPB1;
449 } else {
450 dpll_a_reg = _DPLL_A;
451 dpll_b_reg = _DPLL_B;
452 fpa0_reg = _FPA0;
453 fpb0_reg = _FPB0;
454 fpa1_reg = _FPA1;
455 fpb1_reg = _FPB1;
456 }
457
458 if (HAS_PCH_SPLIT(dev)) {
459 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL);
460 I915_WRITE(DISP_ARB_CTL, dev_priv->regfile.saveDISP_ARB_CTL);
461 }
462
463 /* Pipe & plane A info */
464 /* Prime the clock */
465 if (dev_priv->regfile.saveDPLL_A & DPLL_VCO_ENABLE) {
466 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
467 ~DPLL_VCO_ENABLE);
468 POSTING_READ(dpll_a_reg);
469 udelay(150);
470 }
471 I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
472 I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
473 /* Actually enable it */
474 I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
475 POSTING_READ(dpll_a_reg);
476 udelay(150);
477 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
478 I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
479 POSTING_READ(_DPLL_A_MD);
480 }
481 udelay(150);
482
483 /* Restore mode */
484 I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
485 I915_WRITE(_HBLANK_A, dev_priv->regfile.saveHBLANK_A);
486 I915_WRITE(_HSYNC_A, dev_priv->regfile.saveHSYNC_A);
487 I915_WRITE(_VTOTAL_A, dev_priv->regfile.saveVTOTAL_A);
488 I915_WRITE(_VBLANK_A, dev_priv->regfile.saveVBLANK_A);
489 I915_WRITE(_VSYNC_A, dev_priv->regfile.saveVSYNC_A);
490 if (!HAS_PCH_SPLIT(dev))
491 I915_WRITE(_BCLRPAT_A, dev_priv->regfile.saveBCLRPAT_A);
492
493 if (HAS_PCH_SPLIT(dev)) {
494 I915_WRITE(_PIPEA_DATA_M1, dev_priv->regfile.savePIPEA_DATA_M1);
495 I915_WRITE(_PIPEA_DATA_N1, dev_priv->regfile.savePIPEA_DATA_N1);
496 I915_WRITE(_PIPEA_LINK_M1, dev_priv->regfile.savePIPEA_LINK_M1);
497 I915_WRITE(_PIPEA_LINK_N1, dev_priv->regfile.savePIPEA_LINK_N1);
498
499 I915_WRITE(_FDI_RXA_CTL, dev_priv->regfile.saveFDI_RXA_CTL);
500 I915_WRITE(_FDI_TXA_CTL, dev_priv->regfile.saveFDI_TXA_CTL);
501
502 I915_WRITE(_PFA_CTL_1, dev_priv->regfile.savePFA_CTL_1);
503 I915_WRITE(_PFA_WIN_SZ, dev_priv->regfile.savePFA_WIN_SZ);
504 I915_WRITE(_PFA_WIN_POS, dev_priv->regfile.savePFA_WIN_POS);
505
506 I915_WRITE(_TRANSACONF, dev_priv->regfile.saveTRANSACONF);
507 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->regfile.saveTRANS_HTOTAL_A);
508 I915_WRITE(_TRANS_HBLANK_A, dev_priv->regfile.saveTRANS_HBLANK_A);
509 I915_WRITE(_TRANS_HSYNC_A, dev_priv->regfile.saveTRANS_HSYNC_A);
510 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->regfile.saveTRANS_VTOTAL_A);
511 I915_WRITE(_TRANS_VBLANK_A, dev_priv->regfile.saveTRANS_VBLANK_A);
512 I915_WRITE(_TRANS_VSYNC_A, dev_priv->regfile.saveTRANS_VSYNC_A);
513 }
514
515 /* Restore plane info */
516 I915_WRITE(_DSPASIZE, dev_priv->regfile.saveDSPASIZE);
517 I915_WRITE(_DSPAPOS, dev_priv->regfile.saveDSPAPOS);
518 I915_WRITE(_PIPEASRC, dev_priv->regfile.savePIPEASRC);
519 I915_WRITE(_DSPAADDR, dev_priv->regfile.saveDSPAADDR);
520 I915_WRITE(_DSPASTRIDE, dev_priv->regfile.saveDSPASTRIDE);
521 if (INTEL_INFO(dev)->gen >= 4) {
522 I915_WRITE(_DSPASURF, dev_priv->regfile.saveDSPASURF);
523 I915_WRITE(_DSPATILEOFF, dev_priv->regfile.saveDSPATILEOFF);
524 }
525
526 I915_WRITE(_PIPEACONF, dev_priv->regfile.savePIPEACONF);
527
528 i915_restore_palette(dev, PIPE_A);
529 /* Enable the plane */
530 I915_WRITE(_DSPACNTR, dev_priv->regfile.saveDSPACNTR);
531 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
532
533 /* Pipe & plane B info */
534 if (dev_priv->regfile.saveDPLL_B & DPLL_VCO_ENABLE) {
535 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
536 ~DPLL_VCO_ENABLE);
537 POSTING_READ(dpll_b_reg);
538 udelay(150);
539 }
540 I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
541 I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
542 /* Actually enable it */
543 I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
544 POSTING_READ(dpll_b_reg);
545 udelay(150);
546 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
547 I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
548 POSTING_READ(_DPLL_B_MD);
549 }
550 udelay(150);
551
552 /* Restore mode */
553 I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
554 I915_WRITE(_HBLANK_B, dev_priv->regfile.saveHBLANK_B);
555 I915_WRITE(_HSYNC_B, dev_priv->regfile.saveHSYNC_B);
556 I915_WRITE(_VTOTAL_B, dev_priv->regfile.saveVTOTAL_B);
557 I915_WRITE(_VBLANK_B, dev_priv->regfile.saveVBLANK_B);
558 I915_WRITE(_VSYNC_B, dev_priv->regfile.saveVSYNC_B);
559 if (!HAS_PCH_SPLIT(dev))
560 I915_WRITE(_BCLRPAT_B, dev_priv->regfile.saveBCLRPAT_B);
561
562 if (HAS_PCH_SPLIT(dev)) {
563 I915_WRITE(_PIPEB_DATA_M1, dev_priv->regfile.savePIPEB_DATA_M1);
564 I915_WRITE(_PIPEB_DATA_N1, dev_priv->regfile.savePIPEB_DATA_N1);
565 I915_WRITE(_PIPEB_LINK_M1, dev_priv->regfile.savePIPEB_LINK_M1);
566 I915_WRITE(_PIPEB_LINK_N1, dev_priv->regfile.savePIPEB_LINK_N1);
567
568 I915_WRITE(_FDI_RXB_CTL, dev_priv->regfile.saveFDI_RXB_CTL);
569 I915_WRITE(_FDI_TXB_CTL, dev_priv->regfile.saveFDI_TXB_CTL);
570
571 I915_WRITE(_PFB_CTL_1, dev_priv->regfile.savePFB_CTL_1);
572 I915_WRITE(_PFB_WIN_SZ, dev_priv->regfile.savePFB_WIN_SZ);
573 I915_WRITE(_PFB_WIN_POS, dev_priv->regfile.savePFB_WIN_POS);
574
575 I915_WRITE(_TRANSBCONF, dev_priv->regfile.saveTRANSBCONF);
576 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->regfile.saveTRANS_HTOTAL_B);
577 I915_WRITE(_TRANS_HBLANK_B, dev_priv->regfile.saveTRANS_HBLANK_B);
578 I915_WRITE(_TRANS_HSYNC_B, dev_priv->regfile.saveTRANS_HSYNC_B);
579 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->regfile.saveTRANS_VTOTAL_B);
580 I915_WRITE(_TRANS_VBLANK_B, dev_priv->regfile.saveTRANS_VBLANK_B);
581 I915_WRITE(_TRANS_VSYNC_B, dev_priv->regfile.saveTRANS_VSYNC_B);
582 }
583
584 /* Restore plane info */
585 I915_WRITE(_DSPBSIZE, dev_priv->regfile.saveDSPBSIZE);
586 I915_WRITE(_DSPBPOS, dev_priv->regfile.saveDSPBPOS);
587 I915_WRITE(_PIPEBSRC, dev_priv->regfile.savePIPEBSRC);
588 I915_WRITE(_DSPBADDR, dev_priv->regfile.saveDSPBADDR);
589 I915_WRITE(_DSPBSTRIDE, dev_priv->regfile.saveDSPBSTRIDE);
590 if (INTEL_INFO(dev)->gen >= 4) {
591 I915_WRITE(_DSPBSURF, dev_priv->regfile.saveDSPBSURF);
592 I915_WRITE(_DSPBTILEOFF, dev_priv->regfile.saveDSPBTILEOFF);
593 }
594
595 I915_WRITE(_PIPEBCONF, dev_priv->regfile.savePIPEBCONF);
596
597 i915_restore_palette(dev, PIPE_B);
598 /* Enable the plane */
599 I915_WRITE(_DSPBCNTR, dev_priv->regfile.saveDSPBCNTR);
600 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
601
602 /* Cursor state */
603 I915_WRITE(_CURAPOS, dev_priv->regfile.saveCURAPOS);
604 I915_WRITE(_CURACNTR, dev_priv->regfile.saveCURACNTR);
605 I915_WRITE(_CURABASE, dev_priv->regfile.saveCURABASE);
606 I915_WRITE(_CURBPOS, dev_priv->regfile.saveCURBPOS);
607 I915_WRITE(_CURBCNTR, dev_priv->regfile.saveCURBCNTR);
608 I915_WRITE(_CURBBASE, dev_priv->regfile.saveCURBBASE);
609 if (IS_GEN2(dev))
610 I915_WRITE(CURSIZE, dev_priv->regfile.saveCURSIZE);
611
612 /* CRT state */
613 if (HAS_PCH_SPLIT(dev))
614 I915_WRITE(PCH_ADPA, dev_priv->regfile.saveADPA);
615 else
616 I915_WRITE(ADPA, dev_priv->regfile.saveADPA);
617
618 return;
619 }
620
i915_save_display(struct drm_device * dev)621 static void i915_save_display(struct drm_device *dev)
622 {
623 struct drm_i915_private *dev_priv = dev->dev_private;
624
625 /* Display arbitration control */
626 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
627
628 /* This is only meaningful in non-KMS mode */
629 /* Don't regfile.save them in KMS mode */
630 i915_save_modeset_reg(dev);
631
632 /* LVDS state */
633 if (HAS_PCH_SPLIT(dev)) {
634 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
635 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
636 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
637 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
638 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
639 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
640 } else {
641 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
642 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
643 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
644 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
645 if (INTEL_INFO(dev)->gen >= 4)
646 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
647 if (IS_MOBILE(dev) && !IS_I830(dev))
648 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
649 }
650
651 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
652 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
653
654 if (HAS_PCH_SPLIT(dev)) {
655 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
656 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
657 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
658 } else {
659 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
660 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
661 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
662 }
663
664 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
665 /* Display Port state */
666 if (SUPPORTS_INTEGRATED_DP(dev)) {
667 dev_priv->regfile.saveDP_B = I915_READ(DP_B);
668 dev_priv->regfile.saveDP_C = I915_READ(DP_C);
669 dev_priv->regfile.saveDP_D = I915_READ(DP_D);
670 dev_priv->regfile.savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
671 dev_priv->regfile.savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
672 dev_priv->regfile.savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
673 dev_priv->regfile.savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
674 dev_priv->regfile.savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
675 dev_priv->regfile.savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
676 dev_priv->regfile.savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
677 dev_priv->regfile.savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
678 }
679 /* FIXME: regfile.save TV & SDVO state */
680 }
681
682 /* Only regfile.save FBC state on the platform that supports FBC */
683 if (I915_HAS_FBC(dev)) {
684 if (HAS_PCH_SPLIT(dev)) {
685 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
686 } else if (IS_GM45(dev)) {
687 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
688 } else {
689 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
690 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
691 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
692 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
693 }
694 }
695
696 /* VGA state */
697 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
698 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
699 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
700 if (HAS_PCH_SPLIT(dev))
701 dev_priv->regfile.saveVGACNTRL = I915_READ(CPU_VGACNTRL);
702 else
703 dev_priv->regfile.saveVGACNTRL = I915_READ(VGACNTRL);
704
705 i915_save_vga(dev);
706 }
707
i915_restore_display(struct drm_device * dev)708 static void i915_restore_display(struct drm_device *dev)
709 {
710 struct drm_i915_private *dev_priv = dev->dev_private;
711
712 /* Display arbitration */
713 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
714
715 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
716 /* Display port ratios (must be done before clock is set) */
717 if (SUPPORTS_INTEGRATED_DP(dev)) {
718 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
719 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->regfile.savePIPEB_GMCH_DATA_M);
720 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->regfile.savePIPEA_GMCH_DATA_N);
721 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->regfile.savePIPEB_GMCH_DATA_N);
722 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->regfile.savePIPEA_DP_LINK_M);
723 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->regfile.savePIPEB_DP_LINK_M);
724 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->regfile.savePIPEA_DP_LINK_N);
725 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->regfile.savePIPEB_DP_LINK_N);
726 }
727 }
728
729 /* This is only meaningful in non-KMS mode */
730 /* Don't restore them in KMS mode */
731 i915_restore_modeset_reg(dev);
732
733 /* LVDS state */
734 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
735 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
736
737 if (HAS_PCH_SPLIT(dev)) {
738 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
739 } else if (IS_MOBILE(dev) && !IS_I830(dev))
740 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
741
742 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
743 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
744
745 if (HAS_PCH_SPLIT(dev)) {
746 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
747 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
748 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
749 * otherwise we get blank eDP screen after S3 on some machines
750 */
751 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
752 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
753 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
754 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
755 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
756 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
757 I915_WRITE(RSTDBYCTL,
758 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
759 } else {
760 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
761 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
762 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
763 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
764 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
765 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
766 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
767 }
768
769 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
770 /* Display Port state */
771 if (SUPPORTS_INTEGRATED_DP(dev)) {
772 I915_WRITE(DP_B, dev_priv->regfile.saveDP_B);
773 I915_WRITE(DP_C, dev_priv->regfile.saveDP_C);
774 I915_WRITE(DP_D, dev_priv->regfile.saveDP_D);
775 }
776 /* FIXME: restore TV & SDVO state */
777 }
778
779 /* only restore FBC info on the platform that supports FBC*/
780 intel_disable_fbc(dev);
781 if (I915_HAS_FBC(dev)) {
782 if (HAS_PCH_SPLIT(dev)) {
783 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
784 } else if (IS_GM45(dev)) {
785 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
786 } else {
787 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
788 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
789 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
790 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
791 }
792 }
793 /* VGA state */
794 if (HAS_PCH_SPLIT(dev))
795 I915_WRITE(CPU_VGACNTRL, dev_priv->regfile.saveVGACNTRL);
796 else
797 I915_WRITE(VGACNTRL, dev_priv->regfile.saveVGACNTRL);
798
799 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
800 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
801 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
802 POSTING_READ(VGA_PD);
803 udelay(150);
804
805 i915_restore_vga(dev);
806 }
807
i915_save_state(struct drm_device * dev)808 int i915_save_state(struct drm_device *dev)
809 {
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 int i;
812
813 pci_read_config_byte(dev->dev, LBB, &dev_priv->regfile.saveLBB);
814
815 DRM_LOCK(dev);
816
817 i915_save_display(dev);
818
819 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
820 /* Interrupt state */
821 if (HAS_PCH_SPLIT(dev)) {
822 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
823 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
824 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
825 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
826 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
827 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
828 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
829 I915_READ(RSTDBYCTL);
830 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
831 } else {
832 dev_priv->regfile.saveIER = I915_READ(IER);
833 dev_priv->regfile.saveIMR = I915_READ(IMR);
834 }
835 }
836
837 intel_disable_gt_powersave(dev);
838
839 /* Cache mode state */
840 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
841
842 /* Memory Arbitration state */
843 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
844
845 /* Scratch space */
846 for (i = 0; i < 16; i++) {
847 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
848 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
849 }
850 for (i = 0; i < 3; i++)
851 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
852
853 DRM_UNLOCK(dev);
854
855 return 0;
856 }
857
i915_restore_state(struct drm_device * dev)858 int i915_restore_state(struct drm_device *dev)
859 {
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 int i;
862
863 pci_write_config_byte(dev->dev, LBB, dev_priv->regfile.saveLBB);
864
865 DRM_LOCK(dev);
866
867 i915_restore_display(dev);
868
869 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
870 /* Interrupt state */
871 if (HAS_PCH_SPLIT(dev)) {
872 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
873 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
874 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
875 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
876 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
877 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
878 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
879 } else {
880 I915_WRITE(IER, dev_priv->regfile.saveIER);
881 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
882 }
883 }
884
885 /* Cache mode state */
886 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
887
888 /* Memory arbitration state */
889 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
890
891 for (i = 0; i < 16; i++) {
892 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
893 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
894 }
895 for (i = 0; i < 3; i++)
896 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
897
898 DRM_UNLOCK(dev);
899
900 intel_i2c_reset(dev);
901
902 return 0;
903 }
904