314 	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;  in ironlake_edp_have_panel_vdd()
329 			      I915_READ(PCH_PP_CONTROL));  in intel_dp_check_edp()
973 		      I915_READ(PCH_PP_CONTROL));  in ironlake_wait_panel_status()
978 			  I915_READ(PCH_PP_CONTROL));  in ironlake_wait_panel_status()
1007 	u32	control = I915_READ(PCH_PP_CONTROL);  in ironlake_get_pp_control()
1039 	I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_panel_vdd_on()
1040 	POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_panel_vdd_on()
1042 		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));  in ironlake_edp_panel_vdd_on()
1062 		I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_panel_vdd_off_sync()
1063 		POSTING_READ(PCH_PP_CONTROL);  in ironlake_panel_vdd_off_sync()
1067 			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));  in ironlake_panel_vdd_off_sync()
1132 		I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_panel_on()
1133 		POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_panel_on()
1140 	I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_panel_on()
1141 	POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_panel_on()
1147 		I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_panel_on()
1148 		POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_panel_on()
1169 	I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_panel_off()
1170 	POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_panel_off()
1198 	I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_backlight_on()
1199 	POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_backlight_on()
1218 	I915_WRITE(PCH_PP_CONTROL, pp);  in ironlake_edp_backlight_off()
1219 	POSTING_READ(PCH_PP_CONTROL);  in ironlake_edp_backlight_off()
2605 	I915_WRITE(PCH_PP_CONTROL, pp);  in intel_dp_init_panel_power_sequencer()