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Searched refs:getReg (Results 1 – 25 of 257) sorted by relevance

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/trueos/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp38 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
39 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
40 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
46 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
47 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
48 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
54 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
56 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
62 Src1Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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HDX86ATTInstPrinter.cpp155 printRegName(O, Op.getReg()); in printOperand()
183 if (SegReg.getReg()) { in printMemReference()
190 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
197 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
199 if (BaseReg.getReg()) in printMemReference()
202 if (IndexReg.getReg()) { in printMemReference()
/trueos/contrib/llvm/lib/Target/ARM/InstPrinter/
HDARMInstPrinter.cpp121 printRegName(O, Dst.getReg()); in printInst()
123 printRegName(O, MO1.getReg()); in printInst()
126 printRegName(O, MO2.getReg()); in printInst()
143 printRegName(O, Dst.getReg()); in printInst()
145 printRegName(O, MO1.getReg()); in printInst()
163 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
177 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
182 printRegName(O, MI->getOperand(1).getReg()); in printInst()
192 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
206 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonSplitTFRCondSets.cpp97 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
98 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
99 int SrcReg2 = MI->getOperand(3).getReg(); in runOnMachineFunction()
115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
127 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction()
128 int SrcReg1 = MI->getOperand(2).getReg(); in runOnMachineFunction()
135 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
140 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
145 addReg(MI->getOperand(1).getReg()). in runOnMachineFunction()
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HDHexagonPeephole.cpp141 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
142 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
163 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction()
180 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
181 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction()
192 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
193 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
215 unsigned DstReg = Dst.getReg(); in runOnMachineFunction()
216 unsigned SrcReg = Src.getReg(); in runOnMachineFunction()
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HDHexagonHardwareLoops.cpp255 unsigned getReg() const { in getReg() function in __anon7b8ac49d0111::CountValue
354 unsigned PhiOpReg = Phi->getOperand(i).getReg(); in findInductionRegister()
362 unsigned IndReg = DI->getOperand(1).getReg(); in findInductionRegister()
364 unsigned UpdReg = DI->getOperand(0).getReg(); in findInductionRegister()
380 unsigned PredR = Cond[CSz-1].getReg(); in findInductionRegister()
475 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump. in getLoopTripCount()
500 unsigned PredReg = Cond[Cond.size()-1].getReg(); in getLoopTripCount()
528 if (Op2.isImm() || Op1.getReg() == IVReg) in getLoopTripCount()
565 if (!defWithImmediate(InitialValue->getReg())) in getLoopTripCount()
592 unsigned R = InitialValue->getReg(); in getLoopTripCount()
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HDHexagonCopyToCombine.cpp122 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType()
123 unsigned SrcReg = MI->getOperand(1).getReg(); in isCombinableInstType()
132 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType()
150 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType()
214 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) in removeKillInfo()
241 unsigned I2UseReg = IsImmUseReg ? 0 : I2->getOperand(1).getReg(); in isSafeToMoveTogether()
306 unsigned I1UseReg = IsImmUseReg ? 0 : I1->getOperand(1).getReg(); in isSafeToMoveTogether()
371 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) in findPotentialNewifiableTFRs()
375 unsigned Reg = Op.getReg(); in findPotentialNewifiableTFRs()
401 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) in findPotentialNewifiableTFRs()
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HDHexagonVLIWPacketizer.cpp356 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { in IsCallDependent()
485 DefRegsSet[MI->getOperand(opNum).getReg()] = 1; in GetPostIncrementOperand()
491 if (DefRegsSet[MI->getOperand(opNum).getReg()]) { in GetPostIncrementOperand()
548 GetStoreValueOperand(MI).getReg() != DepReg) in CanPromoteToNewValueStore()
582 GetPostIncrementOperand(MI, QII).getReg() == DepReg) { in CanPromoteToNewValueStore()
588 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) { in CanPromoteToNewValueStore()
612 predRegNumSrc = PacketMI->getOperand(opNum).getReg(); in CanPromoteToNewValueStore()
624 predRegNumDst = MI->getOperand(opNum).getReg(); in CanPromoteToNewValueStore()
678 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(), in CanPromoteToNewValueStore()
692 GetStoreValueOperand(MI).getReg() == DepReg) { in CanPromoteToNewValueStore()
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/trueos/contrib/llvm/lib/Target/X86/MCTargetDesc/
HDX86MCCodeEmitter.cpp56 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; in GetX86RegNum()
70 unsigned SrcReg = MI.getOperand(OpNum).getReg(); in getVEXRegisterEncoding()
82 assert(X86::K0 != MI.getOperand(OpNum).getReg() && in getWriteMaskRegisterEncoding()
224 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
225 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
226 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
227 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
239 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
240 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
241 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
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/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
86 .addReg(MI->getOperand(0).getReg()); in EmitInstruction()
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/trueos/contrib/llvm/lib/Target/R600/
HDR600ExpandSpecialInstrs.cpp77 DstOp.getReg(), AMDGPU::OQAP); in runOnMachineFunction()
85 MI.getOperand(LDSPredSelIdx).getReg()); in runOnMachineFunction()
97 MI.getOperand(0).getReg(), // dst in runOnMachineFunction()
98 MI.getOperand(1).getReg(), // src0 in runOnMachineFunction()
119 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
124 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
150 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
153 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
173 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
192 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction()
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HDSILowerControlFlow.cpp197 unsigned Reg = MI.getOperand(0).getReg(); in If()
198 unsigned Vcc = MI.getOperand(1).getReg(); in If()
215 unsigned Dst = MI.getOperand(0).getReg(); in Else()
216 unsigned Src = MI.getOperand(1).getReg(); in Else()
235 unsigned Dst = MI.getOperand(0).getReg(); in Break()
236 unsigned Src = MI.getOperand(1).getReg(); in Break()
249 unsigned Dst = MI.getOperand(0).getReg(); in IfBreak()
250 unsigned Vcc = MI.getOperand(1).getReg(); in IfBreak()
251 unsigned Src = MI.getOperand(2).getReg(); in IfBreak()
264 unsigned Dst = MI.getOperand(0).getReg(); in ElseBreak()
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HDSIFixSGPRCopies.cpp120 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg())) in hasVGPROperands()
123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
149 I->getOperand(0).getReg(), in inferRegClassFromUses()
172 return inferRegClassFromDef(TRI, MRI, Def->getOperand(1).getReg(), in inferRegClassFromDef()
180 unsigned DstReg = Copy.getOperand(0).getReg(); in isVGPRToSGPRCopy()
181 unsigned SrcReg = Copy.getOperand(1).getReg(); in isVGPRToSGPRCopy()
221 unsigned Reg = MI.getOperand(i).getReg(); in runOnMachineFunction()
226 unsigned Reg = MI.getOperand(0).getReg(); in runOnMachineFunction()
239 unsigned Reg = MI.getOperand(i).getReg(); in runOnMachineFunction()
HDSIInstrInfo.cpp197 RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg()))) in commuteInstruction()
215 unsigned Reg = MI->getOperand(1).getReg(); in commuteInstruction()
316 !TargetRegisterInfo::isVirtualRegister(MO.getReg())) { in verifyInstruction()
319 if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC) in verifyInstruction()
323 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC || in verifyInstruction()
325 (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) || in verifyInstruction()
326 AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) { in verifyInstruction()
327 if (SGPRUsed != MO.getReg()) { in verifyInstruction()
329 SGPRUsed = MO.getReg(); in verifyInstruction()
399 return MRI.getRegClass(MI.getOperand(OpNo).getReg()); in getOpRegClass()
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/trueos/contrib/llvm/lib/Target/X86/
HDX86CodeEmitter.cpp182 unsigned Reg = MO.getReg(); in determineREX()
484 unsigned BaseReg = Base.getReg(); in emitMemModRMByte()
489 assert(IndexReg.getReg() == 0 && Is64BitMode && in emitMemModRMByte()
510 IndexReg.getReg() == 0 && in emitMemModRMByte()
548 assert(IndexReg.getReg() != X86::ESP && in emitMemModRMByte()
549 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); in emitMemModRMByte()
582 if (IndexReg.getReg()) in emitMemModRMByte()
583 IndexRegNo = getX86RegNum(IndexReg.getReg()); in emitMemModRMByte()
590 if (IndexReg.getReg()) in emitMemModRMByte()
591 IndexRegNo = getX86RegNum(IndexReg.getReg()); in emitMemModRMByte()
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/trueos/contrib/llvm/lib/Target/ARM/
HDARMFeatures.h73 return Instr->getOperand(2).getReg() != ARM::PC;
78 return Instr->getOperand(0).getReg() != ARM::PC;
80 return Instr->getOperand(BLXOperandIndex).getReg() != ARM::PC;
82 return Instr->getOperand(0).getReg() != ARM::PC &&
83 Instr->getOperand(2).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(1).getReg() != ARM::PC;
HDA15SDOptimizer.cpp143 unsigned Reg = MO.getReg(); in usesRegClass()
173 SReg = MI->getOperand(1).getReg(); in getPrefSPRLane()
202 unsigned Reg = MO.getReg(); in eraseInstrWithNoUses()
225 unsigned DefReg = MODef.getReg(); in eraseInstrWithNoUses()
255 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg()); in optimizeSDPattern()
259 unsigned DPRReg = MI->getOperand(1).getReg(); in optimizeSDPattern()
260 unsigned SPRReg = MI->getOperand(2).getReg(); in optimizeSDPattern()
263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); in optimizeSDPattern()
264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); in optimizeSDPattern()
281 unsigned FullReg = SPRMI->getOperand(1).getReg(); in optimizeSDPattern()
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HDARMAsmPrinter.cpp63 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) { in EmitDwarfRegOp()
69 unsigned Reg = MLoc.getReg(); in EmitDwarfRegOp()
175 unsigned Reg = MO.getReg(); in printOperand()
263 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) in PrintAsmOperand()
279 unsigned Reg = MI->getOperand(OpNum).getReg(); in PrintAsmOperand()
306 unsigned RegBegin = MO.getReg(); in PrintAsmOperand()
326 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg()); in PrintAsmOperand()
369 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ? in PrintAsmOperand()
382 unsigned Reg = MO.getReg(); in PrintAsmOperand()
391 unsigned Reg = MI->getOperand(OpNum).getReg(); in PrintAsmOperand()
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HDMLxExpansionPass.cpp89 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
117 unsigned Reg = MI->getOperand(0).getReg(); in getDefReg()
128 Reg = UseMI->getOperand(0).getReg(); in getDefReg()
143 unsigned Reg = MI->getOperand(1).getReg(); in hasLoopHazard()
157 unsigned SrcReg = DefMI->getOperand(i).getReg(); in hasLoopHazard()
165 Reg = DefMI->getOperand(1).getReg(); in hasLoopHazard()
171 Reg = DefMI->getOperand(2).getReg(); in hasLoopHazard()
274 unsigned DstReg = MI->getOperand(0).getReg(); in ExpandFPMLxInstruction()
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/trueos/contrib/llvm/lib/Target/Mips/Disassembler/
HDMipsDisassembler.cpp422 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { in getReg() function
444 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo); in DecodeGPR64RegisterClass()
455 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo); in DecodeGPR32RegisterClass()
484 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo); in DecodeFGR64RegisterClass()
496 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo); in DecodeFGR32RegisterClass()
508 unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); in DecodeFGRH32RegisterClass()
519 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo); in DecodeCCRRegisterClass()
530 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo); in DecodeFCCRegisterClass()
543 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); in DecodeMem()
544 Base = getReg(Decoder, Mips::GPR32RegClassID, Base); in DecodeMem()
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/trueos/contrib/llvm/lib/CodeGen/
HDTwoAddressInstructionPass.cpp197 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
201 UseRegs.insert(MO.getReg()); in sink3AddrInstruction()
210 DefReg = MO.getReg(); in sink3AddrInstruction()
270 unsigned MOReg = MO.getReg(); in sink3AddrInstruction()
345 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
346 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
348 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
349 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
438 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
442 DstReg = MI.getOperand(ti).getReg(); in isTwoAddrUse()
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/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.cpp96 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr()
97 DstReg = MI.getOperand(0).getReg(); in isCoalescableExtInstr()
120 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
144 return MI->getOperand(0).getReg(); in isStoreToStackSlot()
174 unsigned Reg0 = MI->getOperand(0).getReg(); in commuteInstruction()
175 unsigned Reg1 = MI->getOperand(1).getReg(); in commuteInstruction()
176 unsigned Reg2 = MI->getOperand(2).getReg(); in commuteInstruction()
196 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); in commuteInstruction()
407 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in InsertBranch()
413 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); in InsertBranch()
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/trueos/contrib/llvm/lib/Target/Sparc/
HDDelaySlotFiller.cpp261 unsigned Reg = MO.getReg(); in delayHasHazard()
294 RegUses.insert(Reg.getReg()); in insertCallDefsUses()
301 RegUses.insert(RegOrImm.getReg()); in insertCallDefsUses()
316 unsigned Reg = MO.getReg(); in insertDefsUses()
372 unsigned reg = AddMI->getOperand(0).getReg(); in combineRestoreADD()
400 unsigned reg = OrMI->getOperand(0).getReg(); in combineRestoreOR()
406 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
407 && OrMI->getOperand(2).getReg() != SP::G0) in combineRestoreOR()
411 && OrMI->getOperand(1).getReg() != SP::G0 in combineRestoreOR()
438 unsigned reg = SetHiMI->getOperand(0).getReg(); in combineRestoreSETHIi()
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/trueos/contrib/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp567 unsigned getReg() const { in getReg() function in __anon87cffc590311::ARMOperand
1572 Inst.addOperand(MCOperand::CreateReg(getReg())); in addCCOutOperands()
1577 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
2511 OS << "<ccout " << getReg() << ">"; in print()
2566 OS << "<register " << getReg() << ">"; in print()
2726 int SrcReg = PrevOp->getReg(); in tryParseShiftRegister()
4148 ((ARMOperand*)Operands[4])->getReg() == in cvtThumbMultiply()
4149 ((ARMOperand*)Operands[3])->getReg()) in cvtThumbMultiply()
4865 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) in shouldOmitCCOutOperand()
4873 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) in shouldOmitCCOutOperand()
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/trueos/contrib/llvm/lib/Target/Mips/
HDMips16ISelLowering.cpp535 BuildMI(BB, DL, TII->get(Opc)).addReg(MI->getOperand(3).getReg()) in emitSel16()
552 TII->get(Mips::PHI), MI->getOperand(0).getReg()) in emitSel16()
553 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) in emitSel16()
554 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); in emitSel16()
598 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) in emitSelT16()
599 .addReg(MI->getOperand(4).getReg()); in emitSelT16()
616 TII->get(Mips::PHI), MI->getOperand(0).getReg()) in emitSelT16()
617 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB) in emitSelT16()
618 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB); in emitSelT16()
663 BuildMI(BB, DL, TII->get(Opc2)).addReg(MI->getOperand(3).getReg()) in emitSeliT16()
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