197       RI.isSGPRClass(MRI.getRegClass(MI->getOperand(1).getReg())))  in commuteInstruction()
215     unsigned Reg = MI->getOperand(1).getReg();  in commuteInstruction()
316           !TargetRegisterInfo::isVirtualRegister(MO.getReg())) {  in verifyInstruction()
319         if (!MO.isImplicit() && MO.getReg() == AMDGPU::EXEC)  in verifyInstruction()
323         if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||  in verifyInstruction()
325             (AMDGPU::SGPR_32RegClass.contains(MO.getReg()) ||  in verifyInstruction()
326             AMDGPU::SGPR_64RegClass.contains(MO.getReg())))) {  in verifyInstruction()
327           if (SGPRUsed != MO.getReg()) {  in verifyInstruction()
329             SGPRUsed = MO.getReg();  in verifyInstruction()
399     return MRI.getRegClass(MI.getOperand(OpNo).getReg());  in getOpRegClass()
453         RI.isSGPRClass(MRI.getRegClass(Src0.getReg()))) {  in legalizeOperands()
459         RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {  in legalizeOperands()
467         (Src1.isReg() && RI.isSGPRClass(MRI.getRegClass(Src1.getReg())))) {  in legalizeOperands()
488         if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))  in legalizeOperands()
491         assert(MO.getReg() != AMDGPU::SCC && "SCC operand to VOP3 instruction");  in legalizeOperands()
493         if (SGPRReg == AMDGPU::NoRegister || SGPRReg == MO.getReg()) {  in legalizeOperands()
494           SGPRReg = MO.getReg();  in legalizeOperands()
516           !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))  in legalizeOperands()
519               MRI.getRegClass(MI->getOperand(i).getReg());  in legalizeOperands()
543           !TargetRegisterInfo::isVirtualRegister(MI->getOperand(i).getReg()))  in legalizeOperands()
575       if (Op.isReg() && Op.getReg() == AMDGPU::SCC)  in moveToVALU()
617     unsigned DstReg = Inst->getOperand(0).getReg();  in moveToVALU()