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Searched refs:dev_priv (Results 1 – 25 of 80) sorted by relevance

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/trueos/sys/dev/drm/
HDradeon_cp.c46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) in radeon_read_ring_rptr() argument
52 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_read_ring_rptr()
53 val = DRM_READ32(dev_priv->ring_rptr, off); in radeon_read_ring_rptr()
56 dev_priv->ring_rptr->virtual) + in radeon_read_ring_rptr()
63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) in radeon_get_ring_head() argument
65 if (dev_priv->writeback_works) in radeon_get_ring_head()
66 return radeon_read_ring_rptr(dev_priv, 0); in radeon_get_ring_head()
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_ring_head()
75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) in radeon_write_ring_rptr() argument
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HDi915_suspend.c40 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
50 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
59 array = dev_priv->save_palette_a; in i915_save_palette()
61 array = dev_priv->save_palette_b; in i915_save_palette()
69 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
78 array = dev_priv->save_palette_a; in i915_restore_palette()
80 array = dev_priv->save_palette_b; in i915_restore_palette()
88 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
96 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
105 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
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HDsavage_bci.c41 savage_bci_wait_fifo_shadow(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_shadow() argument
43 uint32_t mask = dev_priv->status_used_mask; in savage_bci_wait_fifo_shadow()
44 uint32_t threshold = dev_priv->bci_threshold_hi; in savage_bci_wait_fifo_shadow()
49 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold) in savage_bci_wait_fifo_shadow()
56 status = dev_priv->status_ptr[0]; in savage_bci_wait_fifo_shadow()
70 savage_bci_wait_fifo_s3d(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s3d() argument
72 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s3d()
91 savage_bci_wait_fifo_s4(drm_savage_private_t *dev_priv, unsigned int n) in savage_bci_wait_fifo_s4() argument
93 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n; in savage_bci_wait_fifo_s4()
123 savage_bci_wait_event_shadow(drm_savage_private_t *dev_priv, uint16_t e) in savage_bci_wait_event_shadow() argument
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HDvia_dma.c64 dev_priv->dma_low +=8; \
72 dev_priv->dma_low += 8;
74 static void via_cmdbuf_start(drm_via_private_t * dev_priv);
75 static void via_cmdbuf_pause(drm_via_private_t * dev_priv);
76 static void via_cmdbuf_reset(drm_via_private_t * dev_priv);
77 static void via_cmdbuf_rewind(drm_via_private_t * dev_priv);
78 static int via_wait_idle(drm_via_private_t * dev_priv);
79 static void via_pad_cache(drm_via_private_t * dev_priv, int qwords);
85 static uint32_t via_cmdbuf_space(drm_via_private_t * dev_priv) in via_cmdbuf_space() argument
87 uint32_t agp_base = dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr; in via_cmdbuf_space()
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HDr600_cp.c71 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
75 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
77 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
79 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
96 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
100 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
103 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
105 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
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HDr128_cce.c89 drm_r128_private_t *dev_priv = dev->dev_private; in R128_READ_PLL() local
96 static void r128_status(drm_r128_private_t * dev_priv) in r128_status() argument
117 static int r128_do_pixcache_flush(drm_r128_private_t * dev_priv) in r128_do_pixcache_flush() argument
125 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_pixcache_flush()
138 static int r128_do_wait_for_fifo(drm_r128_private_t * dev_priv, int entries) in r128_do_wait_for_fifo() argument
142 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_fifo()
155 static int r128_do_wait_for_idle(drm_r128_private_t * dev_priv) in r128_do_wait_for_idle() argument
159 ret = r128_do_wait_for_fifo(dev_priv, 64); in r128_do_wait_for_idle()
163 for (i = 0; i < dev_priv->usec_timeout; i++) { in r128_do_wait_for_idle()
165 r128_do_pixcache_flush(dev_priv); in r128_do_wait_for_idle()
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HDmga_dma.c58 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv) in mga_do_wait_for_idle() argument
64 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_wait_for_idle()
80 static int mga_do_dma_reset(drm_mga_private_t * dev_priv) in mga_do_dma_reset() argument
82 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_do_dma_reset()
83 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_reset()
108 void mga_do_dma_flush(drm_mga_private_t * dev_priv) in mga_do_dma_flush() argument
110 drm_mga_primary_buffer_t *primary = &dev_priv->prim; in mga_do_dma_flush()
118 for (i = 0; i < dev_priv->usec_timeout; i++) { in mga_do_dma_flush()
130 tail = primary->tail + dev_priv->primary->offset; in mga_do_dma_flush()
154 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset); in mga_do_dma_flush()
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HDi915_irq.c60 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_enable_irq() argument
63 if ((dev_priv->irq_mask_reg & mask) != 0) { in i915_enable_irq()
64 dev_priv->irq_mask_reg &= ~mask; in i915_enable_irq()
65 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_enable_irq()
71 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) in i915_disable_irq() argument
74 if ((dev_priv->irq_mask_reg & mask) != mask) { in i915_disable_irq()
75 dev_priv->irq_mask_reg |= mask; in i915_disable_irq()
76 I915_WRITE(IMR, dev_priv->irq_mask_reg); in i915_disable_irq()
92 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) in i915_enable_pipestat() argument
94 if ((dev_priv->pipestat[pipe] & mask) != mask) { in i915_enable_pipestat()
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HDi915_dma.c44 drm_i915_private_t *dev_priv = dev->dev_private; in i915_wait_ring() local
45 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); in i915_wait_ring()
61 if (dev_priv->sarea_priv) in i915_wait_ring()
62 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; in i915_wait_ring()
84 drm_i915_private_t *dev_priv = dev->dev_private; in i915_init_phys_hws() local
88 dev_priv->status_page_dmah = in i915_init_phys_hws()
91 if (!dev_priv->status_page_dmah) { in i915_init_phys_hws()
95 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr; in i915_init_phys_hws()
96 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; in i915_init_phys_hws()
98 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); in i915_init_phys_hws()
[all …]
HDmach64_dma.c63 int mach64_do_wait_for_fifo(drm_mach64_private_t *dev_priv, int entries) in mach64_do_wait_for_fifo() argument
67 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_do_wait_for_fifo()
81 int mach64_do_wait_for_idle(drm_mach64_private_t *dev_priv) in mach64_do_wait_for_idle() argument
85 ret = mach64_do_wait_for_fifo(dev_priv, 16); in mach64_do_wait_for_idle()
89 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_do_wait_for_idle()
96 mach64_dump_ring_info(dev_priv); in mach64_do_wait_for_idle()
119 int mach64_wait_ring(drm_mach64_private_t *dev_priv, int n) in mach64_wait_ring() argument
121 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring; in mach64_wait_ring()
124 for (i = 0; i < dev_priv->usec_timeout; i++) { in mach64_wait_ring()
125 mach64_update_ring_snapshot(dev_priv); in mach64_wait_ring()
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HDvia_irq.c104 drm_via_private_t *dev_priv = dev->dev_private; in via_get_vblank_counter() local
108 return atomic_read(&dev_priv->vbl_received); in via_get_vblank_counter()
114 drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; in via_driver_irq_handler() local
118 drm_via_irq_t *cur_irq = dev_priv->via_irqs; in via_driver_irq_handler()
123 atomic_inc(&dev_priv->vbl_received); in via_driver_irq_handler()
124 if (!(atomic_read(&dev_priv->vbl_received) & 0x0F)) { in via_driver_irq_handler()
126 if (dev_priv->last_vblank_valid) { in via_driver_irq_handler()
127 dev_priv->usec_per_vblank = in via_driver_irq_handler()
129 &dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
131 dev_priv->last_vblank = cur_vblank; in via_driver_irq_handler()
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HDradeon_irq.c43 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_irq_set_state() local
46 dev_priv->irq_enable_reg |= mask; in radeon_irq_set_state()
48 dev_priv->irq_enable_reg &= ~mask; in radeon_irq_set_state()
51 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_irq_set_state()
56 drm_radeon_private_t *dev_priv = dev->dev_private; in r500_vbl_irq_set_state() local
59 dev_priv->r500_disp_irq_reg |= mask; in r500_vbl_irq_set_state()
61 dev_priv->r500_disp_irq_reg &= ~mask; in r500_vbl_irq_set_state()
64 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in r500_vbl_irq_set_state()
69 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_enable_vblank() local
71 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { in radeon_enable_vblank()
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HDvia_map.c34 drm_via_private_t *dev_priv = dev->dev_private; in via_do_init_map() local
38 dev_priv->sarea = drm_getsarea(dev); in via_do_init_map()
39 if (!dev_priv->sarea) { in via_do_init_map()
41 dev->dev_private = (void *)dev_priv; in via_do_init_map()
46 dev_priv->fb = drm_core_findmap(dev, init->fb_offset); in via_do_init_map()
47 if (!dev_priv->fb) { in via_do_init_map()
49 dev->dev_private = (void *)dev_priv; in via_do_init_map()
53 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset); in via_do_init_map()
54 if (!dev_priv->mmio) { in via_do_init_map()
56 dev->dev_private = (void *)dev_priv; in via_do_init_map()
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HDr600_blit.c1202 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
1217 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && in set_render_target()
1218 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { in set_render_target()
1260 cp_set_surface_sync(drm_radeon_private_t *dev_priv, in cp_set_surface_sync() argument
1284 drm_radeon_private_t *dev_priv = dev->dev_private; in set_shaders() local
1293 vs = (u32 *) ((char *)dev->agp_buffer_map->virtual + dev_priv->blit_vb->offset); in set_shaders()
1294 ps = (u32 *) ((char *)dev->agp_buffer_map->virtual + dev_priv->blit_vb->offset + 256); in set_shaders()
1303 dev_priv->blit_vb->used = 512; in set_shaders()
1305 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
1342 cp_set_surface_sync(dev_priv, in set_shaders()
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HDmga_state.c48 static void mga_emit_clip_rect(drm_mga_private_t * dev_priv, in mga_emit_clip_rect() argument
51 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_emit_clip_rect()
53 unsigned int pitch = dev_priv->front_pitch; in mga_emit_clip_rect()
60 if (dev_priv->chipset >= MGA_CARD_TYPE_G400) { in mga_emit_clip_rect()
73 static __inline__ void mga_g200_emit_context(drm_mga_private_t * dev_priv) in mga_g200_emit_context() argument
75 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g200_emit_context()
87 MGA_WFLAG, ctx->wflag, MGA_ZORG, dev_priv->depth_offset); in mga_g200_emit_context()
96 static __inline__ void mga_g400_emit_context(drm_mga_private_t * dev_priv) in mga_g400_emit_context() argument
98 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv; in mga_g400_emit_context()
112 MGA_ZORG, dev_priv->depth_offset); in mga_g400_emit_context()
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/trueos/sys/dev/drm2/i915/
HDi915_suspend.c37 struct drm_i915_private *dev_priv = dev->dev_private; in i915_pipe_enabled() local
54 struct drm_i915_private *dev_priv = dev->dev_private; in i915_save_palette() local
66 array = dev_priv->save_palette_a; in i915_save_palette()
68 array = dev_priv->save_palette_b; in i915_save_palette()
76 struct drm_i915_private *dev_priv = dev->dev_private; in i915_restore_palette() local
88 array = dev_priv->save_palette_a; in i915_restore_palette()
90 array = dev_priv->save_palette_b; in i915_restore_palette()
98 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_indexed() local
106 struct drm_i915_private *dev_priv = dev->dev_private; in i915_read_ar() local
115 struct drm_i915_private *dev_priv = dev->dev_private; in i915_write_ar() local
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HDi915_dma.c42 intel_ring_begin(LP_RING(dev_priv), (n))
45 intel_ring_emit(LP_RING(dev_priv), x)
48 intel_ring_advance(LP_RING(dev_priv))
56 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) in intel_read_legacy_status_page() argument
58 if (I915_NEED_GFX_HWS(dev_priv->dev)) in intel_read_legacy_status_page()
59 return ((volatile u32*)(dev_priv->dri1.gfx_hws_cpu_addr))[reg]; in intel_read_legacy_status_page()
61 return intel_read_status_page(LP_RING(dev_priv), reg); in intel_read_legacy_status_page()
64 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) argument
65 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) argument
70 drm_i915_private_t *dev_priv = dev->dev_private; in i915_update_dri1_breadcrumb() local
[all …]
HDi915_irq.c46 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) in ironlake_enable_display_irq() argument
48 if ((dev_priv->irq_mask & mask) != 0) { in ironlake_enable_display_irq()
49 dev_priv->irq_mask &= ~mask; in ironlake_enable_display_irq()
50 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_enable_display_irq()
56 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) in ironlake_disable_display_irq() argument
58 if ((dev_priv->irq_mask & mask) != mask) { in ironlake_disable_display_irq()
59 dev_priv->irq_mask |= mask; in ironlake_disable_display_irq()
60 I915_WRITE(DEIMR, dev_priv->irq_mask); in ironlake_disable_display_irq()
66 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) in i915_enable_pipestat() argument
68 if ((dev_priv->pipestat[pipe] & mask) != mask) { in i915_enable_pipestat()
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HDintel_pm.c63 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_disable_fbc() local
86 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_enable_fbc() local
95 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; in i8xx_enable_fbc()
128 struct drm_i915_private *dev_priv = dev->dev_private; in i8xx_fbc_enabled() local
136 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_enable_fbc() local
162 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_disable_fbc() local
177 struct drm_i915_private *dev_priv = dev->dev_private; in g4x_fbc_enabled() local
184 struct drm_i915_private *dev_priv = dev->dev_private; in sandybridge_blit_fbc_update() local
188 gen6_gt_force_wake_get(dev_priv); in sandybridge_blit_fbc_update()
199 gen6_gt_force_wake_put(dev_priv); in sandybridge_blit_fbc_update()
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HDintel_bios.c202 parse_lfp_panel_data(struct drm_i915_private *dev_priv, in parse_lfp_panel_data() argument
217 dev_priv->lvds_dither = lvds_options->pixel_dither; in parse_lfp_panel_data()
231 dev_priv->lvds_vbt = 1; in parse_lfp_panel_data()
242 dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode; in parse_lfp_panel_data()
264 dev_priv->lvds_downclock_avail = 1; in parse_lfp_panel_data()
265 dev_priv->lvds_downclock = downclock * 10; in parse_lfp_panel_data()
278 dev_priv->bios_lvds_val = fp_timing->lvds_reg_val; in parse_lfp_panel_data()
280 dev_priv->bios_lvds_val); in parse_lfp_panel_data()
287 parse_sdvo_panel_data(struct drm_i915_private *dev_priv, in parse_sdvo_panel_data() argument
319 dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode; in parse_sdvo_panel_data()
[all …]
HDi915_drv.c291 struct drm_i915_private *dev_priv; in i915_drm_freeze() local
294 dev_priv = dev->dev_private; in i915_drm_freeze()
317 dev_priv->modeset_on_lid = 0; in i915_drm_freeze()
346 struct drm_i915_private *dev_priv = dev->dev_private; in i915_drm_thaw() local
364 dev_priv->mm.suspended = 0; in i915_drm_thaw()
383 dev_priv->modeset_on_lid = 0; in i915_drm_thaw()
443 drm_i915_private_t *dev_priv; in i915_fb_helper_getinfo() local
448 dev_priv = dev->dev_private; in i915_fb_helper_getinfo()
449 ifbdev = dev_priv->fbdev; in i915_fb_helper_getinfo()
548 struct drm_i915_private *dev_priv; in intel_detect_pch() local
[all …]
/trueos/sys/dev/drm2/radeon/
HDradeon_cp.c67 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
69 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) in radeon_read_ring_rptr() argument
73 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_read_ring_rptr()
74 val = DRM_READ32(dev_priv->ring_rptr, off); in radeon_read_ring_rptr()
77 dev_priv->ring_rptr->handle) + in radeon_read_ring_rptr()
84 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) in radeon_get_ring_head() argument
86 if (dev_priv->writeback_works) in radeon_get_ring_head()
87 return radeon_read_ring_rptr(dev_priv, 0); in radeon_get_ring_head()
89 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_ring_head()
96 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) in radeon_write_ring_rptr() argument
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HDr600_cp.c110 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
114 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
116 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
118 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
135 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
139 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
141 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
142 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
144 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
147 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
[all …]
HDradeon_irq.c42 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_irq_set_state() local
45 dev_priv->irq_enable_reg |= mask; in radeon_irq_set_state()
47 dev_priv->irq_enable_reg &= ~mask; in radeon_irq_set_state()
50 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg); in radeon_irq_set_state()
55 drm_radeon_private_t *dev_priv = dev->dev_private; in r500_vbl_irq_set_state() local
58 dev_priv->r500_disp_irq_reg |= mask; in r500_vbl_irq_set_state()
60 dev_priv->r500_disp_irq_reg &= ~mask; in r500_vbl_irq_set_state()
63 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); in r500_vbl_irq_set_state()
68 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_enable_vblank() local
70 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { in radeon_enable_vblank()
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HDr600_blit.c48 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr) in set_render_target() argument
63 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) && in set_render_target()
64 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) { in set_render_target()
106 cp_set_surface_sync(drm_radeon_private_t *dev_priv, in cp_set_surface_sync() argument
130 drm_radeon_private_t *dev_priv = dev->dev_private; in set_shaders() local
139 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset); in set_shaders()
140 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256); in set_shaders()
147 dev_priv->blit_vb->used = 512; in set_shaders()
149 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset; in set_shaders()
186 cp_set_surface_sync(dev_priv, in set_shaders()
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