Lines Matching refs:dev_priv
71 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) in r600_do_wait_for_fifo() argument
75 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_fifo()
77 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_fifo()
79 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_fifo()
96 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) in r600_do_wait_for_idle() argument
100 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in r600_do_wait_for_idle()
102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in r600_do_wait_for_idle()
103 ret = r600_do_wait_for_fifo(dev_priv, 8); in r600_do_wait_for_idle()
105 ret = r600_do_wait_for_fifo(dev_priv, 16); in r600_do_wait_for_idle()
108 for (i = 0; i < dev_priv->usec_timeout; i++) { in r600_do_wait_for_idle()
149 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_page_table_init() local
150 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; in r600_page_table_init()
204 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_flush_gart_range() local
206 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_flush_gart_range()
207 …RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_si… in r600_vm_flush_gart_range()
219 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_vm_init() local
225 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
226 …RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
275 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r600_vm_init()
276 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r600_vm_init()
277 …RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r600_vm_init()
283 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) in r600_cp_load_microcode() argument
289 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_cp_load_microcode()
330 r600_do_cp_stop(dev_priv); in r600_cp_load_microcode()
361 drm_radeon_private_t *dev_priv = dev->dev_private; in r700_vm_init() local
367 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
368 …RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
404 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); in r700_vm_init()
405 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); in r700_vm_init()
406 …RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size … in r700_vm_init()
412 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) in r700_cp_load_microcode() argument
418 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_cp_load_microcode()
439 r600_do_cp_stop(dev_priv); in r700_cp_load_microcode()
466 static void r600_test_writeback(drm_radeon_private_t *dev_priv) in r600_test_writeback() argument
471 dev_priv->writeback_works = 0; in r600_test_writeback()
476 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); in r600_test_writeback()
480 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { in r600_test_writeback()
483 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); in r600_test_writeback()
489 if (tmp < dev_priv->usec_timeout) { in r600_test_writeback()
490 dev_priv->writeback_works = 1; in r600_test_writeback()
493 dev_priv->writeback_works = 0; in r600_test_writeback()
497 dev_priv->writeback_works = 0; in r600_test_writeback()
501 if (!dev_priv->writeback_works) { in r600_test_writeback()
511 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_engine_reset() local
536 r600_do_cp_reset(dev_priv); in r600_do_engine_reset()
539 dev_priv->cp_running = 0; in r600_do_engine_reset()
668 drm_radeon_private_t *dev_priv) in r600_gfx_init() argument
692 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
694 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
695 dev_priv->r600_max_tile_pipes = 8; in r600_gfx_init()
696 dev_priv->r600_max_simds = 4; in r600_gfx_init()
697 dev_priv->r600_max_backends = 4; in r600_gfx_init()
698 dev_priv->r600_max_gprs = 256; in r600_gfx_init()
699 dev_priv->r600_max_threads = 192; in r600_gfx_init()
700 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
701 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
702 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
703 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
704 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
705 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
706 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
710 dev_priv->r600_max_pipes = 2; in r600_gfx_init()
711 dev_priv->r600_max_tile_pipes = 2; in r600_gfx_init()
712 dev_priv->r600_max_simds = 3; in r600_gfx_init()
713 dev_priv->r600_max_backends = 1; in r600_gfx_init()
714 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
715 dev_priv->r600_max_threads = 192; in r600_gfx_init()
716 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
717 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
718 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
719 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
720 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
721 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
722 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
728 dev_priv->r600_max_pipes = 1; in r600_gfx_init()
729 dev_priv->r600_max_tile_pipes = 1; in r600_gfx_init()
730 dev_priv->r600_max_simds = 2; in r600_gfx_init()
731 dev_priv->r600_max_backends = 1; in r600_gfx_init()
732 dev_priv->r600_max_gprs = 128; in r600_gfx_init()
733 dev_priv->r600_max_threads = 192; in r600_gfx_init()
734 dev_priv->r600_max_stack_entries = 128; in r600_gfx_init()
735 dev_priv->r600_max_hw_contexts = 4; in r600_gfx_init()
736 dev_priv->r600_max_gs_threads = 4; in r600_gfx_init()
737 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
738 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
739 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
740 dev_priv->r600_sq_num_cf_insts = 1; in r600_gfx_init()
743 dev_priv->r600_max_pipes = 4; in r600_gfx_init()
744 dev_priv->r600_max_tile_pipes = 4; in r600_gfx_init()
745 dev_priv->r600_max_simds = 4; in r600_gfx_init()
746 dev_priv->r600_max_backends = 4; in r600_gfx_init()
747 dev_priv->r600_max_gprs = 192; in r600_gfx_init()
748 dev_priv->r600_max_threads = 192; in r600_gfx_init()
749 dev_priv->r600_max_stack_entries = 256; in r600_gfx_init()
750 dev_priv->r600_max_hw_contexts = 8; in r600_gfx_init()
751 dev_priv->r600_max_gs_threads = 16; in r600_gfx_init()
752 dev_priv->r600_sx_max_export_size = 128; in r600_gfx_init()
753 dev_priv->r600_sx_max_export_pos_size = 16; in r600_gfx_init()
754 dev_priv->r600_sx_max_export_smx_size = 128; in r600_gfx_init()
755 dev_priv->r600_sq_num_cf_insts = 2; in r600_gfx_init()
777 switch (dev_priv->r600_max_tile_pipes) { in r600_gfx_init()
810 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, in r600_gfx_init()
811 dev_priv->r600_max_backends, in r600_gfx_init()
812 (0xff << dev_priv->r600_max_backends) & 0xff); in r600_gfx_init()
816 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); in r600_gfx_init()
818 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); in r600_gfx_init()
821 …R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_M… in r600_gfx_init()
848 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) in r600_gfx_init()
853 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) in r600_gfx_init()
857 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
858 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
859 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
860 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
861 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
878 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
879 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
880 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
886 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || in r600_gfx_init()
887 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { in r600_gfx_init()
908 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { in r600_gfx_init()
922 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { in r600_gfx_init()
942 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || in r600_gfx_init()
943 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { in r600_gfx_init()
957 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { in r600_gfx_init()
980 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || in r600_gfx_init()
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || in r600_gfx_init()
982 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || in r600_gfx_init()
983 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) in r600_gfx_init()
1018 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1037 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r600_gfx_init()
1069 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r600_gfx_init()
1214 drm_radeon_private_t *dev_priv) in r700_gfx_init() argument
1235 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1237 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1238 dev_priv->r600_max_tile_pipes = 8; in r700_gfx_init()
1239 dev_priv->r600_max_simds = 10; in r700_gfx_init()
1240 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1241 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1242 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1243 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1244 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1245 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1246 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1247 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1248 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1249 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1251 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1252 dev_priv->r700_sc_prim_fifo_size = 0xF9; in r700_gfx_init()
1253 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1254 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1257 dev_priv->r600_max_pipes = 4; in r700_gfx_init()
1258 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1259 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1260 dev_priv->r600_max_backends = 4; in r700_gfx_init()
1261 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1262 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1263 dev_priv->r600_max_stack_entries = 512; in r700_gfx_init()
1264 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1265 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1266 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1267 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1268 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1269 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1271 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1272 dev_priv->r700_sc_prim_fifo_size = 0x100; in r700_gfx_init()
1273 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1274 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1276 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1277 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1278 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1282 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1283 dev_priv->r600_max_tile_pipes = 4; in r700_gfx_init()
1284 dev_priv->r600_max_simds = 8; in r700_gfx_init()
1285 dev_priv->r600_max_backends = 2; in r700_gfx_init()
1286 dev_priv->r600_max_gprs = 128; in r700_gfx_init()
1287 dev_priv->r600_max_threads = 248; in r700_gfx_init()
1288 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1289 dev_priv->r600_max_hw_contexts = 8; in r700_gfx_init()
1290 dev_priv->r600_max_gs_threads = 16 * 2; in r700_gfx_init()
1291 dev_priv->r600_sx_max_export_size = 256; in r700_gfx_init()
1292 dev_priv->r600_sx_max_export_pos_size = 32; in r700_gfx_init()
1293 dev_priv->r600_sx_max_export_smx_size = 224; in r700_gfx_init()
1294 dev_priv->r600_sq_num_cf_insts = 2; in r700_gfx_init()
1296 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1297 dev_priv->r700_sc_prim_fifo_size = 0xf9; in r700_gfx_init()
1298 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1299 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1301 if (dev_priv->r600_sx_max_export_pos_size > 16) { in r700_gfx_init()
1302 dev_priv->r600_sx_max_export_pos_size -= 16; in r700_gfx_init()
1303 dev_priv->r600_sx_max_export_smx_size += 16; in r700_gfx_init()
1307 dev_priv->r600_max_pipes = 2; in r700_gfx_init()
1308 dev_priv->r600_max_tile_pipes = 2; in r700_gfx_init()
1309 dev_priv->r600_max_simds = 2; in r700_gfx_init()
1310 dev_priv->r600_max_backends = 1; in r700_gfx_init()
1311 dev_priv->r600_max_gprs = 256; in r700_gfx_init()
1312 dev_priv->r600_max_threads = 192; in r700_gfx_init()
1313 dev_priv->r600_max_stack_entries = 256; in r700_gfx_init()
1314 dev_priv->r600_max_hw_contexts = 4; in r700_gfx_init()
1315 dev_priv->r600_max_gs_threads = 8 * 2; in r700_gfx_init()
1316 dev_priv->r600_sx_max_export_size = 128; in r700_gfx_init()
1317 dev_priv->r600_sx_max_export_pos_size = 16; in r700_gfx_init()
1318 dev_priv->r600_sx_max_export_smx_size = 112; in r700_gfx_init()
1319 dev_priv->r600_sq_num_cf_insts = 1; in r700_gfx_init()
1321 dev_priv->r700_sx_num_of_sets = 7; in r700_gfx_init()
1322 dev_priv->r700_sc_prim_fifo_size = 0x40; in r700_gfx_init()
1323 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; in r700_gfx_init()
1324 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; in r700_gfx_init()
1346 switch (dev_priv->r600_max_tile_pipes) { in r700_gfx_init()
1363 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) in r700_gfx_init()
1382 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, in r700_gfx_init()
1383 dev_priv->r600_max_backends, in r700_gfx_init()
1384 (0xff << dev_priv->r600_max_backends) & 0xff); in r700_gfx_init()
1388 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); in r700_gfx_init()
1390 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); in r700_gfx_init()
1393 …R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_M… in r700_gfx_init()
1431 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); in r700_gfx_init()
1439 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) in r700_gfx_init()
1447 …RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_si… in r700_gfx_init()
1448 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | in r700_gfx_init()
1449 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); in r700_gfx_init()
1451 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | in r700_gfx_init()
1452 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | in r700_gfx_init()
1453 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); in r700_gfx_init()
1465 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | in r700_gfx_init()
1468 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1496 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1502 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1503 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | in r700_gfx_init()
1504 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); in r700_gfx_init()
1506 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | in r700_gfx_init()
1507 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); in r700_gfx_init()
1509 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | in r700_gfx_init()
1510 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | in r700_gfx_init()
1511 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); in r700_gfx_init()
1512 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) in r700_gfx_init()
1513 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); in r700_gfx_init()
1515 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); in r700_gfx_init()
1518 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1519 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1521 …RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_e… in r700_gfx_init()
1522 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); in r700_gfx_init()
1524 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1525 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1526 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | in r700_gfx_init()
1527 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); in r700_gfx_init()
1541 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) in r700_gfx_init()
1548 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in r700_gfx_init()
1561 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; in r700_gfx_init()
1608 drm_radeon_private_t *dev_priv, in r600_cp_init_ring_buffer() argument
1614 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_cp_init_ring_buffer()
1615 r700_gfx_init(dev, dev_priv); in r600_cp_init_ring_buffer()
1617 r600_gfx_init(dev, dev_priv); in r600_cp_init_ring_buffer()
1630 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1631 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1635 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1636 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1649 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1650 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1655 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1656 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1662 SET_RING_HEAD(dev_priv, 0); in r600_cp_init_ring_buffer()
1663 dev_priv->ring.tail = 0; in r600_cp_init_ring_buffer()
1666 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1667 rptr_addr = dev_priv->ring_rptr->offset in r600_cp_init_ring_buffer()
1669 dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1673 rptr_addr = dev_priv->ring_rptr->offset - dev->sg->vaddr + in r600_cp_init_ring_buffer()
1674 dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1684 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1685 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1688 (dev_priv->ring.rptr_update_l2qw << 8) | in r600_cp_init_ring_buffer()
1689 dev_priv->ring.size_l2qw); in r600_cp_init_ring_buffer()
1693 if (dev_priv->flags & RADEON_IS_AGP) { in r600_cp_init_ring_buffer()
1695 radeon_write_agp_base(dev_priv, dev->agp->base); in r600_cp_init_ring_buffer()
1698 radeon_write_agp_location(dev_priv, in r600_cp_init_ring_buffer()
1699 (((dev_priv->gart_vm_start - 1 + in r600_cp_init_ring_buffer()
1700 dev_priv->gart_size) & 0xffff0000) | in r600_cp_init_ring_buffer()
1701 (dev_priv->gart_vm_start >> 16))); in r600_cp_init_ring_buffer()
1703 ring_start = (dev_priv->cp_ring->offset in r600_cp_init_ring_buffer()
1705 + dev_priv->gart_vm_start); in r600_cp_init_ring_buffer()
1708 ring_start = dev_priv->cp_ring->offset - dev->sg->vaddr + in r600_cp_init_ring_buffer()
1709 dev_priv->gart_vm_start; in r600_cp_init_ring_buffer()
1739 radeon_enable_bm(dev_priv); in r600_cp_init_ring_buffer()
1741 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); in r600_cp_init_ring_buffer()
1744 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); in r600_cp_init_ring_buffer()
1747 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); in r600_cp_init_ring_buffer()
1751 if (dev_priv->sarea_priv) { in r600_cp_init_ring_buffer()
1752 dev_priv->sarea_priv->last_frame = 0; in r600_cp_init_ring_buffer()
1753 dev_priv->sarea_priv->last_dispatch = 0; in r600_cp_init_ring_buffer()
1754 dev_priv->sarea_priv->last_clear = 0; in r600_cp_init_ring_buffer()
1757 r600_do_wait_for_idle(dev_priv); in r600_cp_init_ring_buffer()
1763 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_cleanup_cp() local
1774 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_cleanup_cp()
1775 if (dev_priv->cp_ring != NULL) { in r600_do_cleanup_cp()
1776 drm_core_ioremapfree(dev_priv->cp_ring, dev); in r600_do_cleanup_cp()
1777 dev_priv->cp_ring = NULL; in r600_do_cleanup_cp()
1779 if (dev_priv->ring_rptr != NULL) { in r600_do_cleanup_cp()
1780 drm_core_ioremapfree(dev_priv->ring_rptr, dev); in r600_do_cleanup_cp()
1781 dev_priv->ring_rptr = NULL; in r600_do_cleanup_cp()
1791 if (dev_priv->gart_info.bus_addr) in r600_do_cleanup_cp()
1792 r600_page_table_cleanup(dev, &dev_priv->gart_info); in r600_do_cleanup_cp()
1794 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { in r600_do_cleanup_cp()
1795 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); in r600_do_cleanup_cp()
1796 dev_priv->gart_info.addr = 0; in r600_do_cleanup_cp()
1800 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); in r600_do_cleanup_cp()
1808 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_init_cp() local
1813 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { in r600_do_init_cp()
1819 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { in r600_do_init_cp()
1821 dev_priv->flags &= ~RADEON_IS_AGP; in r600_do_init_cp()
1826 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) in r600_do_init_cp()
1829 dev_priv->flags |= RADEON_IS_AGP; in r600_do_init_cp()
1832 dev_priv->usec_timeout = init->usec_timeout; in r600_do_init_cp()
1833 if (dev_priv->usec_timeout < 1 || in r600_do_init_cp()
1834 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { in r600_do_init_cp()
1842 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; in r600_do_init_cp()
1844 dev_priv->do_boxes = 0; in r600_do_init_cp()
1845 dev_priv->cp_mode = init->cp_mode; in r600_do_init_cp()
1860 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; in r600_do_init_cp()
1864 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; in r600_do_init_cp()
1867 dev_priv->front_offset = init->front_offset; in r600_do_init_cp()
1868 dev_priv->front_pitch = init->front_pitch; in r600_do_init_cp()
1869 dev_priv->back_offset = init->back_offset; in r600_do_init_cp()
1870 dev_priv->back_pitch = init->back_pitch; in r600_do_init_cp()
1872 dev_priv->ring_offset = init->ring_offset; in r600_do_init_cp()
1873 dev_priv->ring_rptr_offset = init->ring_rptr_offset; in r600_do_init_cp()
1874 dev_priv->buffers_offset = init->buffers_offset; in r600_do_init_cp()
1875 dev_priv->gart_textures_offset = init->gart_textures_offset; in r600_do_init_cp()
1877 dev_priv->sarea = drm_getsarea(dev); in r600_do_init_cp()
1878 if (!dev_priv->sarea) { in r600_do_init_cp()
1884 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); in r600_do_init_cp()
1885 if (!dev_priv->cp_ring) { in r600_do_init_cp()
1890 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); in r600_do_init_cp()
1891 if (!dev_priv->ring_rptr) { in r600_do_init_cp()
1905 dev_priv->gart_textures = in r600_do_init_cp()
1907 if (!dev_priv->gart_textures) { in r600_do_init_cp()
1914 dev_priv->sarea_priv = in r600_do_init_cp()
1915 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual + in r600_do_init_cp()
1920 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
1921 drm_core_ioremap_wc(dev_priv->cp_ring, dev); in r600_do_init_cp()
1922 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); in r600_do_init_cp()
1924 if (!dev_priv->cp_ring->virtual || in r600_do_init_cp()
1925 !dev_priv->ring_rptr->virtual || in r600_do_init_cp()
1934 dev_priv->cp_ring->virtual = in r600_do_init_cp()
1935 (void *)dev_priv->cp_ring->offset; in r600_do_init_cp()
1936 dev_priv->ring_rptr->virtual = in r600_do_init_cp()
1937 (void *)dev_priv->ring_rptr->offset; in r600_do_init_cp()
1942 dev_priv->cp_ring->virtual); in r600_do_init_cp()
1944 dev_priv->ring_rptr->virtual); in r600_do_init_cp()
1949 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; in r600_do_init_cp()
1950 dev_priv->fb_size = in r600_do_init_cp()
1951 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) in r600_do_init_cp()
1952 - dev_priv->fb_location; in r600_do_init_cp()
1954 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | in r600_do_init_cp()
1955 ((dev_priv->front_offset in r600_do_init_cp()
1956 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
1958 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | in r600_do_init_cp()
1959 ((dev_priv->back_offset in r600_do_init_cp()
1960 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
1962 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | in r600_do_init_cp()
1963 ((dev_priv->depth_offset in r600_do_init_cp()
1964 + dev_priv->fb_location) >> 10)); in r600_do_init_cp()
1966 dev_priv->gart_size = init->gart_size; in r600_do_init_cp()
1969 if (dev_priv->new_memmap) { in r600_do_init_cp()
1980 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
1983 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in r600_do_init_cp()
1984 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { in r600_do_init_cp()
1993 base = dev_priv->fb_location + dev_priv->fb_size; in r600_do_init_cp()
1994 if (base < dev_priv->fb_location || in r600_do_init_cp()
1995 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in r600_do_init_cp()
1996 base = dev_priv->fb_location in r600_do_init_cp()
1997 - dev_priv->gart_size; in r600_do_init_cp()
1999 dev_priv->gart_vm_start = base & 0xffc00000u; in r600_do_init_cp()
2000 if (dev_priv->gart_vm_start != base) in r600_do_init_cp()
2002 base, dev_priv->gart_vm_start); in r600_do_init_cp()
2007 if (dev_priv->flags & RADEON_IS_AGP) in r600_do_init_cp()
2008 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in r600_do_init_cp()
2010 + dev_priv->gart_vm_start); in r600_do_init_cp()
2013 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset - in r600_do_init_cp()
2014 dev->sg->vaddr + dev_priv->gart_vm_start; in r600_do_init_cp()
2017 (unsigned int) dev_priv->fb_location, in r600_do_init_cp()
2018 (unsigned int) dev_priv->fb_size); in r600_do_init_cp()
2019 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); in r600_do_init_cp()
2021 (unsigned int) dev_priv->gart_vm_start); in r600_do_init_cp()
2023 dev_priv->gart_buffers_offset); in r600_do_init_cp()
2025 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual; in r600_do_init_cp()
2026 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual in r600_do_init_cp()
2028 dev_priv->ring.size = init->ring_size; in r600_do_init_cp()
2029 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); in r600_do_init_cp()
2031 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; in r600_do_init_cp()
2032 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); in r600_do_init_cp()
2034 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; in r600_do_init_cp()
2035 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); in r600_do_init_cp()
2037 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r600_do_init_cp()
2039 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; in r600_do_init_cp()
2042 if (dev_priv->flags & RADEON_IS_AGP) { in r600_do_init_cp()
2047 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); in r600_do_init_cp()
2049 if (!dev_priv->pcigart_offset_set) { in r600_do_init_cp()
2055 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); in r600_do_init_cp()
2057 dev_priv->gart_info.bus_addr = in r600_do_init_cp()
2058 dev_priv->pcigart_offset + dev_priv->fb_location; in r600_do_init_cp()
2059 dev_priv->gart_info.mapping.offset = in r600_do_init_cp()
2060 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in r600_do_init_cp()
2061 dev_priv->gart_info.mapping.size = in r600_do_init_cp()
2062 dev_priv->gart_info.table_size; in r600_do_init_cp()
2064 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); in r600_do_init_cp()
2065 if (!dev_priv->gart_info.mapping.virtual) { in r600_do_init_cp()
2071 dev_priv->gart_info.addr = in r600_do_init_cp()
2072 dev_priv->gart_info.mapping.virtual; in r600_do_init_cp()
2075 dev_priv->gart_info.addr, in r600_do_init_cp()
2076 dev_priv->pcigart_offset); in r600_do_init_cp()
2084 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2090 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) in r600_do_init_cp()
2091 r700_cp_load_microcode(dev_priv); in r600_do_init_cp()
2093 r600_cp_load_microcode(dev_priv); in r600_do_init_cp()
2095 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); in r600_do_init_cp()
2097 dev_priv->last_buf = 0; in r600_do_init_cp()
2100 r600_test_writeback(dev_priv); in r600_do_init_cp()
2109 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_do_resume_cp() local
2112 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { in r600_do_resume_cp()
2114 r700_cp_load_microcode(dev_priv); in r600_do_resume_cp()
2117 r600_cp_load_microcode(dev_priv); in r600_do_resume_cp()
2119 r600_cp_init_ring_buffer(dev, dev_priv, file_priv); in r600_do_resume_cp()
2127 int r600_do_cp_idle(drm_radeon_private_t *dev_priv) in r600_do_cp_idle() argument
2143 return r600_do_wait_for_idle(dev_priv); in r600_do_cp_idle()
2148 void r600_do_cp_start(drm_radeon_private_t *dev_priv) in r600_do_cp_start() argument
2157 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) in r600_do_cp_start()
2161 OUT_RING((dev_priv->r600_max_hw_contexts - 1)); in r600_do_cp_start()
2172 dev_priv->cp_running = 1; in r600_do_cp_start()
2176 void r600_do_cp_reset(drm_radeon_private_t *dev_priv) in r600_do_cp_reset() argument
2183 SET_RING_HEAD(dev_priv, cur_read_ptr); in r600_do_cp_reset()
2184 dev_priv->ring.tail = cur_read_ptr; in r600_do_cp_reset()
2187 void r600_do_cp_stop(drm_radeon_private_t *dev_priv) in r600_do_cp_stop() argument
2197 dev_priv->cp_running = 0; in r600_do_cp_stop()
2203 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_indirect() local
2207 unsigned long offset = (dev_priv->gart_buffers_offset in r600_cp_dispatch_indirect()
2239 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_swap() local
2240 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; in r600_cp_dispatch_swap()
2248 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) in r600_cp_dispatch_swap()
2253 if (dev_priv->sarea_priv->pfCurrentPage == 0) { in r600_cp_dispatch_swap()
2254 src_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2255 dst_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2256 src = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2257 dst = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2259 src_pitch = dev_priv->front_pitch; in r600_cp_dispatch_swap()
2260 dst_pitch = dev_priv->back_pitch; in r600_cp_dispatch_swap()
2261 src = dev_priv->front_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2262 dst = dev_priv->back_offset + dev_priv->fb_location; in r600_cp_dispatch_swap()
2288 dev_priv->sarea_priv->last_frame++; in r600_cp_dispatch_swap()
2291 R600_FRAME_AGE(dev_priv->sarea_priv->last_frame); in r600_cp_dispatch_swap()
2300 drm_radeon_private_t *dev_priv = dev->dev_private; in r600_cp_dispatch_texture() local
2307 if (!radeon_check_offset(dev_priv, tex->offset)) { in r600_cp_dispatch_texture()
2313 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { in r600_cp_dispatch_texture()
2354 src_offset = dev_priv->gart_buffers_offset + buf->offset; in r600_cp_dispatch_texture()