Lines Matching refs:dev_priv
46 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
48 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off) in radeon_read_ring_rptr() argument
52 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_read_ring_rptr()
53 val = DRM_READ32(dev_priv->ring_rptr, off); in radeon_read_ring_rptr()
56 dev_priv->ring_rptr->virtual) + in radeon_read_ring_rptr()
63 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv) in radeon_get_ring_head() argument
65 if (dev_priv->writeback_works) in radeon_get_ring_head()
66 return radeon_read_ring_rptr(dev_priv, 0); in radeon_get_ring_head()
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_ring_head()
75 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val) in radeon_write_ring_rptr() argument
77 if (dev_priv->flags & RADEON_IS_AGP) in radeon_write_ring_rptr()
78 DRM_WRITE32(dev_priv->ring_rptr, off, val); in radeon_write_ring_rptr()
80 *(((volatile u32 *) dev_priv->ring_rptr->virtual) + in radeon_write_ring_rptr()
84 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val) in radeon_set_ring_head() argument
86 radeon_write_ring_rptr(dev_priv, 0, val); in radeon_set_ring_head()
89 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) in radeon_get_scratch() argument
91 if (dev_priv->writeback_works) { in radeon_get_scratch()
92 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_scratch()
93 return radeon_read_ring_rptr(dev_priv, in radeon_get_scratch()
96 return radeon_read_ring_rptr(dev_priv, in radeon_get_scratch()
99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_get_scratch()
106 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_MM() argument
111 ret = DRM_READ32(dev_priv->mmio, addr); in RADEON_READ_MM()
113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); in RADEON_READ_MM()
114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); in RADEON_READ_MM()
120 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in R500_READ_MCIND() argument
129 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS480_READ_MCIND() argument
138 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS690_READ_MCIND() argument
147 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in RS600_READ_MCIND() argument
156 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) in IGP_READ_MCIND() argument
158 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in IGP_READ_MCIND()
159 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in IGP_READ_MCIND()
160 return RS690_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
161 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in IGP_READ_MCIND()
162 return RS600_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
164 return RS480_READ_MCIND(dev_priv, addr); in IGP_READ_MCIND()
167 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv) in radeon_read_fb_location() argument
170 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_read_fb_location()
172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_read_fb_location()
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_read_fb_location()
175 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION); in radeon_read_fb_location()
176 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_read_fb_location()
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_read_fb_location()
178 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION); in radeon_read_fb_location()
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_read_fb_location()
180 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION); in radeon_read_fb_location()
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_read_fb_location()
182 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION); in radeon_read_fb_location()
187 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc) in radeon_write_fb_location() argument
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_write_fb_location()
191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_write_fb_location()
193 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_write_fb_location()
195 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_fb_location()
196 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_write_fb_location()
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_write_fb_location()
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_write_fb_location()
206 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc) in radeon_write_agp_location() argument
209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { in radeon_write_agp_location()
212 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_write_agp_location()
215 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) in radeon_write_agp_location()
217 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_agp_location()
218 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_write_agp_location()
220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_write_agp_location()
222 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) in radeon_write_agp_location()
228 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base) in radeon_write_agp_base() argument
235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) in radeon_write_agp_base()
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_write_agp_base()
239 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) { in radeon_write_agp_base()
242 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_write_agp_base()
243 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { in radeon_write_agp_base()
246 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { in radeon_write_agp_base()
249 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) { in radeon_write_agp_base()
252 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || in radeon_write_agp_base()
253 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { in radeon_write_agp_base()
258 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200) in radeon_write_agp_base()
263 void radeon_enable_bm(struct drm_radeon_private *dev_priv) in radeon_enable_bm() argument
267 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_enable_bm()
268 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { in radeon_enable_bm()
272 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) || in radeon_enable_bm()
273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || in radeon_enable_bm()
274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || in radeon_enable_bm()
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) { in radeon_enable_bm()
284 drm_radeon_private_t *dev_priv = dev->dev_private; in RADEON_READ_PLL() local
290 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr) in RADEON_READ_PCIE() argument
297 static void radeon_status(drm_radeon_private_t * dev_priv) in radeon_status() argument
323 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv) in radeon_do_pixcache_flush() argument
328 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_pixcache_flush()
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { in radeon_do_pixcache_flush()
335 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_pixcache_flush()
349 radeon_status(dev_priv); in radeon_do_pixcache_flush()
354 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries) in radeon_do_wait_for_fifo() argument
358 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_wait_for_fifo()
360 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_fifo()
373 radeon_status(dev_priv); in radeon_do_wait_for_fifo()
378 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv) in radeon_do_wait_for_idle() argument
382 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_do_wait_for_idle()
384 ret = radeon_do_wait_for_fifo(dev_priv, 64); in radeon_do_wait_for_idle()
388 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_do_wait_for_idle()
391 radeon_do_pixcache_flush(dev_priv); in radeon_do_wait_for_idle()
402 radeon_status(dev_priv); in radeon_do_wait_for_idle()
407 static void radeon_init_pipes(drm_radeon_private_t *dev_priv) in radeon_init_pipes() argument
411 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) { in radeon_init_pipes()
414 dev_priv->num_z_pipes = 2; in radeon_init_pipes()
416 dev_priv->num_z_pipes = 1; in radeon_init_pipes()
418 dev_priv->num_z_pipes = 1; in radeon_init_pipes()
421 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) { in radeon_init_pipes()
423 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; in radeon_init_pipes()
426 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) || in radeon_init_pipes()
427 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) { in radeon_init_pipes()
428 dev_priv->num_gb_pipes = 2; in radeon_init_pipes()
431 dev_priv->num_gb_pipes = 1; in radeon_init_pipes()
434 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes); in radeon_init_pipes()
438 switch (dev_priv->num_gb_pipes) { in radeon_init_pipes()
446 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) { in radeon_init_pipes()
448 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1)); in radeon_init_pipes()
451 radeon_do_wait_for_idle(dev_priv); in radeon_init_pipes()
465 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) in radeon_cp_load_microcode() argument
472 switch (dev_priv->flags & RADEON_FAMILY_MASK) { in radeon_cp_load_microcode()
525 radeon_do_wait_for_idle(dev_priv); in radeon_cp_load_microcode()
539 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv) in radeon_do_cp_flush() argument
552 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv) in radeon_do_cp_idle() argument
566 return radeon_do_wait_for_idle(dev_priv); in radeon_do_cp_idle()
571 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv) in radeon_do_cp_start() argument
576 radeon_do_wait_for_idle(dev_priv); in radeon_do_cp_start()
578 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()
580 dev_priv->cp_running = 1; in radeon_do_cp_start()
595 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED; in radeon_do_cp_start()
602 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv) in radeon_do_cp_reset() argument
609 SET_RING_HEAD(dev_priv, cur_read_ptr); in radeon_do_cp_reset()
610 dev_priv->ring.tail = cur_read_ptr; in radeon_do_cp_reset()
617 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv) in radeon_do_cp_stop() argument
623 dev_priv->cp_running = 0; in radeon_do_cp_stop()
630 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_engine_reset() local
634 radeon_do_pixcache_flush(dev_priv); in radeon_do_engine_reset()
636 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { in radeon_do_engine_reset()
671 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) { in radeon_do_engine_reset()
678 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300) in radeon_do_engine_reset()
679 radeon_init_pipes(dev_priv); in radeon_do_engine_reset()
682 radeon_do_cp_reset(dev_priv); in radeon_do_engine_reset()
685 dev_priv->cp_running = 0; in radeon_do_engine_reset()
694 drm_radeon_private_t *dev_priv, in radeon_cp_init_ring_buffer() argument
704 if (!dev_priv->new_memmap) in radeon_cp_init_ring_buffer()
705 radeon_write_fb_location(dev_priv, in radeon_cp_init_ring_buffer()
706 ((dev_priv->gart_vm_start - 1) & 0xffff0000) in radeon_cp_init_ring_buffer()
707 | (dev_priv->fb_location >> 16)); in radeon_cp_init_ring_buffer()
710 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_cp_init_ring_buffer()
711 radeon_write_agp_base(dev_priv, dev->agp->base); in radeon_cp_init_ring_buffer()
713 radeon_write_agp_location(dev_priv, in radeon_cp_init_ring_buffer()
714 (((dev_priv->gart_vm_start - 1 + in radeon_cp_init_ring_buffer()
715 dev_priv->gart_size) & 0xffff0000) | in radeon_cp_init_ring_buffer()
716 (dev_priv->gart_vm_start >> 16))); in radeon_cp_init_ring_buffer()
718 ring_start = (dev_priv->cp_ring->offset in radeon_cp_init_ring_buffer()
720 + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
723 ring_start = (dev_priv->cp_ring->offset - dev->sg->vaddr + in radeon_cp_init_ring_buffer()
724 dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
734 SET_RING_HEAD(dev_priv, cur_read_ptr); in radeon_cp_init_ring_buffer()
735 dev_priv->ring.tail = cur_read_ptr; in radeon_cp_init_ring_buffer()
738 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_cp_init_ring_buffer()
740 dev_priv->ring_rptr->offset in radeon_cp_init_ring_buffer()
741 - dev->agp->base + dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
746 dev_priv->ring_rptr->offset - dev->sg->vaddr + in radeon_cp_init_ring_buffer()
747 dev_priv->gart_vm_start); in radeon_cp_init_ring_buffer()
754 (dev_priv->ring.fetch_size_l2ow << 18) | in radeon_cp_init_ring_buffer()
755 (dev_priv->ring.rptr_update_l2qw << 8) | in radeon_cp_init_ring_buffer()
756 dev_priv->ring.size_l2qw); in radeon_cp_init_ring_buffer()
759 (dev_priv->ring.fetch_size_l2ow << 18) | in radeon_cp_init_ring_buffer()
760 (dev_priv->ring.rptr_update_l2qw << 8) | in radeon_cp_init_ring_buffer()
761 dev_priv->ring.size_l2qw); in radeon_cp_init_ring_buffer()
777 radeon_enable_bm(dev_priv); in radeon_cp_init_ring_buffer()
779 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0); in radeon_cp_init_ring_buffer()
782 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); in radeon_cp_init_ring_buffer()
785 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0); in radeon_cp_init_ring_buffer()
789 if (dev_priv->sarea_priv) { in radeon_cp_init_ring_buffer()
790 dev_priv->sarea_priv->last_frame = 0; in radeon_cp_init_ring_buffer()
791 dev_priv->sarea_priv->last_dispatch = 0; in radeon_cp_init_ring_buffer()
792 dev_priv->sarea_priv->last_clear = 0; in radeon_cp_init_ring_buffer()
795 radeon_do_wait_for_idle(dev_priv); in radeon_cp_init_ring_buffer()
806 static void radeon_test_writeback(drm_radeon_private_t * dev_priv) in radeon_test_writeback() argument
811 dev_priv->writeback_works = 0; in radeon_test_writeback()
816 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0); in radeon_test_writeback()
820 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { in radeon_test_writeback()
823 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1)); in radeon_test_writeback()
829 if (tmp < dev_priv->usec_timeout) { in radeon_test_writeback()
830 dev_priv->writeback_works = 1; in radeon_test_writeback()
833 dev_priv->writeback_works = 0; in radeon_test_writeback()
837 dev_priv->writeback_works = 0; in radeon_test_writeback()
841 if (!dev_priv->writeback_works) { in radeon_test_writeback()
850 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on) in radeon_set_igpgart() argument
856 dev_priv->gart_vm_start, in radeon_set_igpgart()
857 (long)dev_priv->gart_info.bus_addr, in radeon_set_igpgart()
858 dev_priv->gart_size); in radeon_set_igpgart()
860 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL); in radeon_set_igpgart()
861 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_set_igpgart()
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) in radeon_set_igpgart()
871 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID); in radeon_set_igpgart()
877 temp = dev_priv->gart_info.bus_addr & 0xfffff000; in radeon_set_igpgart()
878 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4; in radeon_set_igpgart()
881 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL); in radeon_set_igpgart()
885 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start); in radeon_set_igpgart()
887 dev_priv->gart_size = 32*1024*1024; in radeon_set_igpgart()
888 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) & in radeon_set_igpgart()
889 0xffff0000) | (dev_priv->gart_vm_start >> 16)); in radeon_set_igpgart()
891 radeon_write_agp_location(dev_priv, temp); in radeon_set_igpgart()
893 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE); in radeon_set_igpgart()
898 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()
908 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL); in radeon_set_igpgart()
921 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on) in rs600_set_igpgart() argument
928 dev_priv->gart_vm_start, in rs600_set_igpgart()
929 (long)dev_priv->gart_info.bus_addr, in rs600_set_igpgart()
930 dev_priv->gart_size); in rs600_set_igpgart()
953 dev_priv->gart_info.bus_addr); in rs600_set_igpgart()
955 dev_priv->gart_vm_start); in rs600_set_igpgart()
957 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
962 dev_priv->gart_vm_start); in rs600_set_igpgart()
964 (dev_priv->gart_vm_start + dev_priv->gart_size - 1)); in rs600_set_igpgart()
967 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
970 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); in rs600_set_igpgart()
974 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
978 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
982 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
986 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL); in rs600_set_igpgart()
990 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1); in rs600_set_igpgart()
996 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on) in radeon_set_pciegart() argument
998 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL); in radeon_set_pciegart()
1002 dev_priv->gart_vm_start, in radeon_set_pciegart()
1003 (long)dev_priv->gart_info.bus_addr, in radeon_set_pciegart()
1004 dev_priv->gart_size); in radeon_set_pciegart()
1006 dev_priv->gart_vm_start); in radeon_set_pciegart()
1008 dev_priv->gart_info.bus_addr); in radeon_set_pciegart()
1010 dev_priv->gart_vm_start); in radeon_set_pciegart()
1012 dev_priv->gart_vm_start + in radeon_set_pciegart()
1013 dev_priv->gart_size - 1); in radeon_set_pciegart()
1015 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ in radeon_set_pciegart()
1026 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on) in radeon_set_pcigart() argument
1030 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || in radeon_set_pcigart()
1031 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) || in radeon_set_pcigart()
1032 (dev_priv->flags & RADEON_IS_IGPGART)) { in radeon_set_pcigart()
1033 radeon_set_igpgart(dev_priv, on); in radeon_set_pcigart()
1037 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) { in radeon_set_pcigart()
1038 rs600_set_igpgart(dev_priv, on); in radeon_set_pcigart()
1042 if (dev_priv->flags & RADEON_IS_PCIE) { in radeon_set_pcigart()
1043 radeon_set_pciegart(dev_priv, on); in radeon_set_pcigart()
1055 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr); in radeon_set_pcigart()
1059 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start); in radeon_set_pcigart()
1060 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start in radeon_set_pcigart()
1061 + dev_priv->gart_size - 1); in radeon_set_pcigart()
1065 radeon_write_agp_location(dev_priv, 0xffffffc0); in radeon_set_pcigart()
1073 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv) in radeon_setup_pcigart_surface() argument
1075 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; in radeon_setup_pcigart_surface()
1080 if (!dev_priv->virt_surfaces[i].file_priv || in radeon_setup_pcigart_surface()
1081 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV) in radeon_setup_pcigart_surface()
1086 vp = &dev_priv->virt_surfaces[i]; in radeon_setup_pcigart_surface()
1089 struct radeon_surface *sp = &dev_priv->surfaces[i]; in radeon_setup_pcigart_surface()
1116 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_init_cp() local
1121 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { in radeon_do_init_cp()
1127 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { in radeon_do_init_cp()
1129 dev_priv->flags &= ~RADEON_IS_AGP; in radeon_do_init_cp()
1130 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) in radeon_do_init_cp()
1133 dev_priv->flags |= RADEON_IS_AGP; in radeon_do_init_cp()
1136 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) { in radeon_do_init_cp()
1142 dev_priv->usec_timeout = init->usec_timeout; in radeon_do_init_cp()
1143 if (dev_priv->usec_timeout < 1 || in radeon_do_init_cp()
1144 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { in radeon_do_init_cp()
1152 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; in radeon_do_init_cp()
1156 dev_priv->microcode_version = UCODE_R200; in radeon_do_init_cp()
1159 dev_priv->microcode_version = UCODE_R300; in radeon_do_init_cp()
1162 dev_priv->microcode_version = UCODE_R100; in radeon_do_init_cp()
1165 dev_priv->do_boxes = 0; in radeon_do_init_cp()
1166 dev_priv->cp_mode = init->cp_mode; in radeon_do_init_cp()
1181 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; in radeon_do_init_cp()
1185 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; in radeon_do_init_cp()
1188 dev_priv->front_offset = init->front_offset; in radeon_do_init_cp()
1189 dev_priv->front_pitch = init->front_pitch; in radeon_do_init_cp()
1190 dev_priv->back_offset = init->back_offset; in radeon_do_init_cp()
1191 dev_priv->back_pitch = init->back_pitch; in radeon_do_init_cp()
1195 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z; in radeon_do_init_cp()
1199 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z; in radeon_do_init_cp()
1202 dev_priv->depth_offset = init->depth_offset; in radeon_do_init_cp()
1203 dev_priv->depth_pitch = init->depth_pitch; in radeon_do_init_cp()
1210 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE | in radeon_do_init_cp()
1211 (dev_priv->color_fmt << 10) | in radeon_do_init_cp()
1212 (dev_priv->microcode_version == in radeon_do_init_cp()
1215 dev_priv->depth_clear.rb3d_zstencilcntl = in radeon_do_init_cp()
1216 (dev_priv->depth_fmt | in radeon_do_init_cp()
1223 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW | in radeon_do_init_cp()
1236 dev_priv->ring_offset = init->ring_offset; in radeon_do_init_cp()
1237 dev_priv->ring_rptr_offset = init->ring_rptr_offset; in radeon_do_init_cp()
1238 dev_priv->buffers_offset = init->buffers_offset; in radeon_do_init_cp()
1239 dev_priv->gart_textures_offset = init->gart_textures_offset; in radeon_do_init_cp()
1241 dev_priv->sarea = drm_getsarea(dev); in radeon_do_init_cp()
1242 if (!dev_priv->sarea) { in radeon_do_init_cp()
1248 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); in radeon_do_init_cp()
1249 if (!dev_priv->cp_ring) { in radeon_do_init_cp()
1254 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); in radeon_do_init_cp()
1255 if (!dev_priv->ring_rptr) { in radeon_do_init_cp()
1269 dev_priv->gart_textures = in radeon_do_init_cp()
1271 if (!dev_priv->gart_textures) { in radeon_do_init_cp()
1278 dev_priv->sarea_priv = in radeon_do_init_cp()
1279 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual + in radeon_do_init_cp()
1283 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1284 drm_core_ioremap_wc(dev_priv->cp_ring, dev); in radeon_do_init_cp()
1285 drm_core_ioremap_wc(dev_priv->ring_rptr, dev); in radeon_do_init_cp()
1287 if (!dev_priv->cp_ring->virtual || in radeon_do_init_cp()
1288 !dev_priv->ring_rptr->virtual || in radeon_do_init_cp()
1297 dev_priv->cp_ring->virtual = in radeon_do_init_cp()
1298 (void *)(unsigned long)dev_priv->cp_ring->offset; in radeon_do_init_cp()
1299 dev_priv->ring_rptr->virtual = in radeon_do_init_cp()
1300 (void *)(unsigned long)dev_priv->ring_rptr->offset; in radeon_do_init_cp()
1305 dev_priv->cp_ring->virtual); in radeon_do_init_cp()
1307 dev_priv->ring_rptr->virtual); in radeon_do_init_cp()
1312 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16; in radeon_do_init_cp()
1313 dev_priv->fb_size = in radeon_do_init_cp()
1314 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000) in radeon_do_init_cp()
1315 - dev_priv->fb_location; in radeon_do_init_cp()
1317 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | in radeon_do_init_cp()
1318 ((dev_priv->front_offset in radeon_do_init_cp()
1319 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1321 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | in radeon_do_init_cp()
1322 ((dev_priv->back_offset in radeon_do_init_cp()
1323 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1325 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | in radeon_do_init_cp()
1326 ((dev_priv->depth_offset in radeon_do_init_cp()
1327 + dev_priv->fb_location) >> 10)); in radeon_do_init_cp()
1329 dev_priv->gart_size = init->gart_size; in radeon_do_init_cp()
1332 if (dev_priv->new_memmap) { in radeon_do_init_cp()
1342 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1345 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && in radeon_do_init_cp()
1346 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { in radeon_do_init_cp()
1355 base = dev_priv->fb_location + dev_priv->fb_size; in radeon_do_init_cp()
1356 if (base < dev_priv->fb_location || in radeon_do_init_cp()
1357 ((base + dev_priv->gart_size) & 0xfffffffful) < base) in radeon_do_init_cp()
1358 base = dev_priv->fb_location in radeon_do_init_cp()
1359 - dev_priv->gart_size; in radeon_do_init_cp()
1361 dev_priv->gart_vm_start = base & 0xffc00000u; in radeon_do_init_cp()
1362 if (dev_priv->gart_vm_start != base) in radeon_do_init_cp()
1364 base, dev_priv->gart_vm_start); in radeon_do_init_cp()
1367 dev_priv->gart_vm_start = dev_priv->fb_location + in radeon_do_init_cp()
1372 if (dev_priv->flags & RADEON_IS_AGP) in radeon_do_init_cp()
1373 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset in radeon_do_init_cp()
1375 + dev_priv->gart_vm_start); in radeon_do_init_cp()
1378 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset - in radeon_do_init_cp()
1379 dev->sg->vaddr + dev_priv->gart_vm_start; in radeon_do_init_cp()
1381 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); in radeon_do_init_cp()
1382 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start); in radeon_do_init_cp()
1384 dev_priv->gart_buffers_offset); in radeon_do_init_cp()
1386 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual; in radeon_do_init_cp()
1387 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual in radeon_do_init_cp()
1389 dev_priv->ring.size = init->ring_size; in radeon_do_init_cp()
1390 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); in radeon_do_init_cp()
1392 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; in radeon_do_init_cp()
1393 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8); in radeon_do_init_cp()
1395 dev_priv->ring.fetch_size = /* init->fetch_size */ 32; in radeon_do_init_cp()
1396 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16); in radeon_do_init_cp()
1397 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in radeon_do_init_cp()
1399 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; in radeon_do_init_cp()
1402 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_init_cp()
1404 radeon_set_pcigart(dev_priv, 0); in radeon_do_init_cp()
1411 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); in radeon_do_init_cp()
1413 if (dev_priv->pcigart_offset_set) { in radeon_do_init_cp()
1414 dev_priv->gart_info.bus_addr = in radeon_do_init_cp()
1415 dev_priv->pcigart_offset + dev_priv->fb_location; in radeon_do_init_cp()
1416 dev_priv->gart_info.mapping.offset = in radeon_do_init_cp()
1417 dev_priv->pcigart_offset + dev_priv->fb_aper_offset; in radeon_do_init_cp()
1418 dev_priv->gart_info.mapping.size = in radeon_do_init_cp()
1419 dev_priv->gart_info.table_size; in radeon_do_init_cp()
1421 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); in radeon_do_init_cp()
1422 dev_priv->gart_info.addr = in radeon_do_init_cp()
1423 dev_priv->gart_info.mapping.virtual; in radeon_do_init_cp()
1425 if (dev_priv->flags & RADEON_IS_PCIE) in radeon_do_init_cp()
1426 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE; in radeon_do_init_cp()
1428 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; in radeon_do_init_cp()
1429 dev_priv->gart_info.gart_table_location = in radeon_do_init_cp()
1433 dev_priv->gart_info.addr, in radeon_do_init_cp()
1434 dev_priv->pcigart_offset); in radeon_do_init_cp()
1436 if (dev_priv->flags & RADEON_IS_IGPGART) in radeon_do_init_cp()
1437 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP; in radeon_do_init_cp()
1439 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI; in radeon_do_init_cp()
1440 dev_priv->gart_info.gart_table_location = in radeon_do_init_cp()
1442 dev_priv->gart_info.addr = NULL; in radeon_do_init_cp()
1443 dev_priv->gart_info.bus_addr = 0; in radeon_do_init_cp()
1444 if (dev_priv->flags & RADEON_IS_PCIE) { in radeon_do_init_cp()
1454 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_init_cp()
1457 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1466 ret = radeon_setup_pcigart_surface(dev_priv); in radeon_do_init_cp()
1469 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_init_cp()
1470 r600_page_table_cleanup(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1472 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info); in radeon_do_init_cp()
1478 radeon_set_pcigart(dev_priv, 1); in radeon_do_init_cp()
1481 radeon_cp_load_microcode(dev_priv); in radeon_do_init_cp()
1482 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); in radeon_do_init_cp()
1484 dev_priv->last_buf = 0; in radeon_do_init_cp()
1487 radeon_test_writeback(dev_priv); in radeon_do_init_cp()
1494 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_cleanup_cp() local
1505 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_cleanup_cp()
1506 if (dev_priv->cp_ring != NULL) { in radeon_do_cleanup_cp()
1507 drm_core_ioremapfree(dev_priv->cp_ring, dev); in radeon_do_cleanup_cp()
1508 dev_priv->cp_ring = NULL; in radeon_do_cleanup_cp()
1510 if (dev_priv->ring_rptr != NULL) { in radeon_do_cleanup_cp()
1511 drm_core_ioremapfree(dev_priv->ring_rptr, dev); in radeon_do_cleanup_cp()
1512 dev_priv->ring_rptr = NULL; in radeon_do_cleanup_cp()
1522 if (dev_priv->gart_info.bus_addr) { in radeon_do_cleanup_cp()
1524 radeon_set_pcigart(dev_priv, 0); in radeon_do_cleanup_cp()
1525 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) in radeon_do_cleanup_cp()
1526 r600_page_table_cleanup(dev, &dev_priv->gart_info); in radeon_do_cleanup_cp()
1528 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info)) in radeon_do_cleanup_cp()
1533 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) in radeon_do_cleanup_cp()
1535 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); in radeon_do_cleanup_cp()
1536 dev_priv->gart_info.addr = 0; in radeon_do_cleanup_cp()
1540 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); in radeon_do_cleanup_cp()
1554 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_resume_cp() local
1556 if (!dev_priv) { in radeon_do_resume_cp()
1564 if (dev_priv->flags & RADEON_IS_AGP) { in radeon_do_resume_cp()
1566 radeon_set_pcigart(dev_priv, 0); in radeon_do_resume_cp()
1571 radeon_set_pcigart(dev_priv, 1); in radeon_do_resume_cp()
1574 radeon_cp_load_microcode(dev_priv); in radeon_do_resume_cp()
1575 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv); in radeon_do_resume_cp()
1587 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_init() local
1603 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_init()
1614 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_start() local
1619 if (dev_priv->cp_running) { in radeon_cp_start()
1623 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) { in radeon_cp_start()
1625 dev_priv->cp_mode); in radeon_cp_start()
1629 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_start()
1630 r600_do_cp_start(dev_priv); in radeon_cp_start()
1632 radeon_do_cp_start(dev_priv); in radeon_cp_start()
1642 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_stop() local
1649 if (!dev_priv->cp_running) in radeon_cp_stop()
1656 radeon_do_cp_flush(dev_priv); in radeon_cp_stop()
1663 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1664 ret = r600_do_cp_idle(dev_priv); in radeon_cp_stop()
1666 ret = radeon_do_cp_idle(dev_priv); in radeon_cp_stop()
1675 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1676 r600_do_cp_stop(dev_priv); in radeon_cp_stop()
1678 radeon_do_cp_stop(dev_priv); in radeon_cp_stop()
1681 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_stop()
1691 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_do_release() local
1694 if (dev_priv) { in radeon_do_release()
1695 if (dev_priv->cp_running) { in radeon_do_release()
1697 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_do_release()
1698 while ((ret = r600_do_cp_idle(dev_priv)) != 0) { in radeon_do_release()
1704 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) { in radeon_do_release()
1710 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_do_release()
1711 r600_do_cp_stop(dev_priv); in radeon_do_release()
1714 radeon_do_cp_stop(dev_priv); in radeon_do_release()
1719 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) { in radeon_do_release()
1721 if (dev_priv->mmio) /* remove this after permanent addmaps */ in radeon_do_release()
1724 if (dev_priv->mmio) { /* remove all surfaces */ in radeon_do_release()
1736 radeon_mem_takedown(&(dev_priv->gart_heap)); in radeon_do_release()
1737 radeon_mem_takedown(&(dev_priv->fb_heap)); in radeon_do_release()
1740 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_do_release()
1751 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_reset() local
1756 if (!dev_priv) { in radeon_cp_reset()
1761 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_reset()
1762 r600_do_cp_reset(dev_priv); in radeon_cp_reset()
1764 radeon_do_cp_reset(dev_priv); in radeon_cp_reset()
1767 dev_priv->cp_running = 0; in radeon_cp_reset()
1774 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_idle() local
1779 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_idle()
1780 return r600_do_cp_idle(dev_priv); in radeon_cp_idle()
1782 return radeon_do_cp_idle(dev_priv); in radeon_cp_idle()
1789 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_cp_resume() local
1792 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_cp_resume()
1800 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_engine_reset() local
1805 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) in radeon_engine_reset()
1846 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_freelist_get() local
1852 if (++dev_priv->last_buf >= dma->buf_count) in radeon_freelist_get()
1853 dev_priv->last_buf = 0; in radeon_freelist_get()
1855 start = dev_priv->last_buf; in radeon_freelist_get()
1857 for (t = 0; t < dev_priv->usec_timeout; t++) { in radeon_freelist_get()
1858 u32 done_age = GET_SCRATCH(dev_priv, 1); in radeon_freelist_get()
1866 dev_priv->stats.requested_bufs++; in radeon_freelist_get()
1876 dev_priv->stats.freelist_loops++; in radeon_freelist_get()
1886 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_freelist_reset() local
1889 dev_priv->last_buf = 0; in radeon_freelist_reset()
1901 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n) in radeon_wait_ring() argument
1903 drm_radeon_ring_buffer_t *ring = &dev_priv->ring; in radeon_wait_ring()
1905 u32 last_head = GET_RING_HEAD(dev_priv); in radeon_wait_ring()
1907 for (i = 0; i < dev_priv->usec_timeout; i++) { in radeon_wait_ring()
1908 u32 head = GET_RING_HEAD(dev_priv); in radeon_wait_ring()
1916 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; in radeon_wait_ring()
1927 radeon_status(dev_priv); in radeon_wait_ring()
1994 drm_radeon_private_t *dev_priv; in radeon_driver_load() local
1997 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER); in radeon_driver_load()
1998 if (dev_priv == NULL) in radeon_driver_load()
2001 memset(dev_priv, 0, sizeof(drm_radeon_private_t)); in radeon_driver_load()
2002 dev->dev_private = (void *)dev_priv; in radeon_driver_load()
2003 dev_priv->flags = flags; in radeon_driver_load()
2018 dev_priv->flags |= RADEON_HAS_HIERZ; in radeon_driver_load()
2026 dev_priv->flags |= RADEON_IS_AGP; in radeon_driver_load()
2028 dev_priv->flags |= RADEON_IS_PCIE; in radeon_driver_load()
2030 dev_priv->flags |= RADEON_IS_PCI; in radeon_driver_load()
2032 mtx_init(&dev_priv->cs.cs_mutex, "cs_mtx", NULL, MTX_DEF); in radeon_driver_load()
2036 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio); in radeon_driver_load()
2047 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : in radeon_driver_load()
2048 (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); in radeon_driver_load()
2064 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_firstopen() local
2066 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE; in radeon_driver_firstopen()
2068 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0); in radeon_driver_firstopen()
2069 ret = drm_addmap(dev, dev_priv->fb_aper_offset, in radeon_driver_firstopen()
2080 drm_radeon_private_t *dev_priv = dev->dev_private; in radeon_driver_unload() local
2084 drm_rmmap(dev, dev_priv->mmio); in radeon_driver_unload()
2086 mtx_destroy(&dev_priv->cs.cs_mutex); in radeon_driver_unload()
2088 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER); in radeon_driver_unload()
2094 void radeon_commit_ring(drm_radeon_private_t *dev_priv) in radeon_commit_ring() argument
2102 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN - 1); in radeon_commit_ring()
2106 ring = dev_priv->ring.start; in radeon_commit_ring()
2109 ring[dev_priv->ring.tail + i] = CP_PACKET2(); in radeon_commit_ring()
2111 dev_priv->ring.tail += i; in radeon_commit_ring()
2113 dev_priv->ring.space -= num_p2 * sizeof(u32); in radeon_commit_ring()
2116 dev_priv->ring.tail &= dev_priv->ring.tail_mask; in radeon_commit_ring()
2119 GET_RING_HEAD( dev_priv ); in radeon_commit_ring()
2121 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) { in radeon_commit_ring()
2122 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail); in radeon_commit_ring()
2126 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail); in radeon_commit_ring()