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Searched refs:CSR_READ_4 (Results 1 – 25 of 61) sorted by relevance

123

/freebsd-13-stable/sys/mips/ingenic/
HDjz4780_clock.c497 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
576 *val = CSR_READ_4(sc, addr); in jz4780_clock_read_4()
588 val = CSR_READ_4(sc, addr); in jz4780_clock_modify_4()
684 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ohci_enable()
715 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
720 reg = CSR_READ_4(sc, JZ_OPCR); in jz4780_ehci_enable()
725 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
730 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
735 reg = CSR_READ_4(sc, JZ_USBPCR1); in jz4780_ehci_enable()
740 reg = CSR_READ_4(sc, JZ_USBPCR); in jz4780_ehci_enable()
[all …]
HDjz4780_efuse.c73 #define CSR_READ_4(sc, reg) \ macro
102 while ((CSR_READ_4(sc, JZ_EFUSTATE) & JZ_EFUSE_RD_DONE) == 0) in jz4780_efuse_read_chunk()
109 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
116 abuf = CSR_READ_4(sc, JZ_EFUDATA0 + i); in jz4780_efuse_read_chunk()
HDjz4780_gpio.c108 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) macro
238 val = CSR_READ_4(sc, JZ_GPIO_INT); in jz4780_gpio_pin_probe()
241 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
247 val = CSR_READ_4(sc, JZ_GPIO_PAT0); in jz4780_gpio_pin_probe()
258 val = CSR_READ_4(sc, JZ_GPIO_MASK); in jz4780_gpio_pin_probe()
261 val = CSR_READ_4(sc, JZ_GPIO_PAT1); in jz4780_gpio_pin_probe()
267 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
275 val = CSR_READ_4(sc, JZ_GPIO_DPULL); in jz4780_gpio_pin_probe()
279 val = ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin) << 1; in jz4780_gpio_pin_probe()
280 val = val | ((CSR_READ_4(sc, JZ_GPIO_PAT1) & mask) >> pin); in jz4780_gpio_pin_probe()
[all …]
/freebsd-13-stable/sys/dev/bge/
HDif_bge.c625 CSR_READ_4(sc, off); in bge_writembx()
967 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) in bge_nvram_getbyte()
975 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); in bge_nvram_getbyte()
982 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { in bge_nvram_getbyte()
994 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); in bge_nvram_getbyte()
1003 CSR_READ_4(sc, BGE_NVRAM_SWARB); in bge_nvram_getbyte()
1059 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) in bge_eeprom_getbyte()
1069 byte = CSR_READ_4(sc, BGE_EE_DATA); in bge_eeprom_getbyte()
1120 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
1123 val = CSR_READ_4(sc, BGE_MI_COMM); in bge_miibus_readreg()
[all …]
/freebsd-13-stable/sys/dev/et/
HDif_et.c435 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_readreg()
449 val = CSR_READ_4(sc, ET_MII_STAT); in et_miibus_readreg()
480 val = CSR_READ_4(sc, ET_MII_IND); in et_miibus_writereg()
535 ctrl = CSR_READ_4(sc, ET_MAC_CTRL); in et_miibus_statchg()
537 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
540 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2); in et_miibus_statchg()
584 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1); in et_miibus_statchg()
657 CSR_WRITE_4(sc, ET_MAC_CFG1, CSR_READ_4(sc, ET_MAC_CFG1) & ~( in et_stop()
1186 status = CSR_READ_4(sc, ET_INTR_STATUS); in et_intr()
1481 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) { in et_stop_rxdma()
[all …]
/freebsd-13-stable/sys/dev/dc/
HDdcphy.c75 CSR_READ_4(sc, reg) | x)
79 CSR_READ_4(sc, reg) & ~x)
208 mode = CSR_READ_4(dc_sc, DC_NETCFG); in dcphy_service()
263 reg = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_service()
309 tstat = CSR_READ_4(dc_sc, DC_10BTSTAT); in dcphy_status()
313 if (CSR_READ_4(dc_sc, DC_10BTCTRL) & DC_TCTL_AUTONEGENBL) { in dcphy_status()
366 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_SPEEDSEL) in dcphy_status()
370 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) in dcphy_status()
HDif_dc.c360 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
363 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
374 CSR_READ_4(sc, DC_BUSCTL); in dc_delay()
410 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { in dc_eeprom_width()
522 r = CSR_READ_4(sc, DC_SIO); in dc_eeprom_getword_pnic()
543 *dest = (uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff; in dc_eeprom_getword_xircom()
546 *dest |= ((uint16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8; in dc_eeprom_getword_xircom()
584 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) in dc_eeprom_getword()
647 val = CSR_READ_4(sc, DC_SIO); in dc_mii_bitbang_read()
691 rval = CSR_READ_4(sc, DC_PN_MII); in dc_miibus_readreg()
[all …]
HDpnphy.c209 reg = CSR_READ_4(dc_sc, DC_ISR); in pnphy_status()
212 reg = CSR_READ_4(dc_sc, DC_NETCFG); in pnphy_status()
/freebsd-13-stable/sys/dev/alc/
HDif_alc.c310 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
337 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
375 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
401 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
452 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
496 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
527 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
710 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
711 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
712 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
[all …]
/freebsd-13-stable/sys/dev/nge/
HDif_nge.c248 CSR_READ_4(sc, reg) | (x))
252 CSR_READ_4(sc, reg) & ~(x))
255 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
258 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
266 CSR_READ_4(sc, NGE_CSR); in nge_delay()
350 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) in nge_eeprom_getword()
390 val = CSR_READ_4(sc, NGE_MEAR); in nge_mii_bitbang_read()
430 reg = CSR_READ_4(sc, NGE_TBI_BMSR); in nge_miibus_readreg()
456 return (CSR_READ_4(sc, reg)); in nge_miibus_readreg()
590 reg = CSR_READ_4(sc, NGE_CFG); in nge_miibus_statchg()
[all …]
/freebsd-13-stable/sys/dev/bfe/
HDif_bfe.c667 val = CSR_READ_4(sc, BFE_TX_CTRL); in bfe_miibus_statchg()
673 flow = CSR_READ_4(sc, BFE_RXCONF); in bfe_miibus_statchg()
683 flow = CSR_READ_4(sc, BFE_MAC_FLOW); in bfe_miibus_statchg()
862 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK; in bfe_pci_setup()
864 val = CSR_READ_4(sc, BFE_SBINTVEC); in bfe_pci_setup()
868 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2); in bfe_pci_setup()
884 CSR_READ_4(sc, reg); in bfe_clear_stats()
886 CSR_READ_4(sc, reg); in bfe_clear_stats()
910 CSR_READ_4(sc, BFE_IMASK); in bfe_chip_halt()
931 val = CSR_READ_4(sc, BFE_SBTMSLOW) & in bfe_chip_reset()
[all …]
/freebsd-13-stable/sys/dev/jme/
HDif_jme.c231 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_readreg()
263 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) in jme_miibus_writereg()
359 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_eeprom_read_byte()
374 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
384 reg = CSR_READ_4(sc, JME_SMBINTF); in jme_eeprom_read_byte()
492 par0 = CSR_READ_4(sc, JME_PAR0); in jme_reg_macaddr()
493 par1 = CSR_READ_4(sc, JME_PAR1); in jme_reg_macaddr()
711 reg = CSR_READ_4(sc, JME_CHIPMODE); in jme_attach()
754 reg = CSR_READ_4(sc, JME_SMBCSR); in jme_attach()
770 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
[all …]
/freebsd-13-stable/sys/dev/sis/
HDif_sis.c120 #define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg) macro
196 CSR_READ_4(sc, reg) | (x))
200 CSR_READ_4(sc, reg) & ~(x))
203 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
206 CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
229 CSR_READ_4(sc, SIS_CSR); in sis_delay()
313 if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT) in sis_eeprom_getword()
415 filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL); in sis_read_mac()
416 csrsave = CSR_READ_4(sc, SIS_CSR); in sis_read_mac()
446 val = CSR_READ_4(sc, SIS_EECTL); in sis_mii_bitbang_read()
[all …]
/freebsd-13-stable/sys/dev/bwi/
HDbwimac.c198 return CSR_READ_4(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
247 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */ in bwi_mac_lateattach()
462 state_lo = CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
468 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
474 CSR_READ_4(sc, BWI_STATE_LO); in bwi_mac_reset()
479 status = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_reset()
569 val = CSR_READ_4(sc, BWI_MAC_STATUS); in bwi_mac_test()
576 val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_test()
718 CSR_READ_4(sc, BWI_MAC_STATUS); /* dummy read */ in bwi_mac_dummy_xmit()
1054 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); in bwi_mac_fw_load()
[all …]
HDif_bwi.c754 val = CSR_READ_4(sc, BWI_ID_HI); in bwi_regwin_info()
788 info = CSR_READ_4(sc, BWI_INFO); in bwi_bbp_attach()
793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); in bwi_bbp_attach()
920 val = CSR_READ_4(sc, BWI_FLAGS); in bwi_bus_init()
977 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ in bwi_bus_init()
979 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ in bwi_bus_init()
1066 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); in bwi_get_clock_freq()
1079 val = CSR_READ_4(sc, BWI_CLOCK_INFO); in bwi_get_clock_freq()
1127 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); in bwi_set_clock_mode()
1250 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & in bwi_init_statechg()
[all …]
HDif_bwivar.h76 #define CSR_READ_4(sc, reg) \ macro
87 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
92 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
97 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
/freebsd-13-stable/sys/dev/stge/
HDif_stge.c518 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia) in stge_attach()
995 CSR_READ_4(sc, STGE_AsicCtrl) | AC_TxReset); in stge_setwol()
1053 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0) in stge_dma_wait()
1386 v = ac = CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK; in stge_link_task()
1392 ac = CSR_READ_4(sc, STGE_AsicCtrl); in stge_link_task()
1397 if ((CSR_READ_4(sc, STGE_AsicCtrl) & AC_ResetBusy) == 0) in stge_link_task()
1413 txstat = CSR_READ_4(sc, STGE_TxStatus); in stge_tx_error()
1435 (CSR_READ_4(sc, STGE_MACCtrl) & MC_MASK) | in stge_tx_error()
1870 CSR_READ_4(sc,STGE_OctetRcvOk); in stge_stats_update()
1872 if_inc_counter(ifp, IFCOUNTER_IPACKETS, CSR_READ_4(sc, STGE_FramesRcvdOk)); in stge_stats_update()
[all …]
/freebsd-13-stable/sys/dev/altera/atse/
HDif_atse.c180 #define CSR_READ_4(sc, reg) \ macro
405 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
411 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_stop_locked()
456 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_rxfilter_locked()
746 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
752 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
788 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
826 val4 = CSR_READ_4(sc, TX_CMD_STAT); in atse_reset()
830 val4 = CSR_READ_4(sc, RX_CMD_STAT); in atse_reset()
836 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); in atse_reset()
[all …]
/freebsd-13-stable/sys/dev/ale/
HDif_ale.c216 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_readreg()
243 v = CSR_READ_4(sc, ALE_MDIO); in ale_miibus_writereg()
293 reg = CSR_READ_4(sc, ALE_MAC_CFG); in ale_miibus_statchg()
366 reg = CSR_READ_4(sc, ALE_SPI_CTRL); in ale_get_macaddr()
377 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | in ale_get_macaddr()
381 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); in ale_get_macaddr()
394 ea[0] = CSR_READ_4(sc, ALE_PAR0); in ale_get_macaddr()
395 ea[1] = CSR_READ_4(sc, ALE_PAR1); in ale_get_macaddr()
495 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { in ale_attach()
521 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> in ale_attach()
[all …]
/freebsd-13-stable/sys/dev/lge/
HDif_lge.c198 CSR_READ_4(sc, reg) | (x))
202 CSR_READ_4(sc, reg) & ~(x))
205 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
208 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
223 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) in lge_eeprom_getword()
231 val = CSR_READ_4(sc, LGE_EEDATA); in lge_eeprom_getword()
281 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_readreg()
289 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); in lge_miibus_readreg()
304 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) in lge_miibus_writereg()
407 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) in lge_reset()
[all …]
/freebsd-13-stable/sys/dev/age/
HDif_age.c222 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_readreg()
252 v = CSR_READ_4(sc, AGE_MDIO); in age_miibus_writereg()
343 reg = CSR_READ_4(sc, AGE_SPI_CTRL); in age_get_macaddr()
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | in age_get_macaddr()
359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); in age_get_macaddr()
372 ea[0] = CSR_READ_4(sc, AGE_PAR0); in age_get_macaddr()
373 ea[1] = CSR_READ_4(sc, AGE_PAR1); in age_get_macaddr()
499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> in age_attach()
523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), in age_attach()
524 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); in age_attach()
[all …]
/freebsd-13-stable/sys/mips/atheros/ar531x/
HDif_are.c460 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_readreg()
464 return (CSR_READ_4(sc, CSR_MIIDATA) & 0xffff); in are_miibus_readreg()
483 if ((CSR_READ_4(sc, CSR_MIIADDR) & MIIADDR_BUSY) == 0) in are_miibus_writereg()
549 if ((CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) == 0) in are_reset()
553 if (CSR_READ_4(sc, CSR_BUSMODE) & BUSMODE_SWR) in are_reset()
832 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_encap()
891 txstat = (CSR_READ_4(sc, CSR_STATUS) >> 20) & 7; in are_start_locked()
918 CSR_READ_4(sc, CSR_MACCTL) & ~(MACCTL_TE | MACCTL_RE)); in are_stop()
931 macctl = CSR_READ_4(sc, CSR_MACCTL); in are_set_filter()
1631 status = CSR_READ_4(sc, CSR_STATUS); in are_intr()
[all …]
/freebsd-13-stable/sys/dev/vge/
HDif_vgevar.h224 #define CSR_READ_4(sc, reg) \ macro
236 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
243 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
/freebsd-13-stable/sys/dev/my/
HDif_my.c141 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
142 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
178 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_send_cmd_to_phy()
242 miir = CSR_READ_4(sc, MY_MANAGEMENT); in my_phy_readreg()
330 rxfilt = CSR_READ_4(sc, MY_TCRRCR); in my_setmulti()
717 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { in my_setcfg()
722 if (!(CSR_READ_4(sc, MY_TCRRCR) & in my_setcfg()
754 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) in my_reset()
1198 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { in my_txeof()
1219 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { in my_txeof()
[all …]
/freebsd-13-stable/sys/dev/ipw/
HDif_ipw.c1253 r = CSR_READ_4(sc, IPW_CSR_RX_READ); in ipw_rx_intr()
1346 r = CSR_READ_4(sc, IPW_CSR_TX_READ); in ipw_tx_intr()
1383 r = CSR_READ_4(sc, IPW_CSR_INTR); in ipw_intr()
1806 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED) in ipw_stop_master()
1813 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_stop_master()
1829 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1834 if (CSR_READ_4(sc, IPW_CSR_CTL) & IPW_CTL_CLOCK_READY) in ipw_reset()
1841 tmp = CSR_READ_4(sc, IPW_CSR_RST); in ipw_reset()
1846 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_reset()
1988 tmp = CSR_READ_4(sc, IPW_CSR_CTL); in ipw_load_firmware()
[all …]

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