Lines Matching refs:CSR_READ_4
310 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_813x()
337 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_readreg_816x()
375 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_813x()
401 v = CSR_READ_4(sc, ALC_MDIO); in alc_mii_writereg_816x()
452 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_miibus_statchg()
496 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_readreg()
527 v = CSR_READ_4(sc, ALC_MDIO); in alc_miiext_writereg()
710 opt = CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
711 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && in alc_get_macaddr_813x()
712 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { in alc_get_macaddr_813x()
724 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
749 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); in alc_get_macaddr_813x()
751 CSR_READ_4(sc, ALC_WOL_CFG); in alc_get_macaddr_813x()
753 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | in alc_get_macaddr_813x()
757 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & in alc_get_macaddr_813x()
775 CSR_READ_4(sc, ALC_OPT_CFG); in alc_get_macaddr_813x()
812 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
821 reg = CSR_READ_4(sc, ALC_SLD); in alc_get_macaddr_816x()
834 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
838 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
849 reg = CSR_READ_4(sc, ALC_EEPROM_LD); in alc_get_macaddr_816x()
867 ea[0] = CSR_READ_4(sc, ALC_PAR0); in alc_get_macaddr_par()
868 ea[1] = CSR_READ_4(sc, ALC_PAR1); in alc_get_macaddr_par()
884 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_disable_l0s_l1()
1023 val = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_phy_reset_816x()
1055 val = CSR_READ_4(sc, ALC_LPI_CTL); in alc_phy_reset_816x()
1104 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_phy_down()
1159 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_aspm_813x()
1243 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_aspm_816x()
1281 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); in alc_init_pcie()
1287 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); in alc_init_pcie()
1289 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | in alc_init_pcie()
1293 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); in alc_init_pcie()
1325 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); in alc_init_pcie()
1328 val = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_init_pcie()
1360 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); in alc_config_msi()
1453 if (CSR_READ_4(sc, ALC_MT_MAGIC) == MT_MAGIC) in alc_attach()
1480 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> in alc_attach()
1492 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, in alc_attach()
1493 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); in alc_attach()
2550 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); in alc_setwol_813x()
2556 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2564 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2571 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_813x()
2580 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); in alc_setwol_813x()
2587 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); in alc_setwol_813x()
2609 master = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_setwol_816x()
2611 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); in alc_setwol_816x()
2618 mac = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_816x()
2629 mac = CSR_READ_4(sc, ALC_MAC_CFG); in alc_setwol_816x()
2641 reg = CSR_READ_4(sc, ALC_MISC); in alc_setwol_816x()
2649 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); in alc_setwol_816x()
3171 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_mac_config()
3219 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); in alc_stats_clear()
3225 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); in alc_stats_clear()
3256 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); in alc_stats_update()
3262 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); in alc_stats_update()
3360 status = CSR_READ_4(sc, ALC_INTR_STATUS); in alc_intr()
3381 status = CSR_READ_4(sc, ALC_INTR_STATUS); in alc_int_task()
3428 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { in alc_int_task()
3468 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); in alc_txeof()
3808 reg = CSR_READ_4(sc, ALC_MISC3); in alc_osc_reset()
3813 reg = CSR_READ_4(sc, ALC_MISC); in alc_osc_reset()
3824 reg = CSR_READ_4(sc, ALC_MISC2); in alc_osc_reset()
3854 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); in alc_reset()
3863 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_reset()
3870 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) in alc_reset()
3878 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) in alc_reset()
3885 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_reset()
3897 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_reset()
3907 reg = CSR_READ_4(sc, ALC_MISC3); in alc_reset()
3911 reg = CSR_READ_4(sc, ALC_MISC); in alc_reset()
3922 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | in alc_reset()
3994 CSR_READ_4(sc, ALC_WOL_CFG); in alc_init_locked()
4078 reg = CSR_READ_4(sc, ALC_MASTER_CFG); in alc_init_locked()
4203 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); in alc_init_locked()
4219 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); in alc_init_locked()
4353 reg = CSR_READ_4(sc, ALC_DMA_CFG); in alc_stop()
4403 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_stop_mac()
4409 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_stop_mac()
4434 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); in alc_start_queue()
4442 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); in alc_start_queue()
4454 reg = CSR_READ_4(sc, ALC_RXQ_CFG); in alc_stop_queue()
4467 reg = CSR_READ_4(sc, ALC_TXQ_CFG); in alc_stop_queue()
4474 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); in alc_stop_queue()
4594 reg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_rxvlan()
4626 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); in alc_rxfilter()