667 	val = CSR_READ_4(sc, BFE_TX_CTRL);  in bfe_miibus_statchg()
673 		flow = CSR_READ_4(sc, BFE_RXCONF);  in bfe_miibus_statchg()
683 		flow = CSR_READ_4(sc, BFE_MAC_FLOW);  in bfe_miibus_statchg()
862 	pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;  in bfe_pci_setup()
864 	val = CSR_READ_4(sc, BFE_SBINTVEC);  in bfe_pci_setup()
868 	val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);  in bfe_pci_setup()
884 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
886 		CSR_READ_4(sc, reg);  in bfe_clear_stats()
910 	CSR_READ_4(sc, BFE_IMASK);  in bfe_chip_halt()
931 	val = CSR_READ_4(sc, BFE_SBTMSLOW) &  in bfe_chip_reset()
939 		if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)  in bfe_chip_reset()
958 	val = CSR_READ_4(sc, BFE_DEVCTRL);  in bfe_chip_reset()
961 	else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {  in bfe_chip_reset()
1006 	if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)  in bfe_core_disable()
1018 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_disable()
1035 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1039 	if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)  in bfe_core_reset()
1041 	val = CSR_READ_4(sc, BFE_SBIMSTATE);  in bfe_core_reset()
1047 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1052 	CSR_READ_4(sc, BFE_SBTMSLOW);  in bfe_core_reset()
1093 	val = CSR_READ_4(sc, BFE_RXCONF);  in bfe_set_rx_mode()
1158 		ptr[i/2] = CSR_READ_4(sc, 4096 + i);  in bfe_read_eeprom()
1168 		u_int32_t val = CSR_READ_4(sc, reg);  in bfe_wait_bit()
1198 	*val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;  in bfe_readphy()
1254 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1256 		*val++ = CSR_READ_4(sc, reg);  in bfe_stats_update()
1340 	chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;  in bfe_txeof()
1385 	status = CSR_READ_4(sc, BFE_DMARX_STAT);  in bfe_rxeof()
1449 	istat = CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()
1458 	CSR_READ_4(sc, BFE_ISTAT);  in bfe_intr()