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Searched refs:SELECT_CC (Results 1 – 25 of 42) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreInstrInfo.td364 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
367 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
369 "# SELECT_CC PSEUDO!",
1207 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1210 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1213 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1215 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1217 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1219 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1221 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
[all …]
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFISelLowering.cpp109 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in BPFTargetLowering()
178 case ISD::SELECT_CC: in LowerOperation()
507 return DAG.getNode(BPFISD::SELECT_CC, DL, VTs, Ops); in LowerSELECT_CC()
518 case BPFISD::SELECT_CC: in getTargetNodeName()
HDBPFISelLowering.h29 SELECT_CC, enumerator
HDBPFInstrInfo.td43 def BPFselectcc : SDNode<"BPFISD::SELECT_CC", SDT_BPFSelectCC, [SDNPInGlue]>;
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp80 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in R600TargetLowering()
81 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in R600TargetLowering()
171 setTargetDAGCombine(ISD::SELECT_CC); in R600TargetLowering()
591 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
1157 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1214 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1238 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1240 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1849 if (SelectCC.getOpcode() != ISD::SELECT_CC || in PerformDAGCombine()
1858 return DAG.getNode(ISD::SELECT_CC, dl, N->getValueType(0), in PerformDAGCombine()
[all …]
HDSIISelLowering.cpp97 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in SITargetLowering()
98 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in SITargetLowering()
99 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in SITargetLowering()
100 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in SITargetLowering()
173 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in SITargetLowering()
218 setTargetDAGCombine(ISD::SELECT_CC); in SITargetLowering()
HDAMDGPUISelLowering.cpp315 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in AMDGPUTargetLowering()
362 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
401 setOperationAction(ISD::SELECT_CC, VT, Expand); in AMDGPUTargetLowering()
412 setTargetDAGCombine(ISD::SELECT_CC); in AMDGPUTargetLowering()
HDEvergreenInstructions.td585 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelLowering.cpp116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); in MSP430TargetLowering()
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); in MSP430TargetLowering()
198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
983 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSETCC()
1002 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); in LowerSELECT_CC()
1154 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC"; in getTargetNodeName()
HDMSP430ISelLowering.h62 SELECT_CC, enumerator
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h357 SELECT_CC, enumerator
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeFloatTypes.cpp102 case ISD::SELECT_CC: R = SoftenFloatRes_SELECT_CC(N); break; in SoftenFloatResult()
616 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in SoftenFloatRes_SELECT_CC()
696 case ISD::SELECT_CC: Res = SoftenFloatOp_SELECT_CC(N); break; in SoftenFloatOperand()
883 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
1387 case ISD::SELECT_CC: Res = ExpandFloatOp_SELECT_CC(N); break; in ExpandFloatOperand()
1625 case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break; in PromoteFloatOperand()
1685 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatOp_SELECT_CC()
1779 case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; in PromoteFloatResult()
1991 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0), in PromoteFloatRes_SELECT_CC()
HDLegalizeTypesGeneric.cpp546 Lo = DAG.getNode(ISD::SELECT_CC, dl, LL.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
548 Hi = DAG.getNode(ISD::SELECT_CC, dl, LH.getValueType(), N->getOperand(0), in SplitRes_SELECT_CC()
HDSelectionDAGDumper.cpp206 case ISD::SELECT_CC: return "select_cc"; in getOperationName()
HDLegalizeDAG.cpp1228 case ISD::SELECT_CC: in LegalizeOp()
1231 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : in LegalizeOp()
1239 if (Node->getOpcode() == ISD::SELECT_CC) in LegalizeOp()
3943 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, in ExpandNode()
3950 case ISD::SELECT_CC: { in ExpandNode()
4011 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), in ExpandNode()
4016 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, in ExpandNode()
HDLegalizeIntegerTypes.cpp72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; in PromoteIntegerResult()
567 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in PromoteIntRes_SELECT_CC()
868 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break; in PromoteIntegerOperand()
1250 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandIntegerResult()
2606 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break; in ExpandIntegerOperand()
HDLegalizeVectorTypes.cpp65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break; in ScalarizeVectorResult()
338 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(), in ScalarizeVecRes_SELECT_CC()
588 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
1932 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break; in WidenVectorResult()
2722 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), in WidenVecRes_SELECT_CC()
HDDAGCombiner.cpp690 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
1362 case ISD::SELECT_CC: return visitSELECT_CC(N); in visit()
4019 case ISD::SELECT_CC: in visitXOR()
5001 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) || in visitSELECT()
5002 TLI.isOperationLegal(ISD::SELECT_CC, VT)) in visitSELECT()
5003 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, in visitSELECT()
5563 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(), in visitSELECT_CC()
8514 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) { in visitSINT_TO_FP()
8525 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops); in visitSINT_TO_FP()
8539 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops); in visitSINT_TO_FP()
[all …]
HDLegalizeVectorOps.cpp289 case ISD::SELECT_CC: in LegalizeOp()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
434 setOperationAction(ISD::SELECT_CC, VT, Promote); in PPCTargetLowering()
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
847 setTargetDAGCombine(ISD::SELECT_CC); in PPCTargetLowering()
7916 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
9392 N->getOpcode() == ISD::SELECT_CC) { in DAGCombineTruncBoolExt()
9435 N->getOperand(0).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
9442 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) && in DAGCombineTruncBoolExt()
9447 N->getOperand(1).getOpcode() != ISD::SELECT_CC && in DAGCombineTruncBoolExt()
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/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelLowering.cpp141 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in NVPTXTargetLowering()
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in NVPTXTargetLowering()
143 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand); in NVPTXTargetLowering()
144 setOperationAction(ISD::SELECT_CC, MVT::i8, Expand); in NVPTXTargetLowering()
145 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); in NVPTXTargetLowering()
146 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in NVPTXTargetLowering()
147 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in NVPTXTargetLowering()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1458 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in SparcTargetLowering()
1459 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in SparcTargetLowering()
1460 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in SparcTargetLowering()
1461 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in SparcTargetLowering()
1473 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in SparcTargetLowering()
2814 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, in LowerOperation()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp141 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in AArch64TargetLowering()
142 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in AArch64TargetLowering()
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in AArch64TargetLowering()
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in AArch64TargetLowering()
182 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in AArch64TargetLowering()
288 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); in AArch64TargetLowering()
357 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand); in AArch64TargetLowering()
390 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand); in AArch64TargetLowering()
495 setTargetDAGCombine(ISD::SELECT_CC); in AArch64TargetLowering()
545 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand); in AArch64TargetLowering()
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp279 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in MipsTargetLowering()
280 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in MipsTargetLowering()
327 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsTargetLowering()
328 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsTargetLowering()
869 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); in LowerOperation()
HDMipsSEISelLowering.cpp177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in MipsSETargetLowering()
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); in MipsSETargetLowering()
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); in MipsSETargetLowering()
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); in MipsSETargetLowering()

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