1 //===-- MSP430ISelLowering.cpp - MSP430 DAG Lowering Implementation ------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the MSP430TargetLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MSP430ISelLowering.h"
15 #include "MSP430.h"
16 #include "MSP430MachineFunctionInfo.h"
17 #include "MSP430Subtarget.h"
18 #include "MSP430TargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/ValueTypes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/GlobalAlias.h"
31 #include "llvm/IR/GlobalVariable.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 using namespace llvm;
38
39 #define DEBUG_TYPE "msp430-lower"
40
41 typedef enum {
42 NoHWMult,
43 HWMultIntr,
44 HWMultNoIntr
45 } HWMultUseMode;
46
47 static cl::opt<HWMultUseMode>
48 HWMultMode("msp430-hwmult-mode", cl::Hidden,
49 cl::desc("Hardware multiplier use mode"),
50 cl::init(HWMultNoIntr),
51 cl::values(
52 clEnumValN(NoHWMult, "no",
53 "Do not use hardware multiplier"),
54 clEnumValN(HWMultIntr, "interrupts",
55 "Assume hardware multiplier can be used inside interrupts"),
56 clEnumValN(HWMultNoIntr, "use",
57 "Assume hardware multiplier cannot be used inside interrupts"),
58 clEnumValEnd));
59
MSP430TargetLowering(const TargetMachine & TM,const MSP430Subtarget & STI)60 MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM,
61 const MSP430Subtarget &STI)
62 : TargetLowering(TM) {
63
64 // Set up the register classes.
65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
67
68 // Compute derived properties from the register classes
69 computeRegisterProperties(STI.getRegisterInfo());
70
71 // Provide all sorts of operation actions
72
73 // Division is expensive
74 setIntDivIsCheap(false);
75
76 setStackPointerRegisterToSaveRestore(MSP430::SP);
77 setBooleanContents(ZeroOrOneBooleanContent);
78 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
79
80 // We have post-incremented loads / stores.
81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal);
82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal);
83
84 for (MVT VT : MVT::integer_valuetypes()) {
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand);
90 }
91
92 // We don't have any truncstores
93 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
94
95 setOperationAction(ISD::SRA, MVT::i8, Custom);
96 setOperationAction(ISD::SHL, MVT::i8, Custom);
97 setOperationAction(ISD::SRL, MVT::i8, Custom);
98 setOperationAction(ISD::SRA, MVT::i16, Custom);
99 setOperationAction(ISD::SHL, MVT::i16, Custom);
100 setOperationAction(ISD::SRL, MVT::i16, Custom);
101 setOperationAction(ISD::ROTL, MVT::i8, Expand);
102 setOperationAction(ISD::ROTR, MVT::i8, Expand);
103 setOperationAction(ISD::ROTL, MVT::i16, Expand);
104 setOperationAction(ISD::ROTR, MVT::i16, Expand);
105 setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
106 setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
107 setOperationAction(ISD::BlockAddress, MVT::i16, Custom);
108 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
109 setOperationAction(ISD::BR_CC, MVT::i8, Custom);
110 setOperationAction(ISD::BR_CC, MVT::i16, Custom);
111 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
112 setOperationAction(ISD::SETCC, MVT::i8, Custom);
113 setOperationAction(ISD::SETCC, MVT::i16, Custom);
114 setOperationAction(ISD::SELECT, MVT::i8, Expand);
115 setOperationAction(ISD::SELECT, MVT::i16, Expand);
116 setOperationAction(ISD::SELECT_CC, MVT::i8, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
118 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom);
119 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i8, Expand);
120 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i16, Expand);
121
122 setOperationAction(ISD::CTTZ, MVT::i8, Expand);
123 setOperationAction(ISD::CTTZ, MVT::i16, Expand);
124 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand);
125 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
126 setOperationAction(ISD::CTLZ, MVT::i8, Expand);
127 setOperationAction(ISD::CTLZ, MVT::i16, Expand);
128 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand);
129 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand);
130 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
131 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
132
133 setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
134 setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
135 setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
136 setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
139
140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
141
142 // FIXME: Implement efficiently multiplication by a constant
143 setOperationAction(ISD::MUL, MVT::i8, Expand);
144 setOperationAction(ISD::MULHS, MVT::i8, Expand);
145 setOperationAction(ISD::MULHU, MVT::i8, Expand);
146 setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
147 setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
148 setOperationAction(ISD::MUL, MVT::i16, Expand);
149 setOperationAction(ISD::MULHS, MVT::i16, Expand);
150 setOperationAction(ISD::MULHU, MVT::i16, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
152 setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
153
154 setOperationAction(ISD::UDIV, MVT::i8, Expand);
155 setOperationAction(ISD::UDIVREM, MVT::i8, Expand);
156 setOperationAction(ISD::UREM, MVT::i8, Expand);
157 setOperationAction(ISD::SDIV, MVT::i8, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i8, Expand);
159 setOperationAction(ISD::SREM, MVT::i8, Expand);
160 setOperationAction(ISD::UDIV, MVT::i16, Expand);
161 setOperationAction(ISD::UDIVREM, MVT::i16, Expand);
162 setOperationAction(ISD::UREM, MVT::i16, Expand);
163 setOperationAction(ISD::SDIV, MVT::i16, Expand);
164 setOperationAction(ISD::SDIVREM, MVT::i16, Expand);
165 setOperationAction(ISD::SREM, MVT::i16, Expand);
166
167 // varargs support
168 setOperationAction(ISD::VASTART, MVT::Other, Custom);
169 setOperationAction(ISD::VAARG, MVT::Other, Expand);
170 setOperationAction(ISD::VAEND, MVT::Other, Expand);
171 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
172 setOperationAction(ISD::JumpTable, MVT::i16, Custom);
173
174 // Libcalls names.
175 if (HWMultMode == HWMultIntr) {
176 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw");
177 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw");
178 } else if (HWMultMode == HWMultNoIntr) {
179 setLibcallName(RTLIB::MUL_I8, "__mulqi3hw_noint");
180 setLibcallName(RTLIB::MUL_I16, "__mulhi3hw_noint");
181 }
182
183 setMinFunctionAlignment(1);
184 setPrefFunctionAlignment(2);
185 }
186
LowerOperation(SDValue Op,SelectionDAG & DAG) const187 SDValue MSP430TargetLowering::LowerOperation(SDValue Op,
188 SelectionDAG &DAG) const {
189 switch (Op.getOpcode()) {
190 case ISD::SHL: // FALLTHROUGH
191 case ISD::SRL:
192 case ISD::SRA: return LowerShifts(Op, DAG);
193 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
194 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
195 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
196 case ISD::SETCC: return LowerSETCC(Op, DAG);
197 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
198 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
199 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
200 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
201 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
202 case ISD::VASTART: return LowerVASTART(Op, DAG);
203 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
204 default:
205 llvm_unreachable("unimplemented operand");
206 }
207 }
208
209 //===----------------------------------------------------------------------===//
210 // MSP430 Inline Assembly Support
211 //===----------------------------------------------------------------------===//
212
213 /// getConstraintType - Given a constraint letter, return the type of
214 /// constraint it is for this target.
215 TargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const216 MSP430TargetLowering::getConstraintType(StringRef Constraint) const {
217 if (Constraint.size() == 1) {
218 switch (Constraint[0]) {
219 case 'r':
220 return C_RegisterClass;
221 default:
222 break;
223 }
224 }
225 return TargetLowering::getConstraintType(Constraint);
226 }
227
228 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const229 MSP430TargetLowering::getRegForInlineAsmConstraint(
230 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
231 if (Constraint.size() == 1) {
232 // GCC Constraint Letters
233 switch (Constraint[0]) {
234 default: break;
235 case 'r': // GENERAL_REGS
236 if (VT == MVT::i8)
237 return std::make_pair(0U, &MSP430::GR8RegClass);
238
239 return std::make_pair(0U, &MSP430::GR16RegClass);
240 }
241 }
242
243 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
244 }
245
246 //===----------------------------------------------------------------------===//
247 // Calling Convention Implementation
248 //===----------------------------------------------------------------------===//
249
250 #include "MSP430GenCallingConv.inc"
251
252 /// For each argument in a function store the number of pieces it is composed
253 /// of.
254 template<typename ArgT>
ParseFunctionArgs(const SmallVectorImpl<ArgT> & Args,SmallVectorImpl<unsigned> & Out)255 static void ParseFunctionArgs(const SmallVectorImpl<ArgT> &Args,
256 SmallVectorImpl<unsigned> &Out) {
257 unsigned CurrentArgIndex = ~0U;
258 for (unsigned i = 0, e = Args.size(); i != e; i++) {
259 if (CurrentArgIndex == Args[i].OrigArgIndex) {
260 Out.back()++;
261 } else {
262 Out.push_back(1);
263 CurrentArgIndex++;
264 }
265 }
266 }
267
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)268 static void AnalyzeVarArgs(CCState &State,
269 const SmallVectorImpl<ISD::OutputArg> &Outs) {
270 State.AnalyzeCallOperands(Outs, CC_MSP430_AssignStack);
271 }
272
AnalyzeVarArgs(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)273 static void AnalyzeVarArgs(CCState &State,
274 const SmallVectorImpl<ISD::InputArg> &Ins) {
275 State.AnalyzeFormalArguments(Ins, CC_MSP430_AssignStack);
276 }
277
278 /// Analyze incoming and outgoing function arguments. We need custom C++ code
279 /// to handle special constraints in the ABI like reversing the order of the
280 /// pieces of splitted arguments. In addition, all pieces of a certain argument
281 /// have to be passed either using registers or the stack but never mixing both.
282 template<typename ArgT>
AnalyzeArguments(CCState & State,SmallVectorImpl<CCValAssign> & ArgLocs,const SmallVectorImpl<ArgT> & Args)283 static void AnalyzeArguments(CCState &State,
284 SmallVectorImpl<CCValAssign> &ArgLocs,
285 const SmallVectorImpl<ArgT> &Args) {
286 static const MCPhysReg RegList[] = {
287 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
288 };
289 static const unsigned NbRegs = array_lengthof(RegList);
290
291 if (State.isVarArg()) {
292 AnalyzeVarArgs(State, Args);
293 return;
294 }
295
296 SmallVector<unsigned, 4> ArgsParts;
297 ParseFunctionArgs(Args, ArgsParts);
298
299 unsigned RegsLeft = NbRegs;
300 bool UseStack = false;
301 unsigned ValNo = 0;
302
303 for (unsigned i = 0, e = ArgsParts.size(); i != e; i++) {
304 MVT ArgVT = Args[ValNo].VT;
305 ISD::ArgFlagsTy ArgFlags = Args[ValNo].Flags;
306 MVT LocVT = ArgVT;
307 CCValAssign::LocInfo LocInfo = CCValAssign::Full;
308
309 // Promote i8 to i16
310 if (LocVT == MVT::i8) {
311 LocVT = MVT::i16;
312 if (ArgFlags.isSExt())
313 LocInfo = CCValAssign::SExt;
314 else if (ArgFlags.isZExt())
315 LocInfo = CCValAssign::ZExt;
316 else
317 LocInfo = CCValAssign::AExt;
318 }
319
320 // Handle byval arguments
321 if (ArgFlags.isByVal()) {
322 State.HandleByVal(ValNo++, ArgVT, LocVT, LocInfo, 2, 2, ArgFlags);
323 continue;
324 }
325
326 unsigned Parts = ArgsParts[i];
327
328 if (!UseStack && Parts <= RegsLeft) {
329 unsigned FirstVal = ValNo;
330 for (unsigned j = 0; j < Parts; j++) {
331 unsigned Reg = State.AllocateReg(RegList);
332 State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo));
333 RegsLeft--;
334 }
335
336 // Reverse the order of the pieces to agree with the "big endian" format
337 // required in the calling convention ABI.
338 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
339 std::reverse(B, B + Parts);
340 } else {
341 UseStack = true;
342 for (unsigned j = 0; j < Parts; j++)
343 CC_MSP430_AssignStack(ValNo++, ArgVT, LocVT, LocInfo, ArgFlags, State);
344 }
345 }
346 }
347
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::InputArg> & Ins)348 static void AnalyzeRetResult(CCState &State,
349 const SmallVectorImpl<ISD::InputArg> &Ins) {
350 State.AnalyzeCallResult(Ins, RetCC_MSP430);
351 }
352
AnalyzeRetResult(CCState & State,const SmallVectorImpl<ISD::OutputArg> & Outs)353 static void AnalyzeRetResult(CCState &State,
354 const SmallVectorImpl<ISD::OutputArg> &Outs) {
355 State.AnalyzeReturn(Outs, RetCC_MSP430);
356 }
357
358 template<typename ArgT>
AnalyzeReturnValues(CCState & State,SmallVectorImpl<CCValAssign> & RVLocs,const SmallVectorImpl<ArgT> & Args)359 static void AnalyzeReturnValues(CCState &State,
360 SmallVectorImpl<CCValAssign> &RVLocs,
361 const SmallVectorImpl<ArgT> &Args) {
362 AnalyzeRetResult(State, Args);
363
364 // Reverse splitted return values to get the "big endian" format required
365 // to agree with the calling convention ABI.
366 std::reverse(RVLocs.begin(), RVLocs.end());
367 }
368
369 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const370 MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
371 CallingConv::ID CallConv,
372 bool isVarArg,
373 const SmallVectorImpl<ISD::InputArg>
374 &Ins,
375 SDLoc dl,
376 SelectionDAG &DAG,
377 SmallVectorImpl<SDValue> &InVals)
378 const {
379
380 switch (CallConv) {
381 default:
382 llvm_unreachable("Unsupported calling convention");
383 case CallingConv::C:
384 case CallingConv::Fast:
385 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
386 case CallingConv::MSP430_INTR:
387 if (Ins.empty())
388 return Chain;
389 report_fatal_error("ISRs cannot have arguments");
390 }
391 }
392
393 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const394 MSP430TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
395 SmallVectorImpl<SDValue> &InVals) const {
396 SelectionDAG &DAG = CLI.DAG;
397 SDLoc &dl = CLI.DL;
398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
399 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
400 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
401 SDValue Chain = CLI.Chain;
402 SDValue Callee = CLI.Callee;
403 bool &isTailCall = CLI.IsTailCall;
404 CallingConv::ID CallConv = CLI.CallConv;
405 bool isVarArg = CLI.IsVarArg;
406
407 // MSP430 target does not yet support tail call optimization.
408 isTailCall = false;
409
410 switch (CallConv) {
411 default:
412 llvm_unreachable("Unsupported calling convention");
413 case CallingConv::Fast:
414 case CallingConv::C:
415 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
416 Outs, OutVals, Ins, dl, DAG, InVals);
417 case CallingConv::MSP430_INTR:
418 report_fatal_error("ISRs cannot be called directly");
419 }
420 }
421
422 /// LowerCCCArguments - transform physical registers into virtual registers and
423 /// generate load operations for arguments places on the stack.
424 // FIXME: struct return stuff
425 SDValue
LowerCCCArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const426 MSP430TargetLowering::LowerCCCArguments(SDValue Chain,
427 CallingConv::ID CallConv,
428 bool isVarArg,
429 const SmallVectorImpl<ISD::InputArg>
430 &Ins,
431 SDLoc dl,
432 SelectionDAG &DAG,
433 SmallVectorImpl<SDValue> &InVals)
434 const {
435 MachineFunction &MF = DAG.getMachineFunction();
436 MachineFrameInfo *MFI = MF.getFrameInfo();
437 MachineRegisterInfo &RegInfo = MF.getRegInfo();
438 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
439
440 // Assign locations to all of the incoming arguments.
441 SmallVector<CCValAssign, 16> ArgLocs;
442 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
443 *DAG.getContext());
444 AnalyzeArguments(CCInfo, ArgLocs, Ins);
445
446 // Create frame index for the start of the first vararg value
447 if (isVarArg) {
448 unsigned Offset = CCInfo.getNextStackOffset();
449 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, Offset, true));
450 }
451
452 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
453 CCValAssign &VA = ArgLocs[i];
454 if (VA.isRegLoc()) {
455 // Arguments passed in registers
456 EVT RegVT = VA.getLocVT();
457 switch (RegVT.getSimpleVT().SimpleTy) {
458 default:
459 {
460 #ifndef NDEBUG
461 errs() << "LowerFormalArguments Unhandled argument type: "
462 << RegVT.getSimpleVT().SimpleTy << "\n";
463 #endif
464 llvm_unreachable(nullptr);
465 }
466 case MVT::i16:
467 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
468 RegInfo.addLiveIn(VA.getLocReg(), VReg);
469 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
470
471 // If this is an 8-bit value, it is really passed promoted to 16
472 // bits. Insert an assert[sz]ext to capture this, then truncate to the
473 // right size.
474 if (VA.getLocInfo() == CCValAssign::SExt)
475 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
476 DAG.getValueType(VA.getValVT()));
477 else if (VA.getLocInfo() == CCValAssign::ZExt)
478 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
479 DAG.getValueType(VA.getValVT()));
480
481 if (VA.getLocInfo() != CCValAssign::Full)
482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
483
484 InVals.push_back(ArgValue);
485 }
486 } else {
487 // Sanity check
488 assert(VA.isMemLoc());
489
490 SDValue InVal;
491 ISD::ArgFlagsTy Flags = Ins[i].Flags;
492
493 if (Flags.isByVal()) {
494 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
495 VA.getLocMemOffset(), true);
496 InVal = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
497 } else {
498 // Load the argument to a virtual register
499 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
500 if (ObjSize > 2) {
501 errs() << "LowerFormalArguments Unhandled argument type: "
502 << EVT(VA.getLocVT()).getEVTString()
503 << "\n";
504 }
505 // Create the frame index object for this incoming parameter...
506 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true);
507
508 // Create the SelectionDAG nodes corresponding to a load
509 //from this parameter
510 SDValue FIN = DAG.getFrameIndex(FI, MVT::i16);
511 InVal = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
512 MachinePointerInfo::getFixedStack(FI),
513 false, false, false, 0);
514 }
515
516 InVals.push_back(InVal);
517 }
518 }
519
520 return Chain;
521 }
522
523 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc dl,SelectionDAG & DAG) const524 MSP430TargetLowering::LowerReturn(SDValue Chain,
525 CallingConv::ID CallConv, bool isVarArg,
526 const SmallVectorImpl<ISD::OutputArg> &Outs,
527 const SmallVectorImpl<SDValue> &OutVals,
528 SDLoc dl, SelectionDAG &DAG) const {
529
530 // CCValAssign - represent the assignment of the return value to a location
531 SmallVector<CCValAssign, 16> RVLocs;
532
533 // ISRs cannot return any value.
534 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty())
535 report_fatal_error("ISRs cannot return any value");
536
537 // CCState - Info about the registers and stack slot.
538 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
539 *DAG.getContext());
540
541 // Analize return values.
542 AnalyzeReturnValues(CCInfo, RVLocs, Outs);
543
544 SDValue Flag;
545 SmallVector<SDValue, 4> RetOps(1, Chain);
546
547 // Copy the result values into the output registers.
548 for (unsigned i = 0; i != RVLocs.size(); ++i) {
549 CCValAssign &VA = RVLocs[i];
550 assert(VA.isRegLoc() && "Can only return in registers!");
551
552 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
553 OutVals[i], Flag);
554
555 // Guarantee that all emitted copies are stuck together,
556 // avoiding something bad.
557 Flag = Chain.getValue(1);
558 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
559 }
560
561 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
562 MSP430ISD::RETI_FLAG : MSP430ISD::RET_FLAG);
563
564 RetOps[0] = Chain; // Update chain.
565
566 // Add the flag if we have it.
567 if (Flag.getNode())
568 RetOps.push_back(Flag);
569
570 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
571 }
572
573 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
574 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
575 // TODO: sret.
576 SDValue
LowerCCCCallTo(SDValue Chain,SDValue Callee,CallingConv::ID CallConv,bool isVarArg,bool isTailCall,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const577 MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
578 CallingConv::ID CallConv, bool isVarArg,
579 bool isTailCall,
580 const SmallVectorImpl<ISD::OutputArg>
581 &Outs,
582 const SmallVectorImpl<SDValue> &OutVals,
583 const SmallVectorImpl<ISD::InputArg> &Ins,
584 SDLoc dl, SelectionDAG &DAG,
585 SmallVectorImpl<SDValue> &InVals) const {
586 // Analyze operands of the call, assigning locations to each operand.
587 SmallVector<CCValAssign, 16> ArgLocs;
588 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
589 *DAG.getContext());
590 AnalyzeArguments(CCInfo, ArgLocs, Outs);
591
592 // Get a count of how many bytes are to be pushed on the stack.
593 unsigned NumBytes = CCInfo.getNextStackOffset();
594 auto PtrVT = getPointerTy(DAG.getDataLayout());
595
596 Chain = DAG.getCALLSEQ_START(Chain,
597 DAG.getConstant(NumBytes, dl, PtrVT, true), dl);
598
599 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
600 SmallVector<SDValue, 12> MemOpChains;
601 SDValue StackPtr;
602
603 // Walk the register/memloc assignments, inserting copies/loads.
604 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
605 CCValAssign &VA = ArgLocs[i];
606
607 SDValue Arg = OutVals[i];
608
609 // Promote the value if needed.
610 switch (VA.getLocInfo()) {
611 default: llvm_unreachable("Unknown loc info!");
612 case CCValAssign::Full: break;
613 case CCValAssign::SExt:
614 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
615 break;
616 case CCValAssign::ZExt:
617 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
618 break;
619 case CCValAssign::AExt:
620 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
621 break;
622 }
623
624 // Arguments that can be passed on register must be kept at RegsToPass
625 // vector
626 if (VA.isRegLoc()) {
627 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
628 } else {
629 assert(VA.isMemLoc());
630
631 if (!StackPtr.getNode())
632 StackPtr = DAG.getCopyFromReg(Chain, dl, MSP430::SP, PtrVT);
633
634 SDValue PtrOff =
635 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
636 DAG.getIntPtrConstant(VA.getLocMemOffset(), dl));
637
638 SDValue MemOp;
639 ISD::ArgFlagsTy Flags = Outs[i].Flags;
640
641 if (Flags.isByVal()) {
642 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i16);
643 MemOp = DAG.getMemcpy(Chain, dl, PtrOff, Arg, SizeNode,
644 Flags.getByValAlign(),
645 /*isVolatile*/false,
646 /*AlwaysInline=*/true,
647 /*isTailCall=*/false,
648 MachinePointerInfo(),
649 MachinePointerInfo());
650 } else {
651 MemOp = DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(),
652 false, false, 0);
653 }
654
655 MemOpChains.push_back(MemOp);
656 }
657 }
658
659 // Transform all store nodes into one single node because all store nodes are
660 // independent of each other.
661 if (!MemOpChains.empty())
662 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
663
664 // Build a sequence of copy-to-reg nodes chained together with token chain and
665 // flag operands which copy the outgoing args into registers. The InFlag in
666 // necessary since all emitted instructions must be stuck together.
667 SDValue InFlag;
668 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
669 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
670 RegsToPass[i].second, InFlag);
671 InFlag = Chain.getValue(1);
672 }
673
674 // If the callee is a GlobalAddress node (quite common, every direct call is)
675 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
676 // Likewise ExternalSymbol -> TargetExternalSymbol.
677 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
678 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i16);
679 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
680 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16);
681
682 // Returns a chain & a flag for retval copy to use.
683 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
684 SmallVector<SDValue, 8> Ops;
685 Ops.push_back(Chain);
686 Ops.push_back(Callee);
687
688 // Add argument registers to the end of the list so that they are
689 // known live into the call.
690 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
691 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
692 RegsToPass[i].second.getValueType()));
693
694 if (InFlag.getNode())
695 Ops.push_back(InFlag);
696
697 Chain = DAG.getNode(MSP430ISD::CALL, dl, NodeTys, Ops);
698 InFlag = Chain.getValue(1);
699
700 // Create the CALLSEQ_END node.
701 Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, dl, PtrVT, true),
702 DAG.getConstant(0, dl, PtrVT, true), InFlag, dl);
703 InFlag = Chain.getValue(1);
704
705 // Handle result values, copying them out of physregs into vregs that we
706 // return.
707 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
708 DAG, InVals);
709 }
710
711 /// LowerCallResult - Lower the result values of a call into the
712 /// appropriate copies out of appropriate physical registers.
713 ///
714 SDValue
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const715 MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
716 CallingConv::ID CallConv, bool isVarArg,
717 const SmallVectorImpl<ISD::InputArg> &Ins,
718 SDLoc dl, SelectionDAG &DAG,
719 SmallVectorImpl<SDValue> &InVals) const {
720
721 // Assign locations to each value returned by this call.
722 SmallVector<CCValAssign, 16> RVLocs;
723 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
724 *DAG.getContext());
725
726 AnalyzeReturnValues(CCInfo, RVLocs, Ins);
727
728 // Copy all of the result registers out of their specified physreg.
729 for (unsigned i = 0; i != RVLocs.size(); ++i) {
730 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
731 RVLocs[i].getValVT(), InFlag).getValue(1);
732 InFlag = Chain.getValue(2);
733 InVals.push_back(Chain.getValue(0));
734 }
735
736 return Chain;
737 }
738
LowerShifts(SDValue Op,SelectionDAG & DAG) const739 SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
740 SelectionDAG &DAG) const {
741 unsigned Opc = Op.getOpcode();
742 SDNode* N = Op.getNode();
743 EVT VT = Op.getValueType();
744 SDLoc dl(N);
745
746 // Expand non-constant shifts to loops:
747 if (!isa<ConstantSDNode>(N->getOperand(1)))
748 switch (Opc) {
749 default: llvm_unreachable("Invalid shift opcode!");
750 case ISD::SHL:
751 return DAG.getNode(MSP430ISD::SHL, dl,
752 VT, N->getOperand(0), N->getOperand(1));
753 case ISD::SRA:
754 return DAG.getNode(MSP430ISD::SRA, dl,
755 VT, N->getOperand(0), N->getOperand(1));
756 case ISD::SRL:
757 return DAG.getNode(MSP430ISD::SRL, dl,
758 VT, N->getOperand(0), N->getOperand(1));
759 }
760
761 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
762
763 // Expand the stuff into sequence of shifts.
764 // FIXME: for some shift amounts this might be done better!
765 // E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
766 SDValue Victim = N->getOperand(0);
767
768 if (Opc == ISD::SRL && ShiftAmount) {
769 // Emit a special goodness here:
770 // srl A, 1 => clrc; rrc A
771 Victim = DAG.getNode(MSP430ISD::RRC, dl, VT, Victim);
772 ShiftAmount -= 1;
773 }
774
775 while (ShiftAmount--)
776 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
777 dl, VT, Victim);
778
779 return Victim;
780 }
781
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const782 SDValue MSP430TargetLowering::LowerGlobalAddress(SDValue Op,
783 SelectionDAG &DAG) const {
784 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
785 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
786 auto PtrVT = getPointerTy(DAG.getDataLayout());
787
788 // Create the TargetGlobalAddress node, folding in the constant offset.
789 SDValue Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op), PtrVT, Offset);
790 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(Op), PtrVT, Result);
791 }
792
LowerExternalSymbol(SDValue Op,SelectionDAG & DAG) const793 SDValue MSP430TargetLowering::LowerExternalSymbol(SDValue Op,
794 SelectionDAG &DAG) const {
795 SDLoc dl(Op);
796 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
797 auto PtrVT = getPointerTy(DAG.getDataLayout());
798 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT);
799
800 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
801 }
802
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const803 SDValue MSP430TargetLowering::LowerBlockAddress(SDValue Op,
804 SelectionDAG &DAG) const {
805 SDLoc dl(Op);
806 auto PtrVT = getPointerTy(DAG.getDataLayout());
807 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
808 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT);
809
810 return DAG.getNode(MSP430ISD::Wrapper, dl, PtrVT, Result);
811 }
812
EmitCMP(SDValue & LHS,SDValue & RHS,SDValue & TargetCC,ISD::CondCode CC,SDLoc dl,SelectionDAG & DAG)813 static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, SDValue &TargetCC,
814 ISD::CondCode CC,
815 SDLoc dl, SelectionDAG &DAG) {
816 // FIXME: Handle bittests someday
817 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
818
819 // FIXME: Handle jump negative someday
820 MSP430CC::CondCodes TCC = MSP430CC::COND_INVALID;
821 switch (CC) {
822 default: llvm_unreachable("Invalid integer condition!");
823 case ISD::SETEQ:
824 TCC = MSP430CC::COND_E; // aka COND_Z
825 // Minor optimization: if LHS is a constant, swap operands, then the
826 // constant can be folded into comparison.
827 if (LHS.getOpcode() == ISD::Constant)
828 std::swap(LHS, RHS);
829 break;
830 case ISD::SETNE:
831 TCC = MSP430CC::COND_NE; // aka COND_NZ
832 // Minor optimization: if LHS is a constant, swap operands, then the
833 // constant can be folded into comparison.
834 if (LHS.getOpcode() == ISD::Constant)
835 std::swap(LHS, RHS);
836 break;
837 case ISD::SETULE:
838 std::swap(LHS, RHS); // FALLTHROUGH
839 case ISD::SETUGE:
840 // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
841 // fold constant into instruction.
842 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
843 LHS = RHS;
844 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
845 TCC = MSP430CC::COND_LO;
846 break;
847 }
848 TCC = MSP430CC::COND_HS; // aka COND_C
849 break;
850 case ISD::SETUGT:
851 std::swap(LHS, RHS); // FALLTHROUGH
852 case ISD::SETULT:
853 // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
854 // fold constant into instruction.
855 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
856 LHS = RHS;
857 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
858 TCC = MSP430CC::COND_HS;
859 break;
860 }
861 TCC = MSP430CC::COND_LO; // aka COND_NC
862 break;
863 case ISD::SETLE:
864 std::swap(LHS, RHS); // FALLTHROUGH
865 case ISD::SETGE:
866 // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
867 // fold constant into instruction.
868 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
869 LHS = RHS;
870 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
871 TCC = MSP430CC::COND_L;
872 break;
873 }
874 TCC = MSP430CC::COND_GE;
875 break;
876 case ISD::SETGT:
877 std::swap(LHS, RHS); // FALLTHROUGH
878 case ISD::SETLT:
879 // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
880 // fold constant into instruction.
881 if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
882 LHS = RHS;
883 RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
884 TCC = MSP430CC::COND_GE;
885 break;
886 }
887 TCC = MSP430CC::COND_L;
888 break;
889 }
890
891 TargetCC = DAG.getConstant(TCC, dl, MVT::i8);
892 return DAG.getNode(MSP430ISD::CMP, dl, MVT::Glue, LHS, RHS);
893 }
894
895
LowerBR_CC(SDValue Op,SelectionDAG & DAG) const896 SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
897 SDValue Chain = Op.getOperand(0);
898 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
899 SDValue LHS = Op.getOperand(2);
900 SDValue RHS = Op.getOperand(3);
901 SDValue Dest = Op.getOperand(4);
902 SDLoc dl (Op);
903
904 SDValue TargetCC;
905 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
906
907 return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(),
908 Chain, Dest, TargetCC, Flag);
909 }
910
LowerSETCC(SDValue Op,SelectionDAG & DAG) const911 SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
912 SDValue LHS = Op.getOperand(0);
913 SDValue RHS = Op.getOperand(1);
914 SDLoc dl (Op);
915
916 // If we are doing an AND and testing against zero, then the CMP
917 // will not be generated. The AND (or BIT) will generate the condition codes,
918 // but they are different from CMP.
919 // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
920 // lowering & isel wouldn't diverge.
921 bool andCC = false;
922 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
923 if (RHSC->isNullValue() && LHS.hasOneUse() &&
924 (LHS.getOpcode() == ISD::AND ||
925 (LHS.getOpcode() == ISD::TRUNCATE &&
926 LHS.getOperand(0).getOpcode() == ISD::AND))) {
927 andCC = true;
928 }
929 }
930 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
931 SDValue TargetCC;
932 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
933
934 // Get the condition codes directly from the status register, if its easy.
935 // Otherwise a branch will be generated. Note that the AND and BIT
936 // instructions generate different flags than CMP, the carry bit can be used
937 // for NE/EQ.
938 bool Invert = false;
939 bool Shift = false;
940 bool Convert = true;
941 switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
942 default:
943 Convert = false;
944 break;
945 case MSP430CC::COND_HS:
946 // Res = SR & 1, no processing is required
947 break;
948 case MSP430CC::COND_LO:
949 // Res = ~(SR & 1)
950 Invert = true;
951 break;
952 case MSP430CC::COND_NE:
953 if (andCC) {
954 // C = ~Z, thus Res = SR & 1, no processing is required
955 } else {
956 // Res = ~((SR >> 1) & 1)
957 Shift = true;
958 Invert = true;
959 }
960 break;
961 case MSP430CC::COND_E:
962 Shift = true;
963 // C = ~Z for AND instruction, thus we can put Res = ~(SR & 1), however,
964 // Res = (SR >> 1) & 1 is 1 word shorter.
965 break;
966 }
967 EVT VT = Op.getValueType();
968 SDValue One = DAG.getConstant(1, dl, VT);
969 if (Convert) {
970 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SR,
971 MVT::i16, Flag);
972 if (Shift)
973 // FIXME: somewhere this is turned into a SRL, lower it MSP specific?
974 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One);
975 SR = DAG.getNode(ISD::AND, dl, MVT::i16, SR, One);
976 if (Invert)
977 SR = DAG.getNode(ISD::XOR, dl, MVT::i16, SR, One);
978 return SR;
979 } else {
980 SDValue Zero = DAG.getConstant(0, dl, VT);
981 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
982 SDValue Ops[] = {One, Zero, TargetCC, Flag};
983 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
984 }
985 }
986
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const987 SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op,
988 SelectionDAG &DAG) const {
989 SDValue LHS = Op.getOperand(0);
990 SDValue RHS = Op.getOperand(1);
991 SDValue TrueV = Op.getOperand(2);
992 SDValue FalseV = Op.getOperand(3);
993 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
994 SDLoc dl (Op);
995
996 SDValue TargetCC;
997 SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG);
998
999 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1000 SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag};
1001
1002 return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops);
1003 }
1004
LowerSIGN_EXTEND(SDValue Op,SelectionDAG & DAG) const1005 SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op,
1006 SelectionDAG &DAG) const {
1007 SDValue Val = Op.getOperand(0);
1008 EVT VT = Op.getValueType();
1009 SDLoc dl(Op);
1010
1011 assert(VT == MVT::i16 && "Only support i16 for now!");
1012
1013 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT,
1014 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val),
1015 DAG.getValueType(Val.getValueType()));
1016 }
1017
1018 SDValue
getReturnAddressFrameIndex(SelectionDAG & DAG) const1019 MSP430TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
1020 MachineFunction &MF = DAG.getMachineFunction();
1021 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1022 int ReturnAddrIndex = FuncInfo->getRAIndex();
1023 auto PtrVT = getPointerTy(MF.getDataLayout());
1024
1025 if (ReturnAddrIndex == 0) {
1026 // Set up a frame object for the return address.
1027 uint64_t SlotSize = MF.getDataLayout().getPointerSize();
1028 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
1029 true);
1030 FuncInfo->setRAIndex(ReturnAddrIndex);
1031 }
1032
1033 return DAG.getFrameIndex(ReturnAddrIndex, PtrVT);
1034 }
1035
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1036 SDValue MSP430TargetLowering::LowerRETURNADDR(SDValue Op,
1037 SelectionDAG &DAG) const {
1038 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1039 MFI->setReturnAddressIsTaken(true);
1040
1041 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1042 return SDValue();
1043
1044 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1045 SDLoc dl(Op);
1046 auto PtrVT = getPointerTy(DAG.getDataLayout());
1047
1048 if (Depth > 0) {
1049 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1050 SDValue Offset =
1051 DAG.getConstant(DAG.getDataLayout().getPointerSize(), dl, MVT::i16);
1052 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1053 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
1054 MachinePointerInfo(), false, false, false, 0);
1055 }
1056
1057 // Just load the return address.
1058 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
1059 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
1060 MachinePointerInfo(), false, false, false, 0);
1061 }
1062
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1063 SDValue MSP430TargetLowering::LowerFRAMEADDR(SDValue Op,
1064 SelectionDAG &DAG) const {
1065 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1066 MFI->setFrameAddressIsTaken(true);
1067
1068 EVT VT = Op.getValueType();
1069 SDLoc dl(Op); // FIXME probably not meaningful
1070 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1071 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1072 MSP430::FP, VT);
1073 while (Depth--)
1074 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1075 MachinePointerInfo(),
1076 false, false, false, 0);
1077 return FrameAddr;
1078 }
1079
LowerVASTART(SDValue Op,SelectionDAG & DAG) const1080 SDValue MSP430TargetLowering::LowerVASTART(SDValue Op,
1081 SelectionDAG &DAG) const {
1082 MachineFunction &MF = DAG.getMachineFunction();
1083 MSP430MachineFunctionInfo *FuncInfo = MF.getInfo<MSP430MachineFunctionInfo>();
1084 auto PtrVT = getPointerTy(DAG.getDataLayout());
1085
1086 // Frame index of first vararg argument
1087 SDValue FrameIndex =
1088 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1089 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1090
1091 // Create a store of the frame index to the location operand
1092 return DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex,
1093 Op.getOperand(1), MachinePointerInfo(SV),
1094 false, false, 0);
1095 }
1096
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1097 SDValue MSP430TargetLowering::LowerJumpTable(SDValue Op,
1098 SelectionDAG &DAG) const {
1099 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1100 auto PtrVT = getPointerTy(DAG.getDataLayout());
1101 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1102 return DAG.getNode(MSP430ISD::Wrapper, SDLoc(JT), PtrVT, Result);
1103 }
1104
1105 /// getPostIndexedAddressParts - returns true by value, base pointer and
1106 /// offset pointer and addressing mode by reference if this node can be
1107 /// combined with a load / store to form a post-indexed load / store.
getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const1108 bool MSP430TargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1109 SDValue &Base,
1110 SDValue &Offset,
1111 ISD::MemIndexedMode &AM,
1112 SelectionDAG &DAG) const {
1113
1114 LoadSDNode *LD = cast<LoadSDNode>(N);
1115 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
1116 return false;
1117
1118 EVT VT = LD->getMemoryVT();
1119 if (VT != MVT::i8 && VT != MVT::i16)
1120 return false;
1121
1122 if (Op->getOpcode() != ISD::ADD)
1123 return false;
1124
1125 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
1126 uint64_t RHSC = RHS->getZExtValue();
1127 if ((VT == MVT::i16 && RHSC != 2) ||
1128 (VT == MVT::i8 && RHSC != 1))
1129 return false;
1130
1131 Base = Op->getOperand(0);
1132 Offset = DAG.getConstant(RHSC, SDLoc(N), VT);
1133 AM = ISD::POST_INC;
1134 return true;
1135 }
1136
1137 return false;
1138 }
1139
1140
getTargetNodeName(unsigned Opcode) const1141 const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
1142 switch ((MSP430ISD::NodeType)Opcode) {
1143 case MSP430ISD::FIRST_NUMBER: break;
1144 case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
1145 case MSP430ISD::RETI_FLAG: return "MSP430ISD::RETI_FLAG";
1146 case MSP430ISD::RRA: return "MSP430ISD::RRA";
1147 case MSP430ISD::RLA: return "MSP430ISD::RLA";
1148 case MSP430ISD::RRC: return "MSP430ISD::RRC";
1149 case MSP430ISD::CALL: return "MSP430ISD::CALL";
1150 case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
1151 case MSP430ISD::BR_CC: return "MSP430ISD::BR_CC";
1152 case MSP430ISD::CMP: return "MSP430ISD::CMP";
1153 case MSP430ISD::SETCC: return "MSP430ISD::SETCC";
1154 case MSP430ISD::SELECT_CC: return "MSP430ISD::SELECT_CC";
1155 case MSP430ISD::SHL: return "MSP430ISD::SHL";
1156 case MSP430ISD::SRA: return "MSP430ISD::SRA";
1157 case MSP430ISD::SRL: return "MSP430ISD::SRL";
1158 }
1159 return nullptr;
1160 }
1161
isTruncateFree(Type * Ty1,Type * Ty2) const1162 bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
1163 Type *Ty2) const {
1164 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
1165 return false;
1166
1167 return (Ty1->getPrimitiveSizeInBits() > Ty2->getPrimitiveSizeInBits());
1168 }
1169
isTruncateFree(EVT VT1,EVT VT2) const1170 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
1171 if (!VT1.isInteger() || !VT2.isInteger())
1172 return false;
1173
1174 return (VT1.getSizeInBits() > VT2.getSizeInBits());
1175 }
1176
isZExtFree(Type * Ty1,Type * Ty2) const1177 bool MSP430TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
1178 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1179 return 0 && Ty1->isIntegerTy(8) && Ty2->isIntegerTy(16);
1180 }
1181
isZExtFree(EVT VT1,EVT VT2) const1182 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
1183 // MSP430 implicitly zero-extends 8-bit results in 16-bit registers.
1184 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16;
1185 }
1186
isZExtFree(SDValue Val,EVT VT2) const1187 bool MSP430TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1188 return isZExtFree(Val.getValueType(), VT2);
1189 }
1190
1191 //===----------------------------------------------------------------------===//
1192 // Other Lowering Code
1193 //===----------------------------------------------------------------------===//
1194
1195 MachineBasicBlock*
EmitShiftInstr(MachineInstr * MI,MachineBasicBlock * BB) const1196 MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,
1197 MachineBasicBlock *BB) const {
1198 MachineFunction *F = BB->getParent();
1199 MachineRegisterInfo &RI = F->getRegInfo();
1200 DebugLoc dl = MI->getDebugLoc();
1201 const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo();
1202
1203 unsigned Opc;
1204 const TargetRegisterClass * RC;
1205 switch (MI->getOpcode()) {
1206 default: llvm_unreachable("Invalid shift opcode!");
1207 case MSP430::Shl8:
1208 Opc = MSP430::SHL8r1;
1209 RC = &MSP430::GR8RegClass;
1210 break;
1211 case MSP430::Shl16:
1212 Opc = MSP430::SHL16r1;
1213 RC = &MSP430::GR16RegClass;
1214 break;
1215 case MSP430::Sra8:
1216 Opc = MSP430::SAR8r1;
1217 RC = &MSP430::GR8RegClass;
1218 break;
1219 case MSP430::Sra16:
1220 Opc = MSP430::SAR16r1;
1221 RC = &MSP430::GR16RegClass;
1222 break;
1223 case MSP430::Srl8:
1224 Opc = MSP430::SAR8r1c;
1225 RC = &MSP430::GR8RegClass;
1226 break;
1227 case MSP430::Srl16:
1228 Opc = MSP430::SAR16r1c;
1229 RC = &MSP430::GR16RegClass;
1230 break;
1231 }
1232
1233 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1234 MachineFunction::iterator I = BB;
1235 ++I;
1236
1237 // Create loop block
1238 MachineBasicBlock *LoopBB = F->CreateMachineBasicBlock(LLVM_BB);
1239 MachineBasicBlock *RemBB = F->CreateMachineBasicBlock(LLVM_BB);
1240
1241 F->insert(I, LoopBB);
1242 F->insert(I, RemBB);
1243
1244 // Update machine-CFG edges by transferring all successors of the current
1245 // block to the block containing instructions after shift.
1246 RemBB->splice(RemBB->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
1247 BB->end());
1248 RemBB->transferSuccessorsAndUpdatePHIs(BB);
1249
1250 // Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
1251 BB->addSuccessor(LoopBB);
1252 BB->addSuccessor(RemBB);
1253 LoopBB->addSuccessor(RemBB);
1254 LoopBB->addSuccessor(LoopBB);
1255
1256 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass);
1257 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass);
1258 unsigned ShiftReg = RI.createVirtualRegister(RC);
1259 unsigned ShiftReg2 = RI.createVirtualRegister(RC);
1260 unsigned ShiftAmtSrcReg = MI->getOperand(2).getReg();
1261 unsigned SrcReg = MI->getOperand(1).getReg();
1262 unsigned DstReg = MI->getOperand(0).getReg();
1263
1264 // BB:
1265 // cmp 0, N
1266 // je RemBB
1267 BuildMI(BB, dl, TII.get(MSP430::CMP8ri))
1268 .addReg(ShiftAmtSrcReg).addImm(0);
1269 BuildMI(BB, dl, TII.get(MSP430::JCC))
1270 .addMBB(RemBB)
1271 .addImm(MSP430CC::COND_E);
1272
1273 // LoopBB:
1274 // ShiftReg = phi [%SrcReg, BB], [%ShiftReg2, LoopBB]
1275 // ShiftAmt = phi [%N, BB], [%ShiftAmt2, LoopBB]
1276 // ShiftReg2 = shift ShiftReg
1277 // ShiftAmt2 = ShiftAmt - 1;
1278 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftReg)
1279 .addReg(SrcReg).addMBB(BB)
1280 .addReg(ShiftReg2).addMBB(LoopBB);
1281 BuildMI(LoopBB, dl, TII.get(MSP430::PHI), ShiftAmtReg)
1282 .addReg(ShiftAmtSrcReg).addMBB(BB)
1283 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1284 BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2)
1285 .addReg(ShiftReg);
1286 BuildMI(LoopBB, dl, TII.get(MSP430::SUB8ri), ShiftAmtReg2)
1287 .addReg(ShiftAmtReg).addImm(1);
1288 BuildMI(LoopBB, dl, TII.get(MSP430::JCC))
1289 .addMBB(LoopBB)
1290 .addImm(MSP430CC::COND_NE);
1291
1292 // RemBB:
1293 // DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
1294 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1295 .addReg(SrcReg).addMBB(BB)
1296 .addReg(ShiftReg2).addMBB(LoopBB);
1297
1298 MI->eraseFromParent(); // The pseudo instruction is gone now.
1299 return RemBB;
1300 }
1301
1302 MachineBasicBlock*
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const1303 MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1304 MachineBasicBlock *BB) const {
1305 unsigned Opc = MI->getOpcode();
1306
1307 if (Opc == MSP430::Shl8 || Opc == MSP430::Shl16 ||
1308 Opc == MSP430::Sra8 || Opc == MSP430::Sra16 ||
1309 Opc == MSP430::Srl8 || Opc == MSP430::Srl16)
1310 return EmitShiftInstr(MI, BB);
1311
1312 const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
1313 DebugLoc dl = MI->getDebugLoc();
1314
1315 assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) &&
1316 "Unexpected instr type to insert");
1317
1318 // To "insert" a SELECT instruction, we actually have to insert the diamond
1319 // control-flow pattern. The incoming instruction knows the destination vreg
1320 // to set, the condition code register to branch on, the true/false values to
1321 // select between, and a branch opcode to use.
1322 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1323 MachineFunction::iterator I = BB;
1324 ++I;
1325
1326 // thisMBB:
1327 // ...
1328 // TrueVal = ...
1329 // cmpTY ccX, r1, r2
1330 // jCC copy1MBB
1331 // fallthrough --> copy0MBB
1332 MachineBasicBlock *thisMBB = BB;
1333 MachineFunction *F = BB->getParent();
1334 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1335 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
1336 F->insert(I, copy0MBB);
1337 F->insert(I, copy1MBB);
1338 // Update machine-CFG edges by transferring all successors of the current
1339 // block to the new block which will contain the Phi node for the select.
1340 copy1MBB->splice(copy1MBB->begin(), BB,
1341 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1342 copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
1343 // Next, add the true and fallthrough blocks as its successors.
1344 BB->addSuccessor(copy0MBB);
1345 BB->addSuccessor(copy1MBB);
1346
1347 BuildMI(BB, dl, TII.get(MSP430::JCC))
1348 .addMBB(copy1MBB)
1349 .addImm(MI->getOperand(3).getImm());
1350
1351 // copy0MBB:
1352 // %FalseValue = ...
1353 // # fallthrough to copy1MBB
1354 BB = copy0MBB;
1355
1356 // Update machine-CFG edges
1357 BB->addSuccessor(copy1MBB);
1358
1359 // copy1MBB:
1360 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1361 // ...
1362 BB = copy1MBB;
1363 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
1364 MI->getOperand(0).getReg())
1365 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1366 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1367
1368 MI->eraseFromParent(); // The pseudo instruction is gone now.
1369 return BB;
1370 }
1371