1//===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are: 11// - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12// - Available only on Evergreen family GPUs. 13// 14//===----------------------------------------------------------------------===// 15 16def isEG : Predicate< 17 "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget->hasCaymanISA()" 20>; 21 22def isEGorCayman : Predicate< 23 "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25>; 26 27//===----------------------------------------------------------------------===// 28// Evergreen / Cayman store instructions 29//===----------------------------------------------------------------------===// 30 31let Predicates = [isEGorCayman] in { 32 33class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 44 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 45 "MSKOR $rw_gpr.XW, $index_gpr", 46 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 47> { 48 let eop = 0; 49} 50 51} // End let Predicates = [isEGorCayman] 52 53//===----------------------------------------------------------------------===// 54// Evergreen Only instructions 55//===----------------------------------------------------------------------===// 56 57let Predicates = [isEG] in { 58 59def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 60defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 61 62def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 63def MULHI_INT_eg : MULHI_INT_Common<0x90>; 64def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 65def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 66def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 67def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 68def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 69def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 70def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 71def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 72def : RsqPat<RECIPSQRT_IEEE_eg, f32>; 73def SIN_eg : SIN_Common<0x8D>; 74def COS_eg : COS_Common<0x8E>; 75 76def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 77def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 78 79defm : Expand24IBitOps<MULLO_INT_eg, ADD_INT>; 80 81//===----------------------------------------------------------------------===// 82// Memory read/write instructions 83//===----------------------------------------------------------------------===// 84 85let usesCustomInserter = 1 in { 86 87// 32-bit store 88def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 89 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 90 "STORE_RAW $rw_gpr, $index_gpr, $eop", 91 [(global_store i32:$rw_gpr, i32:$index_gpr)] 92>; 93 94// 64-bit store 95def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 96 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 97 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 98 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 99>; 100 101//128-bit store 102def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 103 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 104 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 105 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 106>; 107 108} // End usesCustomInserter = 1 109 110class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 111 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> { 112 113 // Static fields 114 let VC_INST = 0; 115 let FETCH_TYPE = 2; 116 let FETCH_WHOLE_QUAD = 0; 117 let BUFFER_ID = buffer_id; 118 let SRC_REL = 0; 119 // XXX: We can infer this field based on the SRC_GPR. This would allow us 120 // to store vertex addresses in any channel, not just X. 121 let SRC_SEL_X = 0; 122 123 let Inst{31-0} = Word0; 124} 125 126class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern> 127 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 128 (outs R600_TReg32_X:$dst_gpr), pattern> { 129 130 let MEGA_FETCH_COUNT = 1; 131 let DST_SEL_X = 0; 132 let DST_SEL_Y = 7; // Masked 133 let DST_SEL_Z = 7; // Masked 134 let DST_SEL_W = 7; // Masked 135 let DATA_FORMAT = 1; // FMT_8 136} 137 138class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern> 139 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 140 (outs R600_TReg32_X:$dst_gpr), pattern> { 141 let MEGA_FETCH_COUNT = 2; 142 let DST_SEL_X = 0; 143 let DST_SEL_Y = 7; // Masked 144 let DST_SEL_Z = 7; // Masked 145 let DST_SEL_W = 7; // Masked 146 let DATA_FORMAT = 5; // FMT_16 147 148} 149 150class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 151 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 152 (outs R600_TReg32_X:$dst_gpr), pattern> { 153 154 let MEGA_FETCH_COUNT = 4; 155 let DST_SEL_X = 0; 156 let DST_SEL_Y = 7; // Masked 157 let DST_SEL_Z = 7; // Masked 158 let DST_SEL_W = 7; // Masked 159 let DATA_FORMAT = 0xD; // COLOR_32 160 161 // This is not really necessary, but there were some GPU hangs that appeared 162 // to be caused by ALU instructions in the next instruction group that wrote 163 // to the $src_gpr registers of the VTX_READ. 164 // e.g. 165 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 166 // %T2_X<def> = MOV %ZERO 167 //Adding this constraint prevents this from happening. 168 let Constraints = "$src_gpr.ptr = $dst_gpr"; 169} 170 171class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern> 172 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id, 173 (outs R600_Reg64:$dst_gpr), pattern> { 174 175 let MEGA_FETCH_COUNT = 8; 176 let DST_SEL_X = 0; 177 let DST_SEL_Y = 1; 178 let DST_SEL_Z = 7; 179 let DST_SEL_W = 7; 180 let DATA_FORMAT = 0x1D; // COLOR_32_32 181} 182 183class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 184 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 185 (outs R600_Reg128:$dst_gpr), pattern> { 186 187 let MEGA_FETCH_COUNT = 16; 188 let DST_SEL_X = 0; 189 let DST_SEL_Y = 1; 190 let DST_SEL_Z = 2; 191 let DST_SEL_W = 3; 192 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 193 194 // XXX: Need to force VTX_READ_128 instructions to write to the same register 195 // that holds its buffer address to avoid potential hangs. We can't use 196 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 197 // registers are different sizes. 198} 199 200//===----------------------------------------------------------------------===// 201// VTX Read from parameter memory space 202//===----------------------------------------------------------------------===// 203 204def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0, 205 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 206>; 207 208def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0, 209 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 210>; 211 212def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0, 213 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 214>; 215 216def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0, 217 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 218>; 219 220def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0, 221 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 222>; 223 224//===----------------------------------------------------------------------===// 225// VTX Read from global memory space 226//===----------------------------------------------------------------------===// 227 228// 8-bit reads 229def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1, 230 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 231>; 232 233def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1, 234 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 235>; 236 237// 32-bit reads 238def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1, 239 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 240>; 241 242// 64-bit reads 243def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1, 244 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 245>; 246 247// 128-bit reads 248def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, 249 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 250>; 251 252} // End Predicates = [isEG] 253 254//===----------------------------------------------------------------------===// 255// Evergreen / Cayman Instructions 256//===----------------------------------------------------------------------===// 257 258let Predicates = [isEGorCayman] in { 259 260// Should be predicated on FeatureFP64 261// def FMA_64 : R600_3OP < 262// 0xA, "FMA_64", 263// [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 264// >; 265 266// BFE_UINT - bit_extract, an optimization for mask and shift 267// Src0 = Input 268// Src1 = Offset 269// Src2 = Width 270// 271// bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 272// 273// Example Usage: 274// (Offset, Width) 275// 276// (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 277// (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 278// (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 279// (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 280def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 282 VecALU 283>; 284 285def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 287 VecALU 288>; 289 290def : BFEPattern <BFE_UINT_eg, MOV_IMM_I32>; 291 292def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 293 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 294 VecALU 295>; 296 297def : Pat<(i32 (sext_inreg i32:$src, i1)), 298 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 299def : Pat<(i32 (sext_inreg i32:$src, i8)), 300 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 301def : Pat<(i32 (sext_inreg i32:$src, i16)), 302 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 303 304defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32, R600_Reg64>; 305 306def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 307 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 308 VecALU 309>; 310 311def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 312 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 313>; 314 315def : UMad24Pat<MULADD_UINT24_eg>; 316 317def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 318def : ROTRPattern <BIT_ALIGN_INT_eg>; 319def MULADD_eg : MULADD_Common<0x14>; 320def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 321def FMA_eg : FMA_Common<0x7>; 322def ASHR_eg : ASHR_Common<0x15>; 323def LSHR_eg : LSHR_Common<0x16>; 324def LSHL_eg : LSHL_Common<0x17>; 325def CNDE_eg : CNDE_Common<0x19>; 326def CNDGT_eg : CNDGT_Common<0x1A>; 327def CNDGE_eg : CNDGE_Common<0x1B>; 328def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 329def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 330def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 331 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 332>; 333def DOT4_eg : DOT4_Common<0xBE>; 334defm CUBE_eg : CUBE_Common<0xC0>; 335 336def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 337 338def ADDC_UINT : R600_2OP_Helper <0x52, "ADDC_UINT", AMDGPUcarry>; 339def SUBB_UINT : R600_2OP_Helper <0x53, "SUBB_UINT", AMDGPUborrow>; 340 341def FFBH_UINT : R600_1OP_Helper <0xAB, "FFBH_UINT", ctlz_zero_undef, VecALU>; 342def FFBL_INT : R600_1OP_Helper <0xAC, "FFBL_INT", cttz_zero_undef, VecALU>; 343 344let hasSideEffects = 1 in { 345 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 346} 347 348def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 349 350def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 351 let Pattern = []; 352 let Itinerary = AnyALU; 353} 354 355def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 356 357def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 358 let Pattern = []; 359} 360 361def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 362 363def GROUP_BARRIER : InstR600 < 364 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, 365 R600ALU_Word0, 366 R600ALU_Word1_OP2 <0x54> { 367 368 let dst = 0; 369 let dst_rel = 0; 370 let src0 = 0; 371 let src0_rel = 0; 372 let src0_neg = 0; 373 let src0_abs = 0; 374 let src1 = 0; 375 let src1_rel = 0; 376 let src1_neg = 0; 377 let src1_abs = 0; 378 let write = 0; 379 let omod = 0; 380 let clamp = 0; 381 let last = 1; 382 let bank_swizzle = 0; 383 let pred_sel = 0; 384 let update_exec_mask = 0; 385 let update_pred = 0; 386 387 let Inst{31-0} = Word0; 388 let Inst{63-32} = Word1; 389 390 let ALUInst = 1; 391} 392 393def : Pat < 394 (int_AMDGPU_barrier_global), 395 (GROUP_BARRIER) 396>; 397 398//===----------------------------------------------------------------------===// 399// LDS Instructions 400//===----------------------------------------------------------------------===// 401class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 402 list<dag> pattern = []> : 403 404 InstR600 <outs, ins, asm, pattern, XALU>, 405 R600_ALU_LDS_Word0, 406 R600LDS_Word1 { 407 408 bits<6> offset = 0; 409 let lds_op = op; 410 411 let Word1{27} = offset{0}; 412 let Word1{12} = offset{1}; 413 let Word1{28} = offset{2}; 414 let Word1{31} = offset{3}; 415 let Word0{12} = offset{4}; 416 let Word0{25} = offset{5}; 417 418 419 let Inst{31-0} = Word0; 420 let Inst{63-32} = Word1; 421 422 let ALUInst = 1; 423 let HasNativeOperands = 1; 424 let UseNamedOperandTable = 1; 425} 426 427class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 428 lds_op, 429 (outs R600_Reg32:$dst), 430 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 431 LAST:$last, R600_Pred:$pred_sel, 432 BANK_SWIZZLE:$bank_swizzle), 433 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 434 pattern 435 > { 436 437 let src1 = 0; 438 let src1_rel = 0; 439 let src2 = 0; 440 let src2_rel = 0; 441 442 let usesCustomInserter = 1; 443 let LDS_1A = 1; 444 let DisableEncoding = "$dst"; 445} 446 447class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 448 string dst =""> : 449 R600_LDS < 450 lds_op, outs, 451 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 452 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 453 LAST:$last, R600_Pred:$pred_sel, 454 BANK_SWIZZLE:$bank_swizzle), 455 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 456 pattern 457 > { 458 459 field string BaseOp; 460 461 let src2 = 0; 462 let src2_rel = 0; 463 let LDS_1A1D = 1; 464} 465 466class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 467 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 468 let BaseOp = name; 469} 470 471class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 472 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 473 474 let BaseOp = name; 475 let usesCustomInserter = 1; 476 let DisableEncoding = "$dst"; 477} 478 479class R600_LDS_1A2D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 480 string dst =""> : 481 R600_LDS < 482 lds_op, outs, 483 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 484 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 485 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 486 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 487 " "#name# "$last "#dst#"$src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 488 pattern> { 489 490 field string BaseOp; 491 492 let LDS_1A1D = 0; 493 let LDS_1A2D = 1; 494} 495 496class R600_LDS_1A2D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 497 R600_LDS_1A2D <lds_op, (outs), name, pattern> { 498 let BaseOp = name; 499} 500 501class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> : 502 R600_LDS_1A2D <lds_op, (outs R600_Reg32:$dst), name, pattern> { 503 504 let BaseOp = name; 505 let usesCustomInserter = 1; 506 let DisableEncoding = "$dst"; 507} 508 509def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 510def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 511def LDS_AND : R600_LDS_1A1D_NORET <0x9, "LDS_AND", [] >; 512def LDS_OR : R600_LDS_1A1D_NORET <0xa, "LDS_OR", [] >; 513def LDS_XOR : R600_LDS_1A1D_NORET <0xb, "LDS_XOR", [] >; 514def LDS_WRXCHG: R600_LDS_1A1D_NORET <0xd, "LDS_WRXCHG", [] >; 515def LDS_CMPST: R600_LDS_1A2D_NORET <0x10, "LDS_CMPST", [] >; 516def LDS_MIN_INT : R600_LDS_1A1D_NORET <0x5, "LDS_MIN_INT", [] >; 517def LDS_MAX_INT : R600_LDS_1A1D_NORET <0x6, "LDS_MAX_INT", [] >; 518def LDS_MIN_UINT : R600_LDS_1A1D_NORET <0x7, "LDS_MIN_UINT", [] >; 519def LDS_MAX_UINT : R600_LDS_1A1D_NORET <0x8, "LDS_MAX_UINT", [] >; 520def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 521 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 522>; 523def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 524 [(truncstorei8_local i32:$src1, i32:$src0)] 525>; 526def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 527 [(truncstorei16_local i32:$src1, i32:$src0)] 528>; 529def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 530 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 531>; 532def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 533 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 534>; 535def LDS_AND_RET : R600_LDS_1A1D_RET <0x29, "LDS_AND", 536 [(set i32:$dst, (atomic_load_and_local i32:$src0, i32:$src1))] 537>; 538def LDS_OR_RET : R600_LDS_1A1D_RET <0x2a, "LDS_OR", 539 [(set i32:$dst, (atomic_load_or_local i32:$src0, i32:$src1))] 540>; 541def LDS_XOR_RET : R600_LDS_1A1D_RET <0x2b, "LDS_XOR", 542 [(set i32:$dst, (atomic_load_xor_local i32:$src0, i32:$src1))] 543>; 544def LDS_MIN_INT_RET : R600_LDS_1A1D_RET <0x25, "LDS_MIN_INT", 545 [(set i32:$dst, (atomic_load_min_local i32:$src0, i32:$src1))] 546>; 547def LDS_MAX_INT_RET : R600_LDS_1A1D_RET <0x26, "LDS_MAX_INT", 548 [(set i32:$dst, (atomic_load_max_local i32:$src0, i32:$src1))] 549>; 550def LDS_MIN_UINT_RET : R600_LDS_1A1D_RET <0x27, "LDS_MIN_UINT", 551 [(set i32:$dst, (atomic_load_umin_local i32:$src0, i32:$src1))] 552>; 553def LDS_MAX_UINT_RET : R600_LDS_1A1D_RET <0x28, "LDS_MAX_UINT", 554 [(set i32:$dst, (atomic_load_umax_local i32:$src0, i32:$src1))] 555>; 556def LDS_WRXCHG_RET : R600_LDS_1A1D_RET <0x2d, "LDS_WRXCHG", 557 [(set i32:$dst, (atomic_swap_local i32:$src0, i32:$src1))] 558>; 559def LDS_CMPST_RET : R600_LDS_1A2D_RET <0x30, "LDS_CMPST", 560 [(set i32:$dst, (atomic_cmp_swap_32_local i32:$src0, i32:$src1, i32:$src2))] 561>; 562def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 563 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 564>; 565def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 566 [(set i32:$dst, (sextloadi8_local i32:$src0))] 567>; 568def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 569 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 570>; 571def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 572 [(set i32:$dst, (sextloadi16_local i32:$src0))] 573>; 574def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 575 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 576>; 577 578// TRUNC is used for the FLT_TO_INT instructions to work around a 579// perceived problem where the rounding modes are applied differently 580// depending on the instruction and the slot they are in. 581// See: 582// https://bugs.freedesktop.org/show_bug.cgi?id=50232 583// Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 584// 585// XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 586// which do not need to be truncated since the fp values are 0.0f or 1.0f. 587// We should look into handling these cases separately. 588def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 589 590def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 591 592// SHA-256 Patterns 593def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 594 595def EG_ExportSwz : ExportSwzInst { 596 let Word1{19-16} = 0; // BURST_COUNT 597 let Word1{20} = 0; // VALID_PIXEL_MODE 598 let Word1{21} = eop; 599 let Word1{29-22} = inst; 600 let Word1{30} = 0; // MARK 601 let Word1{31} = 1; // BARRIER 602} 603defm : ExportPattern<EG_ExportSwz, 83>; 604 605def EG_ExportBuf : ExportBufInst { 606 let Word1{19-16} = 0; // BURST_COUNT 607 let Word1{20} = 0; // VALID_PIXEL_MODE 608 let Word1{21} = eop; 609 let Word1{29-22} = inst; 610 let Word1{30} = 0; // MARK 611 let Word1{31} = 1; // BARRIER 612} 613defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 614 615def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 616 "TEX $COUNT @$ADDR"> { 617 let POP_COUNT = 0; 618} 619def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 620 "VTX $COUNT @$ADDR"> { 621 let POP_COUNT = 0; 622} 623def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 624 "LOOP_START_DX10 @$ADDR"> { 625 let POP_COUNT = 0; 626 let COUNT = 0; 627} 628def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 629 let POP_COUNT = 0; 630 let COUNT = 0; 631} 632def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 633 "LOOP_BREAK @$ADDR"> { 634 let POP_COUNT = 0; 635 let COUNT = 0; 636} 637def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 638 "CONTINUE @$ADDR"> { 639 let POP_COUNT = 0; 640 let COUNT = 0; 641} 642def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 643 "JUMP @$ADDR POP:$POP_COUNT"> { 644 let COUNT = 0; 645} 646def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 647 "PUSH @$ADDR POP:$POP_COUNT"> { 648 let COUNT = 0; 649} 650def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 651 "ELSE @$ADDR POP:$POP_COUNT"> { 652 let COUNT = 0; 653} 654def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 655 let ADDR = 0; 656 let COUNT = 0; 657 let POP_COUNT = 0; 658} 659def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 660 "POP @$ADDR POP:$POP_COUNT"> { 661 let COUNT = 0; 662} 663def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 664 let COUNT = 0; 665 let POP_COUNT = 0; 666 let ADDR = 0; 667 let END_OF_PROGRAM = 1; 668} 669 670} // End Predicates = [isEGorCayman] 671