1 /*-
2 * Copyright 2013 Nathan Whitehorn
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/selinfo.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/eventhandler.h>
39 #include <sys/rman.h>
40 #include <sys/bus_dma.h>
41 #include <sys/bio.h>
42 #include <sys/ioccom.h>
43 #include <sys/uio.h>
44 #include <sys/proc.h>
45 #include <sys/signalvar.h>
46 #include <sys/sysctl.h>
47 #include <sys/endian.h>
48 #include <sys/vmem.h>
49
50 #include <cam/cam.h>
51 #include <cam/cam_ccb.h>
52 #include <cam/cam_debug.h>
53 #include <cam/cam_periph.h>
54 #include <cam/cam_sim.h>
55 #include <cam/cam_xpt_periph.h>
56 #include <cam/cam_xpt_sim.h>
57 #include <cam/scsi/scsi_all.h>
58 #include <cam/scsi/scsi_message.h>
59
60 #include <dev/ofw/openfirm.h>
61 #include <dev/ofw/ofw_bus.h>
62 #include <dev/ofw/ofw_bus_subr.h>
63
64 #include <machine/bus.h>
65 #include <machine/resource.h>
66
67 #include <powerpc/pseries/phyp-hvcall.h>
68
69 struct vscsi_softc;
70
71 /* VSCSI CRQ format from table 260 of PAPR spec 2.4 (page 760) */
72 struct vscsi_crq {
73 uint8_t valid;
74 uint8_t format;
75 uint8_t reserved;
76 uint8_t status;
77 uint16_t timeout;
78 uint16_t iu_length;
79 uint64_t iu_data;
80 };
81
82 struct vscsi_xfer {
83 TAILQ_ENTRY(vscsi_xfer) queue;
84 struct vscsi_softc *sc;
85 union ccb *ccb;
86 bus_dmamap_t dmamap;
87 uint64_t tag;
88
89 vmem_addr_t srp_iu_offset;
90 vmem_size_t srp_iu_size;
91 };
92
93 TAILQ_HEAD(vscsi_xferq, vscsi_xfer);
94
95 struct vscsi_softc {
96 device_t dev;
97 struct cam_devq *devq;
98 struct cam_sim *sim;
99 struct cam_path *path;
100 struct mtx io_lock;
101
102 cell_t unit;
103 int bus_initialized;
104 int bus_logged_in;
105 int max_transactions;
106
107 int irqid;
108 struct resource *irq;
109 void *irq_cookie;
110
111 bus_dma_tag_t crq_tag;
112 struct vscsi_crq *crq_queue;
113 int n_crqs, cur_crq;
114 bus_dmamap_t crq_map;
115 bus_addr_t crq_phys;
116
117 vmem_t *srp_iu_arena;
118 void *srp_iu_queue;
119 bus_addr_t srp_iu_phys;
120
121 bus_dma_tag_t data_tag;
122
123 struct vscsi_xfer loginxp;
124 struct vscsi_xfer *xfer;
125 struct vscsi_xferq active_xferq;
126 struct vscsi_xferq free_xferq;
127 };
128
129 struct srp_login {
130 uint8_t type;
131 uint8_t reserved[7];
132 uint64_t tag;
133 uint64_t max_cmd_length;
134 uint32_t reserved2;
135 uint16_t buffer_formats;
136 uint8_t flags;
137 uint8_t reserved3[5];
138 uint8_t initiator_port_id[16];
139 uint8_t target_port_id[16];
140 } __packed;
141
142 struct srp_login_rsp {
143 uint8_t type;
144 uint8_t reserved[3];
145 uint32_t request_limit_delta;
146 uint8_t tag;
147 uint32_t max_i_to_t_len;
148 uint32_t max_t_to_i_len;
149 uint16_t buffer_formats;
150 uint8_t flags;
151 /* Some reserved bits follow */
152 } __packed;
153
154 struct srp_cmd {
155 uint8_t type;
156 uint8_t flags1;
157 uint8_t reserved[3];
158 uint8_t formats;
159 uint8_t out_buffer_count;
160 uint8_t in_buffer_count;
161 uint64_t tag;
162 uint32_t reserved2;
163 uint64_t lun;
164 uint8_t reserved3[3];
165 uint8_t additional_cdb;
166 uint8_t cdb[16];
167 uint8_t data_payload[0];
168 } __packed;
169
170 struct srp_rsp {
171 uint8_t type;
172 uint8_t reserved[3];
173 uint32_t request_limit_delta;
174 uint64_t tag;
175 uint16_t reserved2;
176 uint8_t flags;
177 uint8_t status;
178 uint32_t data_out_resid;
179 uint32_t data_in_resid;
180 uint32_t sense_data_len;
181 uint32_t response_data_len;
182 uint8_t data_payload[0];
183 } __packed;
184
185 struct srp_tsk_mgmt {
186 uint8_t type;
187 uint8_t reserved[7];
188 uint64_t tag;
189 uint32_t reserved2;
190 uint64_t lun;
191 uint8_t reserved3[2];
192 uint8_t function;
193 uint8_t reserved4;
194 uint64_t manage_tag;
195 uint64_t reserved5;
196 } __packed;
197
198 /* Message code type */
199 #define SRP_LOGIN_REQ 0x00
200 #define SRP_TSK_MGMT 0x01
201 #define SRP_CMD 0x02
202 #define SRP_I_LOGOUT 0x03
203
204 #define SRP_LOGIN_RSP 0xC0
205 #define SRP_RSP 0xC1
206 #define SRP_LOGIN_REJ 0xC2
207
208 #define SRP_T_LOGOUT 0x80
209 #define SRP_CRED_REQ 0x81
210 #define SRP_AER_REQ 0x82
211
212 #define SRP_CRED_RSP 0x41
213 #define SRP_AER_RSP 0x41
214
215 /* Flags for srp_rsp flags field */
216 #define SRP_RSPVALID 0x01
217 #define SRP_SNSVALID 0x02
218 #define SRP_DOOVER 0x04
219 #define SRP_DOUNDER 0x08
220 #define SRP_DIOVER 0x10
221 #define SRP_DIUNDER 0x20
222
223 #define MAD_SUCESS 0x00
224 #define MAD_NOT_SUPPORTED 0xf1
225 #define MAD_FAILED 0xf7
226
227 #define MAD_EMPTY_IU 0x01
228 #define MAD_ERROR_LOGGING_REQUEST 0x02
229 #define MAD_ADAPTER_INFO_REQUEST 0x03
230 #define MAD_CAPABILITIES_EXCHANGE 0x05
231 #define MAD_PHYS_ADAP_INFO_REQUEST 0x06
232 #define MAD_TAPE_PASSTHROUGH_REQUEST 0x07
233 #define MAD_ENABLE_FAST_FAIL 0x08
234
235 static int vscsi_probe(device_t);
236 static int vscsi_attach(device_t);
237 static int vscsi_detach(device_t);
238 static void vscsi_cam_action(struct cam_sim *, union ccb *);
239 static void vscsi_cam_poll(struct cam_sim *);
240 static void vscsi_intr(void *arg);
241 static void vscsi_check_response_queue(struct vscsi_softc *sc);
242 static void vscsi_setup_bus(struct vscsi_softc *sc);
243
244 static void vscsi_srp_login(struct vscsi_softc *sc);
245 static void vscsi_crq_load_cb(void *, bus_dma_segment_t *, int, int);
246 static void vscsi_scsi_command(void *xxp, bus_dma_segment_t *segs,
247 int nsegs, int err);
248 static void vscsi_task_management(struct vscsi_softc *sc, union ccb *ccb);
249 static void vscsi_srp_response(struct vscsi_xfer *, struct vscsi_crq *);
250
251 static devclass_t vscsi_devclass;
252 static device_method_t vscsi_methods[] = {
253 DEVMETHOD(device_probe, vscsi_probe),
254 DEVMETHOD(device_attach, vscsi_attach),
255 DEVMETHOD(device_detach, vscsi_detach),
256
257 DEVMETHOD_END
258 };
259 static driver_t vscsi_driver = {
260 "vscsi",
261 vscsi_methods,
262 sizeof(struct vscsi_softc)
263 };
264 DRIVER_MODULE(vscsi, vdevice, vscsi_driver, vscsi_devclass, 0, 0);
265 MALLOC_DEFINE(M_VSCSI, "vscsi", "CAM device queue for VSCSI");
266
267 static int
vscsi_probe(device_t dev)268 vscsi_probe(device_t dev)
269 {
270
271 if (!ofw_bus_is_compatible(dev, "IBM,v-scsi"))
272 return (ENXIO);
273
274 device_set_desc(dev, "POWER Hypervisor Virtual SCSI Bus");
275 return (0);
276 }
277
278 static int
vscsi_attach(device_t dev)279 vscsi_attach(device_t dev)
280 {
281 struct vscsi_softc *sc;
282 struct vscsi_xfer *xp;
283 int error, i;
284
285 sc = device_get_softc(dev);
286 if (sc == NULL)
287 return (EINVAL);
288
289 sc->dev = dev;
290 mtx_init(&sc->io_lock, "vscsi", NULL, MTX_DEF);
291
292 /* Get properties */
293 OF_getprop(ofw_bus_get_node(dev), "reg", &sc->unit, sizeof(sc->unit));
294
295 /* Setup interrupt */
296 sc->irqid = 0;
297 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
298 RF_ACTIVE);
299
300 if (!sc->irq) {
301 device_printf(dev, "Could not allocate IRQ\n");
302 mtx_destroy(&sc->io_lock);
303 return (ENXIO);
304 }
305
306 bus_setup_intr(dev, sc->irq, INTR_TYPE_CAM | INTR_MPSAFE |
307 INTR_ENTROPY, NULL, vscsi_intr, sc, &sc->irq_cookie);
308
309 /* Data DMA */
310 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
311 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
312 256, BUS_SPACE_MAXSIZE_32BIT, 0, busdma_lock_mutex, &sc->io_lock,
313 &sc->data_tag);
314
315 TAILQ_INIT(&sc->active_xferq);
316 TAILQ_INIT(&sc->free_xferq);
317
318 /* First XFER for login data */
319 sc->loginxp.sc = sc;
320 bus_dmamap_create(sc->data_tag, 0, &sc->loginxp.dmamap);
321 TAILQ_INSERT_TAIL(&sc->free_xferq, &sc->loginxp, queue);
322
323 /* CRQ area */
324 error = bus_dma_tag_create(bus_get_dma_tag(dev), PAGE_SIZE, 0,
325 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 8*PAGE_SIZE,
326 1, BUS_SPACE_MAXSIZE, 0, NULL, NULL, &sc->crq_tag);
327 error = bus_dmamem_alloc(sc->crq_tag, (void **)&sc->crq_queue,
328 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->crq_map);
329 sc->crq_phys = 0;
330 sc->n_crqs = 0;
331 error = bus_dmamap_load(sc->crq_tag, sc->crq_map, sc->crq_queue,
332 8*PAGE_SIZE, vscsi_crq_load_cb, sc, 0);
333
334 mtx_lock(&sc->io_lock);
335 vscsi_setup_bus(sc);
336 sc->xfer = malloc(sizeof(sc->xfer[0])*sc->max_transactions, M_VSCSI,
337 M_NOWAIT);
338 for (i = 0; i < sc->max_transactions; i++) {
339 xp = &sc->xfer[i];
340 xp->sc = sc;
341
342 error = bus_dmamap_create(sc->data_tag, 0, &xp->dmamap);
343 if (error) {
344 device_printf(dev, "Could not create DMA map (%d)\n",
345 error);
346 break;
347 }
348
349 TAILQ_INSERT_TAIL(&sc->free_xferq, xp, queue);
350 }
351 mtx_unlock(&sc->io_lock);
352
353 /* Allocate CAM bits */
354 if ((sc->devq = cam_simq_alloc(sc->max_transactions)) == NULL)
355 return (ENOMEM);
356
357 sc->sim = cam_sim_alloc(vscsi_cam_action, vscsi_cam_poll, "vscsi", sc,
358 device_get_unit(dev), &sc->io_lock,
359 sc->max_transactions, sc->max_transactions,
360 sc->devq);
361 if (sc->sim == NULL) {
362 cam_simq_free(sc->devq);
363 sc->devq = NULL;
364 device_printf(dev, "CAM SIM attach failed\n");
365 return (EINVAL);
366 }
367
368
369 mtx_lock(&sc->io_lock);
370 if (xpt_bus_register(sc->sim, dev, 0) != 0) {
371 device_printf(dev, "XPT bus registration failed\n");
372 cam_sim_free(sc->sim, FALSE);
373 sc->sim = NULL;
374 cam_simq_free(sc->devq);
375 sc->devq = NULL;
376 mtx_unlock(&sc->io_lock);
377 return (EINVAL);
378 }
379 mtx_unlock(&sc->io_lock);
380
381 return (0);
382 }
383
384 static int
vscsi_detach(device_t dev)385 vscsi_detach(device_t dev)
386 {
387 struct vscsi_softc *sc;
388
389 sc = device_get_softc(dev);
390 if (sc == NULL)
391 return (EINVAL);
392
393 if (sc->sim != NULL) {
394 mtx_lock(&sc->io_lock);
395 xpt_bus_deregister(cam_sim_path(sc->sim));
396 cam_sim_free(sc->sim, FALSE);
397 sc->sim = NULL;
398 mtx_unlock(&sc->io_lock);
399 }
400
401 if (sc->devq != NULL) {
402 cam_simq_free(sc->devq);
403 sc->devq = NULL;
404 }
405
406 mtx_destroy(&sc->io_lock);
407
408 return (0);
409 }
410
411 static void
vscsi_cam_action(struct cam_sim * sim,union ccb * ccb)412 vscsi_cam_action(struct cam_sim *sim, union ccb *ccb)
413 {
414 struct vscsi_softc *sc = cam_sim_softc(sim);
415
416 mtx_assert(&sc->io_lock, MA_OWNED);
417
418 switch (ccb->ccb_h.func_code) {
419 case XPT_PATH_INQ:
420 {
421 struct ccb_pathinq *cpi = &ccb->cpi;
422
423 cpi->version_num = 1;
424 cpi->hba_inquiry = PI_TAG_ABLE;
425 cpi->hba_misc = PIM_EXTLUNS;
426 cpi->target_sprt = 0;
427 cpi->hba_eng_cnt = 0;
428 cpi->max_target = 0;
429 cpi->max_lun = ~(lun_id_t)(0);
430 cpi->initiator_id = ~0;
431 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
432 strncpy(cpi->hba_vid, "IBM", HBA_IDLEN);
433 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
434 cpi->unit_number = cam_sim_unit(sim);
435 cpi->bus_id = cam_sim_bus(sim);
436 cpi->base_transfer_speed = 150000;
437 cpi->transport = XPORT_SRP;
438 cpi->transport_version = 0;
439 cpi->protocol = PROTO_SCSI;
440 cpi->protocol_version = SCSI_REV_SPC4;
441 cpi->ccb_h.status = CAM_REQ_CMP;
442 break;
443 }
444 case XPT_RESET_BUS:
445 ccb->ccb_h.status = CAM_REQ_CMP;
446 break;
447 case XPT_RESET_DEV:
448 ccb->ccb_h.status = CAM_REQ_INPROG;
449 vscsi_task_management(sc, ccb);
450 return;
451 case XPT_GET_TRAN_SETTINGS:
452 ccb->cts.protocol = PROTO_SCSI;
453 ccb->cts.protocol_version = SCSI_REV_SPC4;
454 ccb->cts.transport = XPORT_SRP;
455 ccb->cts.transport_version = 0;
456 ccb->cts.proto_specific.valid = 0;
457 ccb->cts.xport_specific.valid = 0;
458 ccb->ccb_h.status = CAM_REQ_CMP;
459 break;
460 case XPT_SET_TRAN_SETTINGS:
461 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
462 break;
463 case XPT_SCSI_IO:
464 {
465 struct vscsi_xfer *xp;
466
467 ccb->ccb_h.status = CAM_REQ_INPROG;
468
469 xp = TAILQ_FIRST(&sc->free_xferq);
470 if (xp == NULL)
471 panic("SCSI queue flooded");
472 xp->ccb = ccb;
473 TAILQ_REMOVE(&sc->free_xferq, xp, queue);
474 TAILQ_INSERT_TAIL(&sc->active_xferq, xp, queue);
475 bus_dmamap_load_ccb(sc->data_tag, xp->dmamap,
476 ccb, vscsi_scsi_command, xp, 0);
477
478 return;
479 }
480 default:
481 ccb->ccb_h.status = CAM_REQ_INVALID;
482 break;
483 }
484
485 xpt_done(ccb);
486 return;
487 }
488
489 static void
vscsi_srp_login(struct vscsi_softc * sc)490 vscsi_srp_login(struct vscsi_softc *sc)
491 {
492 struct vscsi_xfer *xp;
493 struct srp_login *login;
494 struct vscsi_crq crq;
495 int err;
496
497 mtx_assert(&sc->io_lock, MA_OWNED);
498
499 xp = TAILQ_FIRST(&sc->free_xferq);
500 if (xp == NULL)
501 panic("SCSI queue flooded");
502 xp->ccb = NULL;
503 TAILQ_REMOVE(&sc->free_xferq, xp, queue);
504 TAILQ_INSERT_TAIL(&sc->active_xferq, xp, queue);
505
506 /* Set up command */
507 xp->srp_iu_size = crq.iu_length = 64;
508 err = vmem_alloc(xp->sc->srp_iu_arena, xp->srp_iu_size,
509 M_BESTFIT | M_NOWAIT, &xp->srp_iu_offset);
510 if (err)
511 panic("Error during VMEM allocation (%d)", err);
512
513 login = (struct srp_login *)((uint8_t *)xp->sc->srp_iu_queue +
514 (uintptr_t)xp->srp_iu_offset);
515 bzero(login, xp->srp_iu_size);
516 login->type = SRP_LOGIN_REQ;
517 login->tag = (uint64_t)(xp);
518 login->max_cmd_length = htobe64(256);
519 login->buffer_formats = htobe16(0x1 | 0x2); /* Direct and indirect */
520 login->flags = 0;
521
522 /* Create CRQ entry */
523 crq.valid = 0x80;
524 crq.format = 0x01;
525 crq.iu_data = xp->sc->srp_iu_phys + xp->srp_iu_offset;
526 bus_dmamap_sync(sc->crq_tag, sc->crq_map, BUS_DMASYNC_PREWRITE);
527
528 err = phyp_hcall(H_SEND_CRQ, xp->sc->unit, ((uint64_t *)(&crq))[0],
529 ((uint64_t *)(&crq))[1]);
530 if (err != 0)
531 panic("CRQ send failure (%d)", err);
532 }
533
534 static void
vscsi_task_management(struct vscsi_softc * sc,union ccb * ccb)535 vscsi_task_management(struct vscsi_softc *sc, union ccb *ccb)
536 {
537 struct srp_tsk_mgmt *cmd;
538 struct vscsi_xfer *xp;
539 struct vscsi_crq crq;
540 int err;
541
542 mtx_assert(&sc->io_lock, MA_OWNED);
543
544 xp = TAILQ_FIRST(&sc->free_xferq);
545 if (xp == NULL)
546 panic("SCSI queue flooded");
547 xp->ccb = ccb;
548 TAILQ_REMOVE(&sc->free_xferq, xp, queue);
549 TAILQ_INSERT_TAIL(&sc->active_xferq, xp, queue);
550
551 xp->srp_iu_size = crq.iu_length = sizeof(*cmd);
552 err = vmem_alloc(xp->sc->srp_iu_arena, xp->srp_iu_size,
553 M_BESTFIT | M_NOWAIT, &xp->srp_iu_offset);
554 if (err)
555 panic("Error during VMEM allocation (%d)", err);
556
557 cmd = (struct srp_tsk_mgmt *)((uint8_t *)xp->sc->srp_iu_queue +
558 (uintptr_t)xp->srp_iu_offset);
559 bzero(cmd, xp->srp_iu_size);
560 cmd->type = SRP_TSK_MGMT;
561 cmd->tag = (uint64_t)xp;
562 cmd->lun = htobe64(CAM_EXTLUN_BYTE_SWIZZLE(ccb->ccb_h.target_lun));
563
564 switch (ccb->ccb_h.func_code) {
565 case XPT_RESET_DEV:
566 cmd->function = 0x08;
567 break;
568 default:
569 panic("Unimplemented code %d", ccb->ccb_h.func_code);
570 break;
571 }
572
573 bus_dmamap_sync(xp->sc->crq_tag, xp->sc->crq_map, BUS_DMASYNC_PREWRITE);
574
575 /* Create CRQ entry */
576 crq.valid = 0x80;
577 crq.format = 0x01;
578 crq.iu_data = xp->sc->srp_iu_phys + xp->srp_iu_offset;
579
580 err = phyp_hcall(H_SEND_CRQ, xp->sc->unit, ((uint64_t *)(&crq))[0],
581 ((uint64_t *)(&crq))[1]);
582 if (err != 0)
583 panic("CRQ send failure (%d)", err);
584 }
585
586 static void
vscsi_scsi_command(void * xxp,bus_dma_segment_t * segs,int nsegs,int err)587 vscsi_scsi_command(void *xxp, bus_dma_segment_t *segs, int nsegs, int err)
588 {
589 struct vscsi_xfer *xp = xxp;
590 uint8_t *cdb;
591 union ccb *ccb = xp->ccb;
592 struct srp_cmd *cmd;
593 uint64_t chunk_addr;
594 uint32_t chunk_size;
595 int desc_start, i;
596 struct vscsi_crq crq;
597
598 KASSERT(err == 0, ("DMA error %d\n", err));
599
600 mtx_assert(&xp->sc->io_lock, MA_OWNED);
601
602 cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
603 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
604
605 /* Command format from Table 20, page 37 of SRP spec */
606 crq.iu_length = 48 + ((nsegs > 1) ? 20 : 16) +
607 ((ccb->csio.cdb_len > 16) ? (ccb->csio.cdb_len - 16) : 0);
608 xp->srp_iu_size = crq.iu_length;
609 if (nsegs > 1)
610 xp->srp_iu_size += nsegs*16;
611 xp->srp_iu_size = roundup(xp->srp_iu_size, 16);
612 err = vmem_alloc(xp->sc->srp_iu_arena, xp->srp_iu_size,
613 M_BESTFIT | M_NOWAIT, &xp->srp_iu_offset);
614 if (err)
615 panic("Error during VMEM allocation (%d)", err);
616
617 cmd = (struct srp_cmd *)((uint8_t *)xp->sc->srp_iu_queue +
618 (uintptr_t)xp->srp_iu_offset);
619 bzero(cmd, xp->srp_iu_size);
620 cmd->type = SRP_CMD;
621 if (ccb->csio.cdb_len > 16)
622 cmd->additional_cdb = (ccb->csio.cdb_len - 16) << 2;
623 memcpy(cmd->cdb, cdb, ccb->csio.cdb_len);
624
625 cmd->tag = (uint64_t)(xp); /* Let the responder find this again */
626 cmd->lun = htobe64(CAM_EXTLUN_BYTE_SWIZZLE(ccb->ccb_h.target_lun));
627
628 if (nsegs > 1) {
629 /* Use indirect descriptors */
630 switch (ccb->ccb_h.flags & CAM_DIR_MASK) {
631 case CAM_DIR_OUT:
632 cmd->formats = (2 << 4);
633 break;
634 case CAM_DIR_IN:
635 cmd->formats = 2;
636 break;
637 default:
638 panic("Does not support bidirectional commands (%d)",
639 ccb->ccb_h.flags & CAM_DIR_MASK);
640 break;
641 }
642
643 desc_start = ((ccb->csio.cdb_len > 16) ?
644 ccb->csio.cdb_len - 16 : 0);
645 chunk_addr = xp->sc->srp_iu_phys + xp->srp_iu_offset + 20 +
646 desc_start + sizeof(*cmd);
647 chunk_size = 16*nsegs;
648 memcpy(&cmd->data_payload[desc_start], &chunk_addr, 8);
649 memcpy(&cmd->data_payload[desc_start+12], &chunk_size, 4);
650 chunk_size = 0;
651 for (i = 0; i < nsegs; i++)
652 chunk_size += segs[i].ds_len;
653 memcpy(&cmd->data_payload[desc_start+16], &chunk_size, 4);
654 desc_start += 20;
655 for (i = 0; i < nsegs; i++) {
656 chunk_addr = segs[i].ds_addr;
657 chunk_size = segs[i].ds_len;
658
659 memcpy(&cmd->data_payload[desc_start + 16*i],
660 &chunk_addr, 8);
661 /* Set handle tag to 0 */
662 memcpy(&cmd->data_payload[desc_start + 16*i + 12],
663 &chunk_size, 4);
664 }
665 } else if (nsegs == 1) {
666 switch (ccb->ccb_h.flags & CAM_DIR_MASK) {
667 case CAM_DIR_OUT:
668 cmd->formats = (1 << 4);
669 break;
670 case CAM_DIR_IN:
671 cmd->formats = 1;
672 break;
673 default:
674 panic("Does not support bidirectional commands (%d)",
675 ccb->ccb_h.flags & CAM_DIR_MASK);
676 break;
677 }
678
679 /*
680 * Memory descriptor:
681 * 8 byte address
682 * 4 byte handle
683 * 4 byte length
684 */
685
686 chunk_addr = segs[0].ds_addr;
687 chunk_size = segs[0].ds_len;
688 desc_start = ((ccb->csio.cdb_len > 16) ?
689 ccb->csio.cdb_len - 16 : 0);
690
691 memcpy(&cmd->data_payload[desc_start], &chunk_addr, 8);
692 /* Set handle tag to 0 */
693 memcpy(&cmd->data_payload[desc_start+12], &chunk_size, 4);
694 KASSERT(xp->srp_iu_size >= 48 + ((ccb->csio.cdb_len > 16) ?
695 ccb->csio.cdb_len : 16), ("SRP IU command length"));
696 } else {
697 cmd->formats = 0;
698 }
699 bus_dmamap_sync(xp->sc->crq_tag, xp->sc->crq_map, BUS_DMASYNC_PREWRITE);
700
701 /* Create CRQ entry */
702 crq.valid = 0x80;
703 crq.format = 0x01;
704 crq.iu_data = xp->sc->srp_iu_phys + xp->srp_iu_offset;
705
706 err = phyp_hcall(H_SEND_CRQ, xp->sc->unit, ((uint64_t *)(&crq))[0],
707 ((uint64_t *)(&crq))[1]);
708 if (err != 0)
709 panic("CRQ send failure (%d)", err);
710 }
711
712 static void
vscsi_crq_load_cb(void * xsc,bus_dma_segment_t * segs,int nsegs,int err)713 vscsi_crq_load_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int err)
714 {
715 struct vscsi_softc *sc = xsc;
716
717 sc->crq_phys = segs[0].ds_addr;
718 sc->n_crqs = PAGE_SIZE/sizeof(struct vscsi_crq);
719
720 sc->srp_iu_queue = (uint8_t *)(sc->crq_queue);
721 sc->srp_iu_phys = segs[0].ds_addr;
722 sc->srp_iu_arena = vmem_create("VSCSI SRP IU", PAGE_SIZE,
723 segs[0].ds_len - PAGE_SIZE, 16, 0, M_BESTFIT | M_NOWAIT);
724 }
725
726 static void
vscsi_setup_bus(struct vscsi_softc * sc)727 vscsi_setup_bus(struct vscsi_softc *sc)
728 {
729 struct vscsi_crq crq;
730 struct vscsi_xfer *xp;
731 int error;
732
733 struct {
734 uint32_t type;
735 uint16_t status;
736 uint16_t length;
737 uint64_t tag;
738 uint64_t buffer;
739 struct {
740 char srp_version[8];
741 char partition_name[96];
742 uint32_t partition_number;
743 uint32_t mad_version;
744 uint32_t os_type;
745 uint32_t port_max_txu[8];
746 } payload;
747 } mad_adapter_info;
748
749 bzero(&crq, sizeof(crq));
750
751 /* Init message */
752 crq.valid = 0xc0;
753 crq.format = 0x01;
754
755 do {
756 error = phyp_hcall(H_FREE_CRQ, sc->unit);
757 } while (error == H_BUSY);
758
759 /* See initialization sequence page 757 */
760 bzero(sc->crq_queue, sc->n_crqs*sizeof(sc->crq_queue[0]));
761 sc->cur_crq = 0;
762 sc->bus_initialized = 0;
763 sc->bus_logged_in = 0;
764 bus_dmamap_sync(sc->crq_tag, sc->crq_map, BUS_DMASYNC_PREWRITE);
765 error = phyp_hcall(H_REG_CRQ, sc->unit, sc->crq_phys,
766 sc->n_crqs*sizeof(sc->crq_queue[0]));
767 KASSERT(error == 0, ("CRQ registration success"));
768
769 error = phyp_hcall(H_SEND_CRQ, sc->unit, ((uint64_t *)(&crq))[0],
770 ((uint64_t *)(&crq))[1]);
771 if (error != 0)
772 panic("CRQ setup failure (%d)", error);
773
774 while (sc->bus_initialized == 0)
775 vscsi_check_response_queue(sc);
776
777 /* Send MAD adapter info */
778 mad_adapter_info.type = MAD_ADAPTER_INFO_REQUEST;
779 mad_adapter_info.status = 0;
780 mad_adapter_info.length = sizeof(mad_adapter_info.payload);
781
782 strcpy(mad_adapter_info.payload.srp_version, "16.a");
783 strcpy(mad_adapter_info.payload.partition_name, "UNKNOWN");
784 mad_adapter_info.payload.partition_number = -1;
785 mad_adapter_info.payload.mad_version = 1;
786 mad_adapter_info.payload.os_type = 2; /* Claim we are Linux */
787 mad_adapter_info.payload.port_max_txu[0] = 0;
788 /* If this fails, we get the defaults above */
789 OF_getprop(OF_finddevice("/"), "ibm,partition-name",
790 mad_adapter_info.payload.partition_name,
791 sizeof(mad_adapter_info.payload.partition_name));
792 OF_getprop(OF_finddevice("/"), "ibm,partition-no",
793 &mad_adapter_info.payload.partition_number,
794 sizeof(mad_adapter_info.payload.partition_number));
795
796 xp = TAILQ_FIRST(&sc->free_xferq);
797 xp->ccb = NULL;
798 TAILQ_REMOVE(&sc->free_xferq, xp, queue);
799 TAILQ_INSERT_TAIL(&sc->active_xferq, xp, queue);
800 xp->srp_iu_size = crq.iu_length = sizeof(mad_adapter_info);
801 vmem_alloc(xp->sc->srp_iu_arena, xp->srp_iu_size,
802 M_BESTFIT | M_NOWAIT, &xp->srp_iu_offset);
803 mad_adapter_info.buffer = xp->sc->srp_iu_phys + xp->srp_iu_offset + 24;
804 mad_adapter_info.tag = (uint64_t)xp;
805 memcpy((uint8_t *)xp->sc->srp_iu_queue + (uintptr_t)xp->srp_iu_offset,
806 &mad_adapter_info, sizeof(mad_adapter_info));
807 crq.valid = 0x80;
808 crq.format = 0x02;
809 crq.iu_data = xp->sc->srp_iu_phys + xp->srp_iu_offset;
810 bus_dmamap_sync(sc->crq_tag, sc->crq_map, BUS_DMASYNC_PREWRITE);
811 phyp_hcall(H_SEND_CRQ, xp->sc->unit, ((uint64_t *)(&crq))[0],
812 ((uint64_t *)(&crq))[1]);
813
814 while (TAILQ_EMPTY(&sc->free_xferq))
815 vscsi_check_response_queue(sc);
816
817 /* Send SRP login */
818 vscsi_srp_login(sc);
819 while (sc->bus_logged_in == 0)
820 vscsi_check_response_queue(sc);
821
822 error = phyp_hcall(H_VIO_SIGNAL, sc->unit, 1); /* Enable interrupts */
823 }
824
825
826 static void
vscsi_intr(void * xsc)827 vscsi_intr(void *xsc)
828 {
829 struct vscsi_softc *sc = xsc;
830
831 mtx_lock(&sc->io_lock);
832 vscsi_check_response_queue(sc);
833 mtx_unlock(&sc->io_lock);
834 }
835
836 static void
vscsi_srp_response(struct vscsi_xfer * xp,struct vscsi_crq * crq)837 vscsi_srp_response(struct vscsi_xfer *xp, struct vscsi_crq *crq)
838 {
839 union ccb *ccb = xp->ccb;
840 struct vscsi_softc *sc = xp->sc;
841 struct srp_rsp *rsp;
842 uint32_t sense_len;
843
844 /* SRP response packet in original request */
845 rsp = (struct srp_rsp *)((uint8_t *)sc->srp_iu_queue +
846 (uintptr_t)xp->srp_iu_offset);
847 ccb->csio.scsi_status = rsp->status;
848 if (ccb->csio.scsi_status == SCSI_STATUS_OK)
849 ccb->ccb_h.status = CAM_REQ_CMP;
850 else
851 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
852 #ifdef NOTYET
853 /* Collect fast fail codes */
854 if (crq->status != 0)
855 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
856 #endif
857
858 if (ccb->ccb_h.status != CAM_REQ_CMP) {
859 ccb->ccb_h.status |= CAM_DEV_QFRZN;
860 xpt_freeze_devq(ccb->ccb_h.path, /*count*/ 1);
861 }
862
863 if (!(rsp->flags & SRP_RSPVALID))
864 rsp->response_data_len = 0;
865 if (!(rsp->flags & SRP_SNSVALID))
866 rsp->sense_data_len = 0;
867 if (!(rsp->flags & (SRP_DOOVER | SRP_DOUNDER)))
868 rsp->data_out_resid = 0;
869 if (!(rsp->flags & (SRP_DIOVER | SRP_DIUNDER)))
870 rsp->data_in_resid = 0;
871
872 if (rsp->flags & SRP_SNSVALID) {
873 bzero(&ccb->csio.sense_data, sizeof(struct scsi_sense_data));
874 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
875 sense_len = min(be32toh(rsp->sense_data_len),
876 ccb->csio.sense_len);
877 memcpy(&ccb->csio.sense_data,
878 &rsp->data_payload[be32toh(rsp->response_data_len)],
879 sense_len);
880 ccb->csio.sense_resid = ccb->csio.sense_len -
881 be32toh(rsp->sense_data_len);
882 }
883
884 switch (ccb->ccb_h.flags & CAM_DIR_MASK) {
885 case CAM_DIR_OUT:
886 ccb->csio.resid = rsp->data_out_resid;
887 break;
888 case CAM_DIR_IN:
889 ccb->csio.resid = rsp->data_in_resid;
890 break;
891 }
892
893 bus_dmamap_sync(sc->data_tag, xp->dmamap, BUS_DMASYNC_POSTREAD);
894 bus_dmamap_unload(sc->data_tag, xp->dmamap);
895 xpt_done(ccb);
896 xp->ccb = NULL;
897 }
898
899 static void
vscsi_login_response(struct vscsi_xfer * xp,struct vscsi_crq * crq)900 vscsi_login_response(struct vscsi_xfer *xp, struct vscsi_crq *crq)
901 {
902 struct vscsi_softc *sc = xp->sc;
903 struct srp_login_rsp *rsp;
904
905 /* SRP response packet in original request */
906 rsp = (struct srp_login_rsp *)((uint8_t *)sc->srp_iu_queue +
907 (uintptr_t)xp->srp_iu_offset);
908 KASSERT(be16toh(rsp->buffer_formats) & 0x3, ("Both direct and indirect "
909 "buffers supported"));
910
911 sc->max_transactions = be32toh(rsp->request_limit_delta);
912 device_printf(sc->dev, "Queue depth %d commands\n",
913 sc->max_transactions);
914 sc->bus_logged_in = 1;
915 }
916
917 static void
vscsi_cam_poll(struct cam_sim * sim)918 vscsi_cam_poll(struct cam_sim *sim)
919 {
920 struct vscsi_softc *sc = cam_sim_softc(sim);
921
922 vscsi_check_response_queue(sc);
923 }
924
925 static void
vscsi_check_response_queue(struct vscsi_softc * sc)926 vscsi_check_response_queue(struct vscsi_softc *sc)
927 {
928 struct vscsi_crq *crq;
929 struct vscsi_xfer *xp;
930 int code;
931
932 mtx_assert(&sc->io_lock, MA_OWNED);
933
934 phyp_hcall(H_VIO_SIGNAL, sc->unit, 0);
935 bus_dmamap_sync(sc->crq_tag, sc->crq_map, BUS_DMASYNC_POSTREAD);
936
937 while (sc->crq_queue[sc->cur_crq].valid != 0) {
938 crq = &sc->crq_queue[sc->cur_crq];
939
940 switch (crq->valid) {
941 case 0xc0:
942 if (crq->format == 0x02)
943 sc->bus_initialized = 1;
944 break;
945 case 0x80:
946 /* IU data is set to tag pointer (the XP) */
947 xp = (struct vscsi_xfer *)crq->iu_data;
948
949 switch (crq->format) {
950 case 0x01:
951 code = *((uint8_t *)sc->srp_iu_queue +
952 (uintptr_t)xp->srp_iu_offset);
953 switch (code) {
954 case SRP_RSP:
955 vscsi_srp_response(xp, crq);
956 break;
957 case SRP_LOGIN_RSP:
958 vscsi_login_response(xp, crq);
959 break;
960 default:
961 device_printf(sc->dev, "Unknown SRP "
962 "response code %d\n", code);
963 break;
964 }
965 break;
966 case 0x02:
967 /* Ignore management datagrams */
968 break;
969 default:
970 panic("Unknown CRQ format %d\n", crq->format);
971 break;
972 }
973 vmem_free(sc->srp_iu_arena, xp->srp_iu_offset,
974 xp->srp_iu_size);
975 TAILQ_REMOVE(&sc->active_xferq, xp, queue);
976 TAILQ_INSERT_TAIL(&sc->free_xferq, xp, queue);
977 break;
978 default:
979 device_printf(sc->dev,
980 "Unknown CRQ message type %d\n", crq->valid);
981 break;
982 }
983
984 crq->valid = 0;
985 sc->cur_crq = (sc->cur_crq + 1) % sc->n_crqs;
986 };
987
988 bus_dmamap_sync(sc->crq_tag, sc->crq_map, BUS_DMASYNC_PREWRITE);
989 phyp_hcall(H_VIO_SIGNAL, sc->unit, 1);
990 }
991
992