1 /*- 2 * Copyright (c) 2009, Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef __IF_ARGEVAR_H__ 31 #define __IF_ARGEVAR_H__ 32 33 #define ARGE_NPHY 32 34 #define ARGE_TX_RING_COUNT 128 35 #define ARGE_RX_RING_COUNT 128 36 #define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc) 37 #define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc) 38 #define ARGE_MAXFRAGS 8 39 #define ARGE_RING_ALIGN sizeof(struct arge_desc) 40 #define ARGE_RX_ALIGN sizeof(uint32_t) 41 #define ARGE_MAXFRAGS 8 42 #define ARGE_TX_RING_ADDR(sc, i) \ 43 ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i)) 44 #define ARGE_RX_RING_ADDR(sc, i) \ 45 ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i)) 46 #define ARGE_INC(x,y) (x) = (((x) + 1) % y) 47 48 49 #define ARGE_MII_TIMEOUT 1000 50 51 #define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx) 52 #define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx) 53 #define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED) 54 55 /* 56 * register space access macros 57 */ 58 #define ARGE_WRITE(sc, reg, val) do { \ 59 bus_write_4(sc->arge_res, (reg), (val)); \ 60 } while (0) 61 62 #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg)) 63 64 #define ARGE_SET_BITS(sc, reg, bits) \ 65 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits)) 66 67 #define ARGE_CLEAR_BITS(sc, reg, bits) \ 68 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits)) 69 70 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \ 71 ARGE_WRITE((_sc), (_reg), (_val)) 72 #define ARGE_MDIO_READ(_sc, _reg) \ 73 ARGE_READ((_sc), (_reg)) 74 75 #define ARGE_DESC_EMPTY (1U << 31) 76 #define ARGE_DESC_MORE (1 << 24) 77 #define ARGE_DESC_SIZE_MASK ((1 << 12) - 1) 78 #define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK) 79 struct arge_desc { 80 uint32_t packet_addr; 81 uint32_t packet_ctrl; 82 uint32_t next_desc; 83 uint32_t padding; 84 }; 85 86 struct arge_txdesc { 87 struct mbuf *tx_m; 88 bus_dmamap_t tx_dmamap; 89 }; 90 91 struct arge_rxdesc { 92 struct mbuf *rx_m; 93 bus_dmamap_t rx_dmamap; 94 struct arge_desc *desc; 95 }; 96 97 struct arge_chain_data { 98 bus_dma_tag_t arge_parent_tag; 99 bus_dma_tag_t arge_tx_tag; 100 struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT]; 101 bus_dma_tag_t arge_rx_tag; 102 struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT]; 103 bus_dma_tag_t arge_tx_ring_tag; 104 bus_dma_tag_t arge_rx_ring_tag; 105 bus_dmamap_t arge_tx_ring_map; 106 bus_dmamap_t arge_rx_ring_map; 107 bus_dmamap_t arge_rx_sparemap; 108 int arge_tx_prod; 109 int arge_tx_cons; 110 int arge_tx_cnt; 111 int arge_rx_cons; 112 }; 113 114 struct arge_ring_data { 115 struct arge_desc *arge_rx_ring; 116 struct arge_desc *arge_tx_ring; 117 bus_addr_t arge_rx_ring_paddr; 118 bus_addr_t arge_tx_ring_paddr; 119 }; 120 121 /* 122 * Allow PLL values to be overridden. 123 */ 124 struct arge_pll_data { 125 uint32_t pll_10; 126 uint32_t pll_100; 127 uint32_t pll_1000; 128 }; 129 130 struct arge_softc { 131 struct ifnet *arge_ifp; /* interface info */ 132 device_t arge_dev; 133 struct ifmedia arge_ifmedia; 134 /* 135 * Media & duples settings for multiPHY MAC 136 */ 137 uint32_t arge_media_type; 138 uint32_t arge_duplex_mode; 139 uint32_t arge_phymask; 140 uint8_t arge_eaddr[ETHER_ADDR_LEN]; 141 struct resource *arge_res; 142 int arge_rid; 143 struct resource *arge_irq; 144 void *arge_intrhand; 145 device_t arge_miibus; 146 device_t arge_miiproxy; 147 ar71xx_mii_mode arge_miicfg; 148 struct arge_pll_data arge_pllcfg; 149 bus_dma_tag_t arge_parent_tag; 150 bus_dma_tag_t arge_tag; 151 struct mtx arge_mtx; 152 struct callout arge_stat_callout; 153 struct task arge_link_task; 154 struct arge_chain_data arge_cdata; 155 struct arge_ring_data arge_rdata; 156 int arge_link_status; 157 int arge_detach; 158 uint32_t arge_intr_status; 159 int arge_mac_unit; 160 int arge_if_flags; 161 uint32_t arge_debug; 162 struct { 163 uint32_t tx_pkts_unaligned; 164 uint32_t tx_pkts_aligned; 165 uint32_t rx_overflow; 166 uint32_t tx_underflow; 167 } stats; 168 }; 169 170 #endif /* __IF_ARGEVAR_H__ */ 171