1 /*-
2 * Copyright (c) 2001 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef _MACHINE_PTE_H_
30 #define _MACHINE_PTE_H_
31
32 #define PTE_PRESENT 0x0000000000000001
33 #define PTE__RV1_ 0x0000000000000002
34 #define PTE_MA_MASK 0x000000000000001C
35 #define PTE_MA_WB 0x0000000000000000
36 #define PTE_MA_UC 0x0000000000000010
37 #define PTE_MA_UCE 0x0000000000000014
38 #define PTE_MA_WC 0x0000000000000018
39 #define PTE_MA_NATPAGE 0x000000000000001C
40 #define PTE_ACCESSED 0x0000000000000020
41 #define PTE_DIRTY 0x0000000000000040
42 #define PTE_PL_MASK 0x0000000000000180
43 #define PTE_PL_KERN 0x0000000000000000
44 #define PTE_PL_USER 0x0000000000000180
45 #define PTE_AR_MASK 0x0000000000000E00
46 #define PTE_AR_R 0x0000000000000000
47 #define PTE_AR_RX 0x0000000000000200
48 #define PTE_AR_RW 0x0000000000000400
49 #define PTE_AR_RWX 0x0000000000000600
50 #define PTE_AR_R_RW 0x0000000000000800
51 #define PTE_AR_RX_RWX 0x0000000000000A00
52 #define PTE_AR_RWX_RW 0x0000000000000C00
53 #define PTE_AR_X_RX 0x0000000000000E00
54 #define PTE_PPN_MASK 0x0003FFFFFFFFF000
55 #define PTE__RV2_ 0x000C000000000000
56 #define PTE_ED 0x0010000000000000
57 #define PTE_IG_MASK 0xFFE0000000000000
58 #define PTE_WIRED 0x0020000000000000
59 #define PTE_MANAGED 0x0040000000000000
60 #define PTE_PROT_MASK 0x0700000000000000
61
62 #define ITIR__RV1_ 0x0000000000000003
63 #define ITIR_PS_MASK 0x00000000000000FC
64 #define ITIR_KEY_MASK 0x00000000FFFFFF00
65 #define ITIR__RV2_ 0xFFFFFFFF00000000
66
67 #ifndef LOCORE
68
69 typedef uint64_t pt_entry_t;
70
71 static __inline pt_entry_t
pte_atomic_clear(pt_entry_t * ptep,uint64_t val)72 pte_atomic_clear(pt_entry_t *ptep, uint64_t val)
73 {
74 return (atomic_clear_64(ptep, val));
75 }
76
77 static __inline pt_entry_t
pte_atomic_set(pt_entry_t * ptep,uint64_t val)78 pte_atomic_set(pt_entry_t *ptep, uint64_t val)
79 {
80 return (atomic_set_64(ptep, val));
81 }
82
83 /*
84 * A long-format VHPT entry.
85 */
86 struct ia64_lpte {
87 pt_entry_t pte;
88 uint64_t itir;
89 uint64_t tag; /* includes ti */
90 uint64_t chain; /* pa of collision chain */
91 };
92
93 /*
94 * Layout of rr[x].
95 */
96 struct ia64_rr {
97 uint64_t rr_ve :1; /* bit 0 */
98 uint64_t __rv1__ :1; /* bit 1 */
99 uint64_t rr_ps :6; /* bits 2..7 */
100 uint64_t rr_rid :24; /* bits 8..31 */
101 uint64_t __rv2__ :32; /* bits 32..63 */
102 };
103
104 #endif /* !LOCORE */
105
106 #endif /* !_MACHINE_PTE_H_ */
107