1 /*- 2 * Copyright (C) 2013 Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _NTB_REGS_H_ 30 #define _NTB_REGS_H_ 31 32 #define NTB_LINK_ENABLE 0x0000 33 #define NTB_LINK_DISABLE 0x0002 34 #define NTB_LINK_STATUS_ACTIVE 0x2000 35 #define NTB_LINK_SPEED_MASK 0x000f 36 #define NTB_LINK_WIDTH_MASK 0x03f0 37 38 #define XEON_MSIX_CNT 4 39 #define XEON_MAX_SPADS 16 40 #define XEON_MAX_COMPAT_SPADS 8 41 /* Reserve the uppermost bit for link interrupt */ 42 #define XEON_MAX_DB_BITS 15 43 #define XEON_DB_BITS_PER_VEC 5 44 45 #define XEON_DB_HW_LINK 0x8000 46 47 #define XEON_PCICMD_OFFSET 0x0504 48 #define XEON_DEVCTRL_OFFSET 0x0598 49 #define XEON_LINK_STATUS_OFFSET 0x01a2 50 51 #define XEON_PBAR2LMT_OFFSET 0x0000 52 #define XEON_PBAR4LMT_OFFSET 0x0008 53 #define XEON_PBAR2XLAT_OFFSET 0x0010 54 #define XEON_PBAR4XLAT_OFFSET 0x0018 55 #define XEON_SBAR2LMT_OFFSET 0x0020 56 #define XEON_SBAR4LMT_OFFSET 0x0028 57 #define XEON_SBAR2XLAT_OFFSET 0x0030 58 #define XEON_SBAR4XLAT_OFFSET 0x0038 59 #define XEON_SBAR0BASE_OFFSET 0x0040 60 #define XEON_SBAR2BASE_OFFSET 0x0048 61 #define XEON_SBAR4BASE_OFFSET 0x0050 62 #define XEON_NTBCNTL_OFFSET 0x0058 63 #define XEON_SBDF_OFFSET 0x005c 64 #define XEON_PDOORBELL_OFFSET 0x0060 65 #define XEON_PDBMSK_OFFSET 0x0062 66 #define XEON_SDOORBELL_OFFSET 0x0064 67 #define XEON_SDBMSK_OFFSET 0x0066 68 #define XEON_USMEMMISS 0x0070 69 #define XEON_SPAD_OFFSET 0x0080 70 #define XEON_SPADSEMA4_OFFSET 0x00c0 71 #define XEON_WCCNTRL_OFFSET 0x00e0 72 #define XEON_B2B_SPAD_OFFSET 0x0100 73 #define XEON_B2B_DOORBELL_OFFSET 0x0140 74 #define XEON_B2B_XLAT_OFFSET 0x0144 75 76 #define SOC_MSIX_CNT 34 77 #define SOC_MAX_SPADS 16 78 #define SOC_MAX_COMPAT_SPADS 16 79 #define SOC_MAX_DB_BITS 34 80 #define SOC_DB_BITS_PER_VEC 1 81 82 #define SOC_PCICMD_OFFSET 0xb004 83 #define SOC_MBAR23_OFFSET 0xb018 84 #define SOC_MBAR45_OFFSET 0xb020 85 #define SOC_DEVCTRL_OFFSET 0xb048 86 #define SOC_LINK_STATUS_OFFSET 0xb052 87 #define SOC_ERRCORSTS_OFFSET 0xb110 88 89 #define SOC_SBAR2XLAT_OFFSET 0x0008 90 #define SOC_SBAR4XLAT_OFFSET 0x0010 91 #define SOC_PDOORBELL_OFFSET 0x0020 92 #define SOC_PDBMSK_OFFSET 0x0028 93 #define SOC_NTBCNTL_OFFSET 0x0060 94 #define SOC_EBDF_OFFSET 0x0064 95 #define SOC_SPAD_OFFSET 0x0080 96 #define SOC_SPADSEMA_OFFSET 0x00c0 97 #define SOC_STKYSPAD_OFFSET 0x00c4 98 #define SOC_PBAR2XLAT_OFFSET 0x8008 99 #define SOC_PBAR4XLAT_OFFSET 0x8010 100 #define SOC_B2B_DOORBELL_OFFSET 0x8020 101 #define SOC_B2B_SPAD_OFFSET 0x8080 102 #define SOC_B2B_SPADSEMA_OFFSET 0x80c0 103 #define SOC_B2B_STKYSPAD_OFFSET 0x80c4 104 105 #define SOC_MODPHY_PCSREG4 0x1c004 106 #define SOC_MODPHY_PCSREG6 0x1c006 107 108 #define SOC_IP_BASE 0xc000 109 #define SOC_DESKEWSTS_OFFSET (SOC_IP_BASE + 0x3024) 110 #define SOC_LTSSMERRSTS0_OFFSET (SOC_IP_BASE + 0x3180) 111 #define SOC_LTSSMSTATEJMP_OFFSET (SOC_IP_BASE + 0x3040) 112 #define SOC_IBSTERRRCRVSTS0_OFFSET (SOC_IP_BASE + 0x3324) 113 114 #define SOC_DESKEWSTS_DBERR (1 << 15) 115 #define SOC_LTSSMERRSTS0_UNEXPECTEDEI (1 << 20) 116 #define SOC_LTSSMSTATEJMP_FORCEDETECT (1 << 2) 117 #define SOC_IBIST_ERR_OFLOW 0x7fff7fff 118 119 #define NTB_CNTL_BAR23_SNOOP (1 << 2) 120 #define NTB_CNTL_BAR45_SNOOP (1 << 6) 121 #define SOC_CNTL_LINK_DOWN (1 << 16) 122 123 #define XEON_PBAR23SZ_OFFSET 0x00d0 124 #define XEON_PBAR45SZ_OFFSET 0x00d1 125 #define NTB_PPD_OFFSET 0x00d4 126 #define XEON_PPD_CONN_TYPE 0x0003 127 #define XEON_PPD_DEV_TYPE 0x0010 128 #define SOC_PPD_INIT_LINK 0x0008 129 #define SOC_PPD_CONN_TYPE 0x0300 130 #define SOC_PPD_DEV_TYPE 0x1000 131 132 #define NTB_CONN_CLASSIC 0 133 #define NTB_CONN_B2B 1 134 #define NTB_CONN_RP 2 135 136 #define NTB_DEV_DSD 1 137 #define NTB_DEV_USD 0 138 139 #define PBAR2XLAT_USD_ADDR 0x0000004000000000 140 #define PBAR4XLAT_USD_ADDR 0x0000008000000000 141 #define MBAR01_USD_ADDR 0x000000210000000c 142 #define MBAR23_USD_ADDR 0x000000410000000c 143 #define MBAR45_USD_ADDR 0x000000810000000c 144 #define PBAR2XLAT_DSD_ADDR 0x0000004100000000 145 #define PBAR4XLAT_DSD_ADDR 0x0000008100000000 146 #define MBAR01_DSD_ADDR 0x000000200000000c 147 #define MBAR23_DSD_ADDR 0x000000400000000c 148 #define MBAR45_DSD_ADDR 0x000000800000000c 149 150 /* XEON Shadowed MMIO Space */ 151 #define XEON_SHADOW_PDOORBELL_OFFSET 0x60 152 #define XEON_SHADOW_SPAD_OFFSET 0x80 153 154 #endif /* _NTB_REGS_H_ */ 155