xref: /trueos/sys/dev/ncv/ncr53c500hwtab.h (revision 4b319958e7f00cc908274c4518b7a9c5ed821812)
1 /*	$FreeBSD$	*/
2 /*	$NecBSD: ncr53c500hwtab.h,v 1.2.18.1 2001/06/08 06:27:44 honda Exp $	*/
3 /*	$NetBSD$	*/
4 
5 /*-
6  * [NetBSD for NEC PC-98 series]
7  *  Copyright (c) 1996, 1997, 1998
8  *	NetBSD/pc98 porting staff. All rights reserved.
9  *  Copyright (c) 1996, 1997, 1998
10  *	Naofumi HONDA. All rights reserved.
11  *
12  *  Redistribution and use in source and binary forms, with or without
13  *  modification, are permitted provided that the following conditions
14  *  are met:
15  *  1. Redistributions of source code must retain the above copyright
16  *     notice, this list of conditions and the following disclaimer.
17  *  2. Redistributions in binary form must reproduce the above copyright
18  *     notice, this list of conditions and the following disclaimer in the
19  *     documentation and/or other materials provided with the distribution.
20  *  3. The name of the author may not be used to endorse or promote products
21  *     derived from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
31  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
32  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 static struct ncv_hw ncv_template = {
37 	0,			/* CFG1 img */
38 	C2_FE | C2_SCSI2,	/* CFG2 img */
39 	0,			/* CFG3 img */
40 	C4_ANE,			/* CFG4 img */
41 	0x80,			/* CFG5 img */
42 
43 	CLK_40M_F,		/* clock */
44 	200 / 4,		/* max period */
45 	15,			/* max offset */
46 
47 	0x10,			/* CFG3_FSCSI bit */
48 	0x08,			/* CFG3_FCLK bit */
49 };
50