1 /******************************************************************************
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3 Copyright (c) 2001-2015, Intel Corporation
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34
35
36 #include "ixgbe_type.h"
37 #include "ixgbe_dcb.h"
38 #include "ixgbe_dcb_82598.h"
39 #include "ixgbe_dcb_82599.h"
40
41 /**
42 * ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
43 * credits from the configured bandwidth percentages. Credits
44 * are the smallest unit programmable into the underlying
45 * hardware. The IEEE 802.1Qaz specification do not use bandwidth
46 * groups so this is much simplified from the CEE case.
47 */
ixgbe_dcb_calculate_tc_credits(u8 * bw,u16 * refill,u16 * max,int max_frame_size)48 s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
49 int max_frame_size)
50 {
51 int min_percent = 100;
52 int min_credit, multiplier;
53 int i;
54
55 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
56 IXGBE_DCB_CREDIT_QUANTUM;
57
58 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
59 if (bw[i] < min_percent && bw[i])
60 min_percent = bw[i];
61 }
62
63 multiplier = (min_credit / min_percent) + 1;
64
65 /* Find out the hw credits for each TC */
66 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
67 int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
68
69 if (val < min_credit)
70 val = min_credit;
71 refill[i] = (u16)val;
72
73 max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
74 }
75
76 return 0;
77 }
78
79 /**
80 * ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
81 * @ixgbe_dcb_config: Struct containing DCB settings.
82 * @direction: Configuring either Tx or Rx.
83 *
84 * This function calculates the credits allocated to each traffic class.
85 * It should be called only after the rules are checked by
86 * ixgbe_dcb_check_config_cee().
87 */
ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config,u32 max_frame_size,u8 direction)88 s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
89 struct ixgbe_dcb_config *dcb_config,
90 u32 max_frame_size, u8 direction)
91 {
92 struct ixgbe_dcb_tc_path *p;
93 u32 min_multiplier = 0;
94 u16 min_percent = 100;
95 s32 ret_val = IXGBE_SUCCESS;
96 /* Initialization values default for Tx settings */
97 u32 min_credit = 0;
98 u32 credit_refill = 0;
99 u32 credit_max = 0;
100 u16 link_percentage = 0;
101 u8 bw_percent = 0;
102 u8 i;
103
104 if (dcb_config == NULL) {
105 ret_val = IXGBE_ERR_CONFIG;
106 goto out;
107 }
108
109 min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
110 IXGBE_DCB_CREDIT_QUANTUM;
111
112 /* Find smallest link percentage */
113 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
114 p = &dcb_config->tc_config[i].path[direction];
115 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
116 link_percentage = p->bwg_percent;
117
118 link_percentage = (link_percentage * bw_percent) / 100;
119
120 if (link_percentage && link_percentage < min_percent)
121 min_percent = link_percentage;
122 }
123
124 /*
125 * The ratio between traffic classes will control the bandwidth
126 * percentages seen on the wire. To calculate this ratio we use
127 * a multiplier. It is required that the refill credits must be
128 * larger than the max frame size so here we find the smallest
129 * multiplier that will allow all bandwidth percentages to be
130 * greater than the max frame size.
131 */
132 min_multiplier = (min_credit / min_percent) + 1;
133
134 /* Find out the link percentage for each TC first */
135 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
136 p = &dcb_config->tc_config[i].path[direction];
137 bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
138
139 link_percentage = p->bwg_percent;
140 /* Must be careful of integer division for very small nums */
141 link_percentage = (link_percentage * bw_percent) / 100;
142 if (p->bwg_percent > 0 && link_percentage == 0)
143 link_percentage = 1;
144
145 /* Save link_percentage for reference */
146 p->link_percent = (u8)link_percentage;
147
148 /* Calculate credit refill ratio using multiplier */
149 credit_refill = min(link_percentage * min_multiplier,
150 (u32)IXGBE_DCB_MAX_CREDIT_REFILL);
151 p->data_credits_refill = (u16)credit_refill;
152
153 /* Calculate maximum credit for the TC */
154 credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
155
156 /*
157 * Adjustment based on rule checking, if the percentage
158 * of a TC is too small, the maximum credit may not be
159 * enough to send out a jumbo frame in data plane arbitration.
160 */
161 if (credit_max && (credit_max < min_credit))
162 credit_max = min_credit;
163
164 if (direction == IXGBE_DCB_TX_CONFIG) {
165 /*
166 * Adjustment based on rule checking, if the
167 * percentage of a TC is too small, the maximum
168 * credit may not be enough to send out a TSO
169 * packet in descriptor plane arbitration.
170 */
171 if (credit_max && (credit_max <
172 IXGBE_DCB_MIN_TSO_CREDIT)
173 && (hw->mac.type == ixgbe_mac_82598EB))
174 credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
175
176 dcb_config->tc_config[i].desc_credits_max =
177 (u16)credit_max;
178 }
179
180 p->data_credits_max = (u16)credit_max;
181 }
182
183 out:
184 return ret_val;
185 }
186
187 /**
188 * ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
189 * @cfg: dcb configuration to unpack into hardware consumable fields
190 * @map: user priority to traffic class map
191 * @pfc_up: u8 to store user priority PFC bitmask
192 *
193 * This unpacks the dcb configuration PFC info which is stored per
194 * traffic class into a 8bit user priority bitmask that can be
195 * consumed by hardware routines. The priority to tc map must be
196 * updated before calling this routine to use current up-to maps.
197 */
ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config * cfg,u8 * map,u8 * pfc_up)198 void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
199 {
200 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
201 int up;
202
203 /*
204 * If the TC for this user priority has PFC enabled then set the
205 * matching bit in 'pfc_up' to reflect that PFC is enabled.
206 */
207 for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
208 if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
209 *pfc_up |= 1 << up;
210 }
211 }
212
ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config * cfg,int direction,u16 * refill)213 void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
214 u16 *refill)
215 {
216 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
217 int tc;
218
219 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
220 refill[tc] = tc_config[tc].path[direction].data_credits_refill;
221 }
222
ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config * cfg,u16 * max)223 void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
224 {
225 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
226 int tc;
227
228 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
229 max[tc] = tc_config[tc].desc_credits_max;
230 }
231
ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config * cfg,int direction,u8 * bwgid)232 void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
233 u8 *bwgid)
234 {
235 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
236 int tc;
237
238 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
239 bwgid[tc] = tc_config[tc].path[direction].bwg_id;
240 }
241
ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config * cfg,int direction,u8 * tsa)242 void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
243 u8 *tsa)
244 {
245 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
246 int tc;
247
248 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
249 tsa[tc] = tc_config[tc].path[direction].tsa;
250 }
251
ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config * cfg,int direction,u8 up)252 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
253 {
254 struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
255 u8 prio_mask = 1 << up;
256 u8 tc = cfg->num_tcs.pg_tcs;
257
258 /* If tc is 0 then DCB is likely not enabled or supported */
259 if (!tc)
260 goto out;
261
262 /*
263 * Test from maximum TC to 1 and report the first match we find. If
264 * we find no match we can assume that the TC is 0 since the TC must
265 * be set for all user priorities
266 */
267 for (tc--; tc; tc--) {
268 if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
269 break;
270 }
271 out:
272 return tc;
273 }
274
ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config * cfg,int direction,u8 * map)275 void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
276 u8 *map)
277 {
278 u8 up;
279
280 for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
281 map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
282 }
283
284 /**
285 * ixgbe_dcb_config - Struct containing DCB settings.
286 * @dcb_config: Pointer to DCB config structure
287 *
288 * This function checks DCB rules for DCB settings.
289 * The following rules are checked:
290 * 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
291 * 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
292 * Group must total 100.
293 * 3. A Traffic Class should not be set to both Link Strict Priority
294 * and Group Strict Priority.
295 * 4. Link strict Bandwidth Groups can only have link strict traffic classes
296 * with zero bandwidth.
297 */
ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config * dcb_config)298 s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
299 {
300 struct ixgbe_dcb_tc_path *p;
301 s32 ret_val = IXGBE_SUCCESS;
302 u8 i, j, bw = 0, bw_id;
303 u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
304 bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
305
306 memset(bw_sum, 0, sizeof(bw_sum));
307 memset(link_strict, 0, sizeof(link_strict));
308
309 /* First Tx, then Rx */
310 for (i = 0; i < 2; i++) {
311 /* Check each traffic class for rule violation */
312 for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
313 p = &dcb_config->tc_config[j].path[i];
314
315 bw = p->bwg_percent;
316 bw_id = p->bwg_id;
317
318 if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
319 ret_val = IXGBE_ERR_CONFIG;
320 goto err_config;
321 }
322 if (p->tsa == ixgbe_dcb_tsa_strict) {
323 link_strict[i][bw_id] = TRUE;
324 /* Link strict should have zero bandwidth */
325 if (bw) {
326 ret_val = IXGBE_ERR_CONFIG;
327 goto err_config;
328 }
329 } else if (!bw) {
330 /*
331 * Traffic classes without link strict
332 * should have non-zero bandwidth.
333 */
334 ret_val = IXGBE_ERR_CONFIG;
335 goto err_config;
336 }
337 bw_sum[i][bw_id] += bw;
338 }
339
340 bw = 0;
341
342 /* Check each bandwidth group for rule violation */
343 for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
344 bw += dcb_config->bw_percentage[i][j];
345 /*
346 * Sum of bandwidth percentages of all traffic classes
347 * within a Bandwidth Group must total 100 except for
348 * link strict group (zero bandwidth).
349 */
350 if (link_strict[i][j]) {
351 if (bw_sum[i][j]) {
352 /*
353 * Link strict group should have zero
354 * bandwidth.
355 */
356 ret_val = IXGBE_ERR_CONFIG;
357 goto err_config;
358 }
359 } else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
360 bw_sum[i][j] != 0) {
361 ret_val = IXGBE_ERR_CONFIG;
362 goto err_config;
363 }
364 }
365
366 if (bw != IXGBE_DCB_BW_PERCENT) {
367 ret_val = IXGBE_ERR_CONFIG;
368 goto err_config;
369 }
370 }
371
372 err_config:
373 DEBUGOUT2("DCB error code %d while checking %s settings.\n",
374 ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
375
376 return ret_val;
377 }
378
379 /**
380 * ixgbe_dcb_get_tc_stats - Returns status of each traffic class
381 * @hw: pointer to hardware structure
382 * @stats: pointer to statistics structure
383 * @tc_count: Number of elements in bwg_array.
384 *
385 * This function returns the status data for each of the Traffic Classes in use.
386 */
ixgbe_dcb_get_tc_stats(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)387 s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
388 u8 tc_count)
389 {
390 s32 ret = IXGBE_NOT_IMPLEMENTED;
391 switch (hw->mac.type) {
392 case ixgbe_mac_82598EB:
393 ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
394 break;
395 case ixgbe_mac_82599EB:
396 case ixgbe_mac_X540:
397 case ixgbe_mac_X550:
398 case ixgbe_mac_X550EM_x:
399 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
400 ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
401 break;
402 #endif
403 default:
404 break;
405 }
406 return ret;
407 }
408
409 /**
410 * ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
411 * @hw: pointer to hardware structure
412 * @stats: pointer to statistics structure
413 * @tc_count: Number of elements in bwg_array.
414 *
415 * This function returns the CBFC status data for each of the Traffic Classes.
416 */
ixgbe_dcb_get_pfc_stats(struct ixgbe_hw * hw,struct ixgbe_hw_stats * stats,u8 tc_count)417 s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
418 u8 tc_count)
419 {
420 s32 ret = IXGBE_NOT_IMPLEMENTED;
421 switch (hw->mac.type) {
422 case ixgbe_mac_82598EB:
423 ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
424 break;
425 case ixgbe_mac_82599EB:
426 case ixgbe_mac_X540:
427 case ixgbe_mac_X550:
428 case ixgbe_mac_X550EM_x:
429 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
430 ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
431 break;
432 #endif
433 default:
434 break;
435 }
436 return ret;
437 }
438
439 /**
440 * ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
441 * @hw: pointer to hardware structure
442 * @dcb_config: pointer to ixgbe_dcb_config structure
443 *
444 * Configure Rx Data Arbiter and credits for each traffic class.
445 */
ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)446 s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
447 struct ixgbe_dcb_config *dcb_config)
448 {
449 s32 ret = IXGBE_NOT_IMPLEMENTED;
450 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
451 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
452 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
453 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
454 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
455
456 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
457 ixgbe_dcb_unpack_max_cee(dcb_config, max);
458 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
459 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
460 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
461
462 switch (hw->mac.type) {
463 case ixgbe_mac_82598EB:
464 ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
465 break;
466 case ixgbe_mac_82599EB:
467 case ixgbe_mac_X540:
468 case ixgbe_mac_X550:
469 case ixgbe_mac_X550EM_x:
470 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
471 ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
472 tsa, map);
473 break;
474 #endif
475 default:
476 break;
477 }
478 return ret;
479 }
480
481 /**
482 * ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
483 * @hw: pointer to hardware structure
484 * @dcb_config: pointer to ixgbe_dcb_config structure
485 *
486 * Configure Tx Descriptor Arbiter and credits for each traffic class.
487 */
ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)488 s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
489 struct ixgbe_dcb_config *dcb_config)
490 {
491 s32 ret = IXGBE_NOT_IMPLEMENTED;
492 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
493 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
494 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
495 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
496
497 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
498 ixgbe_dcb_unpack_max_cee(dcb_config, max);
499 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
500 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
501
502 switch (hw->mac.type) {
503 case ixgbe_mac_82598EB:
504 ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
505 bwgid, tsa);
506 break;
507 case ixgbe_mac_82599EB:
508 case ixgbe_mac_X540:
509 case ixgbe_mac_X550:
510 case ixgbe_mac_X550EM_x:
511 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
512 ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
513 bwgid, tsa);
514 break;
515 #endif
516 default:
517 break;
518 }
519 return ret;
520 }
521
522 /**
523 * ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
524 * @hw: pointer to hardware structure
525 * @dcb_config: pointer to ixgbe_dcb_config structure
526 *
527 * Configure Tx Data Arbiter and credits for each traffic class.
528 */
ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)529 s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
530 struct ixgbe_dcb_config *dcb_config)
531 {
532 s32 ret = IXGBE_NOT_IMPLEMENTED;
533 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
534 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
535 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
536 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
537 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
538
539 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
540 ixgbe_dcb_unpack_max_cee(dcb_config, max);
541 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
542 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
543 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
544
545 switch (hw->mac.type) {
546 case ixgbe_mac_82598EB:
547 ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
548 bwgid, tsa);
549 break;
550 case ixgbe_mac_82599EB:
551 case ixgbe_mac_X540:
552 case ixgbe_mac_X550:
553 case ixgbe_mac_X550EM_x:
554 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
555 ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
556 bwgid, tsa,
557 map);
558 break;
559 #endif
560 default:
561 break;
562 }
563 return ret;
564 }
565
566 /**
567 * ixgbe_dcb_config_pfc_cee - Config priority flow control
568 * @hw: pointer to hardware structure
569 * @dcb_config: pointer to ixgbe_dcb_config structure
570 *
571 * Configure Priority Flow Control for each traffic class.
572 */
ixgbe_dcb_config_pfc_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)573 s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
574 struct ixgbe_dcb_config *dcb_config)
575 {
576 s32 ret = IXGBE_NOT_IMPLEMENTED;
577 u8 pfc_en;
578 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
579
580 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
581 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
582
583 switch (hw->mac.type) {
584 case ixgbe_mac_82598EB:
585 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
586 break;
587 case ixgbe_mac_82599EB:
588 case ixgbe_mac_X540:
589 case ixgbe_mac_X550:
590 case ixgbe_mac_X550EM_x:
591 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
592 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
593 break;
594 #endif
595 default:
596 break;
597 }
598 return ret;
599 }
600
601 /**
602 * ixgbe_dcb_config_tc_stats - Config traffic class statistics
603 * @hw: pointer to hardware structure
604 *
605 * Configure queue statistics registers, all queues belonging to same traffic
606 * class uses a single set of queue statistics counters.
607 */
ixgbe_dcb_config_tc_stats(struct ixgbe_hw * hw)608 s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
609 {
610 s32 ret = IXGBE_NOT_IMPLEMENTED;
611 switch (hw->mac.type) {
612 case ixgbe_mac_82598EB:
613 ret = ixgbe_dcb_config_tc_stats_82598(hw);
614 break;
615 case ixgbe_mac_82599EB:
616 case ixgbe_mac_X540:
617 case ixgbe_mac_X550:
618 case ixgbe_mac_X550EM_x:
619 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
620 ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
621 break;
622 #endif
623 default:
624 break;
625 }
626 return ret;
627 }
628
629 /**
630 * ixgbe_dcb_hw_config_cee - Config and enable DCB
631 * @hw: pointer to hardware structure
632 * @dcb_config: pointer to ixgbe_dcb_config structure
633 *
634 * Configure dcb settings and enable dcb mode.
635 */
ixgbe_dcb_hw_config_cee(struct ixgbe_hw * hw,struct ixgbe_dcb_config * dcb_config)636 s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
637 struct ixgbe_dcb_config *dcb_config)
638 {
639 s32 ret = IXGBE_NOT_IMPLEMENTED;
640 u8 pfc_en;
641 u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
642 u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
643 u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
644 u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
645 u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
646
647 /* Unpack CEE standard containers */
648 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
649 ixgbe_dcb_unpack_max_cee(dcb_config, max);
650 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
651 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
652 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
653
654 hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs,
655 0, dcb_config->rx_pba_cfg);
656
657 switch (hw->mac.type) {
658 case ixgbe_mac_82598EB:
659 ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
660 refill, max, bwgid, tsa);
661 break;
662 case ixgbe_mac_82599EB:
663 case ixgbe_mac_X540:
664 case ixgbe_mac_X550:
665 case ixgbe_mac_X550EM_x:
666 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
667 ixgbe_dcb_config_82599(hw, dcb_config);
668 ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
669 refill, max, bwgid,
670 tsa, map);
671
672 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
673 break;
674 #endif
675 default:
676 break;
677 }
678
679 if (!ret && dcb_config->pfc_mode_enable) {
680 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
681 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
682 }
683
684 return ret;
685 }
686
687 /* Helper routines to abstract HW specifics from DCB netlink ops */
ixgbe_dcb_config_pfc(struct ixgbe_hw * hw,u8 pfc_en,u8 * map)688 s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
689 {
690 int ret = IXGBE_ERR_PARAM;
691
692 switch (hw->mac.type) {
693 case ixgbe_mac_82598EB:
694 ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
695 break;
696 case ixgbe_mac_82599EB:
697 case ixgbe_mac_X540:
698 case ixgbe_mac_X550:
699 case ixgbe_mac_X550EM_x:
700 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
701 ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
702 break;
703 #endif
704 default:
705 break;
706 }
707 return ret;
708 }
709
ixgbe_dcb_hw_config(struct ixgbe_hw * hw,u16 * refill,u16 * max,u8 * bwg_id,u8 * tsa,u8 * map)710 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
711 u8 *bwg_id, u8 *tsa, u8 *map)
712 {
713 switch (hw->mac.type) {
714 case ixgbe_mac_82598EB:
715 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
716 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
717 tsa);
718 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
719 tsa);
720 break;
721 case ixgbe_mac_82599EB:
722 case ixgbe_mac_X540:
723 case ixgbe_mac_X550:
724 case ixgbe_mac_X550EM_x:
725 #if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
726 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
727 tsa, map);
728 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
729 tsa);
730 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
731 tsa, map);
732 break;
733 #endif
734 default:
735 break;
736 }
737 return 0;
738 }
739