1 /*-
2 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * This software is derived from software provide by Kwikbyte who specifically
25 * disclaimed copyright on the code.
26 *
27 * $FreeBSD$
28 */
29
30 #include "at91rm9200.h"
31 #include "at91rm9200_lowlevel.h"
32
33 extern int __bss_start__[];
34 extern int __bss_end__[];
35
36 #define BAUD 115200
37 #define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \
38 AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK)
39
40 /*
41 * void DefaultSystemInit(void)
42 * Load the system with sane values based on how the system is configured.
43 * at91rm9200_lowlevel.h is expected to define the necessary parameters.
44 */
45 void
_init(void)46 _init(void)
47 {
48 int *i;
49
50 AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
51 AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
52
53 register unsigned value;
54 volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE;
55
56 AT91C_BASE_ST->ST_RTMR = 1;
57 #ifdef BOOT_TSC
58 // For the TSC board, we turn ON the one LED we have while
59 // early in boot.
60 AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10;
61 AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10;
62 AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10;
63 #endif
64
65 #if defined(BOOT_KB920X)
66 AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
67 AT91C_PIO_PC20;
68 AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
69 AT91C_PIO_PC20;
70 AT91C_BASE_PIOC->PIO_SODR = AT91C_PIO_PC18 | AT91C_PIO_PC19 |
71 AT91C_PIO_PC20;
72 AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC18;
73 #endif
74
75 // configure clocks
76 // assume:
77 // main osc = 10Mhz
78 // PLLB configured for 96MHz (48MHz after div)
79 // CSS = PLLB
80 // set PLLA = 180MHz
81 // assume main osc = 10Mhz
82 // div = 5 , out = 2 (150MHz = 240MHz)
83 value = AT91C_BASE_CKGR->CKGR_PLLAR;
84 value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA);
85 value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA |
86 ((OSC_MAIN_MULT - 1) << 16);
87 AT91C_BASE_CKGR->CKGR_PLLAR = value;
88
89 // wait for lock
90 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA))
91 continue;
92
93 // change divider = 3, pres = 1
94 value = AT91C_BASE_PMC->PMC_MCKR;
95 value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES);
96 value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK;
97 AT91C_BASE_PMC->PMC_MCKR = value;
98
99 // wait for update
100 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
101 continue;
102
103 // change CSS = PLLA
104 value &= ~AT91C_PMC_CSS;
105 value |= AT91C_PMC_CSS_PLLA_CLK;
106 AT91C_BASE_PMC->PMC_MCKR = value;
107
108 // wait for update
109 while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
110 continue;
111
112 #ifdef BOOT_KB920X
113 // setup flash access (allow ample margin)
114 // 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
115 ((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] =
116 AT91C_SMC2_WSEN |
117 (9 & AT91C_SMC2_NWS) |
118 ((1 << 8) & AT91C_SMC2_TDF) |
119 AT91C_SMC2_DBW_8 |
120 ((1 << 24) & AT91C_SMC2_RWSETUP) |
121 ((1 << 29) & AT91C_SMC2_RWHOLD);
122 #endif
123
124 // setup SDRAM access
125 // EBI chip-select register (CS1 = SDRAM controller)
126 // 9 col, 13row, 4 bank, CAS2
127 // write recovery = 2 (Twr)
128 // row cycle = 5 (Trc)
129 // precharge delay = 2 (Trp)
130 // row to col delay 2 (Trcd)
131 // active to precharge = 4 (Tras)
132 // exit self refresh to active = 6 (Txsr)
133 value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA;
134 value &= ~AT91C_EBI_CS1A;
135 value |= AT91C_EBI_CS1A_SDRAMC;
136 AT91C_BASE_EBI->EBI_CSA = value;
137
138 AT91C_BASE_SDRC->SDRC_CR =
139 #if defined(KB9202_B) || defined(SDRAM_128M)
140 AT91C_SDRC_NC_10 |
141 #else
142 AT91C_SDRC_NC_9 |
143 #endif
144 AT91C_SDRC_NR_13 |
145 AT91C_SDRC_NB_4_BANKS |
146 AT91C_SDRC_CAS_2 |
147 ((2 << 7) & AT91C_SDRC_TWR) |
148 ((5 << 11) & AT91C_SDRC_TRC) |
149 ((2 << 15) & AT91C_SDRC_TRP) |
150 ((2 << 19) & AT91C_SDRC_TRCD) |
151 ((4 << 23) & AT91C_SDRC_TRAS) |
152 ((6 << 27) & AT91C_SDRC_TXSR);
153
154 // Step 1: We assume 200us of idle time.
155 // Step 2: Issue an all banks precharge command
156 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD;
157 *p = 0;
158
159 // Step 3: Issue 8 Auto-refresh (CBR) cycles
160 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD;
161 *p = 0;
162 *p = 0;
163 *p = 0;
164 *p = 0;
165 *p = 0;
166 *p = 0;
167 *p = 0;
168 *p = 0;
169
170 // Step 4: Issue an Mode Set Register (MRS) cycle to program in
171 // the parameters that we setup in the SDRC_CR register above.
172 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD;
173 *p = 0;
174
175 // Step 5: set the refresh timer and access memory to start it
176 // running. We have to wait 3 clocks after the LMR_CMD above,
177 // and this fits the bill nicely.
178 AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000;
179 *p = 0;
180
181 // Step 6: Set normal mode.
182 AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD;
183 *p = 0;
184
185 #if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS
186 // Turn on the upper 16 bits on the SDRAM bus.
187 AT91C_BASE_PIOC->PIO_ASR = 0xffff0000;
188 AT91C_BASE_PIOC->PIO_PDR = 0xffff0000;
189 #endif
190 // Configure DBGU -use local routine optimized for space
191 AT91C_BASE_PIOA->PIO_ASR = AT91C_PIO_PA31 | AT91C_PIO_PA30;
192 AT91C_BASE_PIOA->PIO_PDR = AT91C_PIO_PA31 | AT91C_PIO_PA30;
193 pUSART->US_IDR = (unsigned int) -1;
194 pUSART->US_CR =
195 AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
196 pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10);
197 pUSART->US_TTGR = 0;
198 pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
199 pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
200 pPDC->PDC_TNPR = 0;
201 pPDC->PDC_TNCR = 0;
202
203 pPDC->PDC_RNPR = 0;
204 pPDC->PDC_RNCR = 0;
205
206 pPDC->PDC_TPR = 0;
207 pPDC->PDC_TCR = 0;
208
209 pPDC->PDC_RPR = 0;
210 pPDC->PDC_RCR = 0;
211
212 pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
213 pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
214
215 pUSART->US_MR = AT91C_US_ASYNC_MODE;
216 pUSART->US_CR = AT91C_US_TXEN;
217 pUSART->US_CR = AT91C_US_RXEN;
218
219 /* Zero BSS now that we have memory setup */
220 i = (int *)__bss_start__;
221 while (i < (int *)__bss_end__)
222 *i++ = 0;
223 }
224