1 /*-
2 * Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/bus.h>
33 #include <sys/kernel.h>
34 #include <sys/lock.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/rman.h>
39 #include <sys/sysctl.h>
40 #include <sys/taskqueue.h>
41
42 #include <machine/bus.h>
43
44 #include <dev/fdt/fdt_common.h>
45 #include <dev/ofw/ofw_bus.h>
46 #include <dev/ofw/ofw_bus_subr.h>
47
48 #include <dev/mmc/bridge.h>
49 #include <dev/mmc/mmcreg.h>
50 #include <dev/mmc/mmcbrvar.h>
51
52 #include <dev/sdhci/sdhci.h>
53 #include "sdhci_if.h"
54
55 #include "bcm2835_dma.h"
56 #include "bcm2835_vcbus.h"
57
58 #define BCM2835_DEFAULT_SDHCI_FREQ 50
59
60 #define BCM_SDHCI_BUFFER_SIZE 512
61 #define NUM_DMA_SEGS 2
62
63 #ifdef DEBUG
64 #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \
65 printf(fmt,##args); } while (0)
66 #else
67 #define dprintf(fmt, args...)
68 #endif
69
70 static int bcm2835_sdhci_hs = 1;
71 static int bcm2835_sdhci_pio_mode = 0;
72
73 TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
74 TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
75
76 struct bcm_sdhci_softc {
77 device_t sc_dev;
78 struct mtx sc_mtx;
79 struct resource * sc_mem_res;
80 struct resource * sc_irq_res;
81 bus_space_tag_t sc_bst;
82 bus_space_handle_t sc_bsh;
83 void * sc_intrhand;
84 struct mmc_request * sc_req;
85 struct mmc_data * sc_data;
86 uint32_t sc_flags;
87 #define LPC_SD_FLAGS_IGNORECRC (1 << 0)
88 int sc_xfer_direction;
89 #define DIRECTION_READ 0
90 #define DIRECTION_WRITE 1
91 int sc_xfer_done;
92 int sc_bus_busy;
93 struct sdhci_slot sc_slot;
94 int sc_dma_inuse;
95 int sc_dma_ch;
96 bus_dma_tag_t sc_dma_tag;
97 bus_dmamap_t sc_dma_map;
98 vm_paddr_t sc_sdhci_buffer_phys;
99 uint32_t cmd_and_mode;
100 bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS];
101 bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS];
102 int dmamap_seg_count;
103 int dmamap_seg_index;
104 int dmamap_status;
105 };
106
107 static int bcm_sdhci_probe(device_t);
108 static int bcm_sdhci_attach(device_t);
109 static int bcm_sdhci_detach(device_t);
110 static void bcm_sdhci_intr(void *);
111
112 static int bcm_sdhci_get_ro(device_t, device_t);
113 static void bcm_sdhci_dma_intr(int ch, void *arg);
114
115 #define bcm_sdhci_lock(_sc) \
116 mtx_lock(&_sc->sc_mtx);
117 #define bcm_sdhci_unlock(_sc) \
118 mtx_unlock(&_sc->sc_mtx);
119
120 static void
bcm_sdhci_dmacb(void * arg,bus_dma_segment_t * segs,int nseg,int err)121 bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
122 {
123 struct bcm_sdhci_softc *sc = arg;
124 int i;
125
126 sc->dmamap_status = err;
127 sc->dmamap_seg_count = nseg;
128
129 /* Note nseg is guaranteed to be zero if err is non-zero. */
130 for (i = 0; i < nseg; i++) {
131 sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
132 sc->dmamap_seg_sizes[i] = segs[i].ds_len;
133 }
134 }
135
136 static int
bcm_sdhci_probe(device_t dev)137 bcm_sdhci_probe(device_t dev)
138 {
139
140 if (!ofw_bus_status_okay(dev))
141 return (ENXIO);
142
143 if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-sdhci"))
144 return (ENXIO);
145
146 device_set_desc(dev, "Broadcom 2708 SDHCI controller");
147 return (BUS_PROBE_DEFAULT);
148 }
149
150 static int
bcm_sdhci_attach(device_t dev)151 bcm_sdhci_attach(device_t dev)
152 {
153 struct bcm_sdhci_softc *sc = device_get_softc(dev);
154 int rid, err;
155 phandle_t node;
156 pcell_t cell;
157 int default_freq;
158
159 sc->sc_dev = dev;
160 sc->sc_req = NULL;
161 err = 0;
162
163 default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
164 node = ofw_bus_get_node(sc->sc_dev);
165 if ((OF_getprop(node, "clock-frequency", &cell, sizeof(cell))) > 0)
166 default_freq = (int)fdt32_to_cpu(cell)/1000000;
167
168 dprintf("SDHCI frequency: %dMHz\n", default_freq);
169
170 mtx_init(&sc->sc_mtx, "bcm sdhci", "sdhci", MTX_DEF);
171
172 rid = 0;
173 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
174 RF_ACTIVE);
175 if (!sc->sc_mem_res) {
176 device_printf(dev, "cannot allocate memory window\n");
177 err = ENXIO;
178 goto fail;
179 }
180
181 sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
182 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
183
184 rid = 0;
185 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
186 RF_ACTIVE);
187 if (!sc->sc_irq_res) {
188 device_printf(dev, "cannot allocate interrupt\n");
189 err = ENXIO;
190 goto fail;
191 }
192
193 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
194 NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
195 device_printf(dev, "cannot setup interrupt handler\n");
196 err = ENXIO;
197 goto fail;
198 }
199
200 if (!bcm2835_sdhci_pio_mode)
201 sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
202
203 sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
204 if (bcm2835_sdhci_hs)
205 sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
206 sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
207 sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
208 | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
209 | SDHCI_QUIRK_DONT_SET_HISPD_BIT
210 | SDHCI_QUIRK_MISSING_CAPS;
211
212 sdhci_init_slot(dev, &sc->sc_slot, 0);
213
214 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
215 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
216 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
217 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
218 sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
219 if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
220 goto fail;
221
222 bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
223
224 /* Allocate bus_dma resources. */
225 err = bus_dma_tag_create(bus_get_dma_tag(dev),
226 1, 0, BUS_SPACE_MAXADDR_32BIT,
227 BUS_SPACE_MAXADDR, NULL, NULL,
228 BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
229 BUS_DMA_ALLOCNOW, NULL, NULL,
230 &sc->sc_dma_tag);
231
232 if (err) {
233 device_printf(dev, "failed allocate DMA tag");
234 goto fail;
235 }
236
237 err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
238 if (err) {
239 device_printf(dev, "bus_dmamap_create failed\n");
240 goto fail;
241 }
242
243 sc->sc_sdhci_buffer_phys = BUS_SPACE_PHYSADDR(sc->sc_mem_res,
244 SDHCI_BUFFER);
245
246 bus_generic_probe(dev);
247 bus_generic_attach(dev);
248
249 sdhci_start_slot(&sc->sc_slot);
250
251 return (0);
252
253 fail:
254 if (sc->sc_intrhand)
255 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
256 if (sc->sc_irq_res)
257 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
258 if (sc->sc_mem_res)
259 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
260 mtx_destroy(&sc->sc_mtx);
261
262 return (err);
263 }
264
265 static int
bcm_sdhci_detach(device_t dev)266 bcm_sdhci_detach(device_t dev)
267 {
268
269 return (EBUSY);
270 }
271
272 static void
bcm_sdhci_intr(void * arg)273 bcm_sdhci_intr(void *arg)
274 {
275 struct bcm_sdhci_softc *sc = arg;
276
277 sdhci_generic_intr(&sc->sc_slot);
278 }
279
280 static int
bcm_sdhci_get_ro(device_t bus,device_t child)281 bcm_sdhci_get_ro(device_t bus, device_t child)
282 {
283
284 return (0);
285 }
286
287 static inline uint32_t
RD4(struct bcm_sdhci_softc * sc,bus_size_t off)288 RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
289 {
290 uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
291 return val;
292 }
293
294 static inline void
WR4(struct bcm_sdhci_softc * sc,bus_size_t off,uint32_t val)295 WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
296 {
297
298 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
299 /*
300 * The Arasan HC has a bug where it may lose the content of
301 * consecutive writes to registers that are within two SD-card
302 * clock cycles of each other (a clock domain crossing problem).
303 */
304 if (sc->sc_slot.clock > 0)
305 DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
306 }
307
308 static uint8_t
bcm_sdhci_read_1(device_t dev,struct sdhci_slot * slot,bus_size_t off)309 bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
310 {
311 struct bcm_sdhci_softc *sc = device_get_softc(dev);
312 uint32_t val = RD4(sc, off & ~3);
313
314 return ((val >> (off & 3)*8) & 0xff);
315 }
316
317 static uint16_t
bcm_sdhci_read_2(device_t dev,struct sdhci_slot * slot,bus_size_t off)318 bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
319 {
320 struct bcm_sdhci_softc *sc = device_get_softc(dev);
321 uint32_t val = RD4(sc, off & ~3);
322
323 /*
324 * Standard 32-bit handling of command and transfer mode.
325 */
326 if (off == SDHCI_TRANSFER_MODE) {
327 return (sc->cmd_and_mode >> 16);
328 } else if (off == SDHCI_COMMAND_FLAGS) {
329 return (sc->cmd_and_mode & 0x0000ffff);
330 }
331 return ((val >> (off & 3)*8) & 0xffff);
332 }
333
334 static uint32_t
bcm_sdhci_read_4(device_t dev,struct sdhci_slot * slot,bus_size_t off)335 bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
336 {
337 struct bcm_sdhci_softc *sc = device_get_softc(dev);
338
339 return RD4(sc, off);
340 }
341
342 static void
bcm_sdhci_read_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)343 bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
344 uint32_t *data, bus_size_t count)
345 {
346 struct bcm_sdhci_softc *sc = device_get_softc(dev);
347
348 bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
349 }
350
351 static void
bcm_sdhci_write_1(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint8_t val)352 bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val)
353 {
354 struct bcm_sdhci_softc *sc = device_get_softc(dev);
355 uint32_t val32 = RD4(sc, off & ~3);
356 val32 &= ~(0xff << (off & 3)*8);
357 val32 |= (val << (off & 3)*8);
358 WR4(sc, off & ~3, val32);
359 }
360
361 static void
bcm_sdhci_write_2(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint16_t val)362 bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val)
363 {
364 struct bcm_sdhci_softc *sc = device_get_softc(dev);
365 uint32_t val32;
366 if (off == SDHCI_COMMAND_FLAGS)
367 val32 = sc->cmd_and_mode;
368 else
369 val32 = RD4(sc, off & ~3);
370 val32 &= ~(0xffff << (off & 3)*8);
371 val32 |= (val << (off & 3)*8);
372 if (off == SDHCI_TRANSFER_MODE)
373 sc->cmd_and_mode = val32;
374 else {
375 WR4(sc, off & ~3, val32);
376 if (off == SDHCI_COMMAND_FLAGS)
377 sc->cmd_and_mode = val32;
378 }
379 }
380
381 static void
bcm_sdhci_write_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t val)382 bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val)
383 {
384 struct bcm_sdhci_softc *sc = device_get_softc(dev);
385 WR4(sc, off, val);
386 }
387
388 static void
bcm_sdhci_write_multi_4(device_t dev,struct sdhci_slot * slot,bus_size_t off,uint32_t * data,bus_size_t count)389 bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
390 uint32_t *data, bus_size_t count)
391 {
392 struct bcm_sdhci_softc *sc = device_get_softc(dev);
393
394 bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
395 }
396
397 static void
bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc * sc)398 bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
399 {
400 struct sdhci_slot *slot;
401 vm_paddr_t pdst, psrc;
402 int err, idx, len, sync_op;
403
404 slot = &sc->sc_slot;
405 idx = sc->dmamap_seg_index++;
406 len = sc->dmamap_seg_sizes[idx];
407 slot->offset += len;
408
409 if (slot->curcmd->data->flags & MMC_DATA_READ) {
410 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
411 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
412 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
413 BCM_DMA_INC_ADDR,
414 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
415 psrc = sc->sc_sdhci_buffer_phys;
416 pdst = sc->dmamap_seg_addrs[idx];
417 sync_op = BUS_DMASYNC_PREREAD;
418 } else {
419 bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
420 BCM_DMA_INC_ADDR,
421 (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
422 bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
423 BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
424 psrc = sc->dmamap_seg_addrs[idx];
425 pdst = sc->sc_sdhci_buffer_phys;
426 sync_op = BUS_DMASYNC_PREWRITE;
427 }
428
429 /*
430 * When starting a new DMA operation do the busdma sync operation, and
431 * disable SDCHI data interrrupts because we'll be driven by DMA
432 * interrupts (or SDHCI error interrupts) until the IO is done.
433 */
434 if (idx == 0) {
435 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
436 slot->intmask &= ~(SDHCI_INT_DATA_AVAIL |
437 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
438 bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE,
439 slot->intmask);
440 }
441
442 /*
443 * Start the DMA transfer. Only programming errors (like failing to
444 * allocate a channel) cause a non-zero return from bcm_dma_start().
445 */
446 err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
447 KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
448 }
449
450 static void
bcm_sdhci_dma_intr(int ch,void * arg)451 bcm_sdhci_dma_intr(int ch, void *arg)
452 {
453 struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
454 struct sdhci_slot *slot = &sc->sc_slot;
455 uint32_t reg, mask;
456 int left, sync_op;
457
458 mtx_lock(&slot->mtx);
459
460 /*
461 * If there are more segments for the current dma, start the next one.
462 * Otherwise unload the dma map and decide what to do next based on the
463 * status of the sdhci controller and whether there's more data left.
464 */
465 if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
466 bcm_sdhci_start_dma_seg(sc);
467 mtx_unlock(&slot->mtx);
468 return;
469 }
470
471 if (slot->curcmd->data->flags & MMC_DATA_READ) {
472 sync_op = BUS_DMASYNC_POSTREAD;
473 mask = SDHCI_INT_DATA_AVAIL;
474 } else {
475 sync_op = BUS_DMASYNC_POSTWRITE;
476 mask = SDHCI_INT_SPACE_AVAIL;
477 }
478 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
479 bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
480
481 sc->dmamap_seg_count = 0;
482 sc->dmamap_seg_index = 0;
483
484 left = min(BCM_SDHCI_BUFFER_SIZE,
485 slot->curcmd->data->len - slot->offset);
486
487 /* DATA END? */
488 reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
489
490 if (reg & SDHCI_INT_DATA_END) {
491 /* ACK for all outstanding interrupts */
492 bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
493
494 /* enable INT */
495 slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
496 | SDHCI_INT_DATA_END;
497 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
498 slot->intmask);
499
500 /* finish this data */
501 sdhci_finish_data(slot);
502 }
503 else {
504 /* already available? */
505 if (reg & mask) {
506
507 /* ACK for DATA_AVAIL or SPACE_AVAIL */
508 bcm_sdhci_write_4(slot->bus, slot,
509 SDHCI_INT_STATUS, mask);
510
511 /* continue next DMA transfer */
512 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
513 (uint8_t *)slot->curcmd->data->data +
514 slot->offset, left, bcm_sdhci_dmacb, sc,
515 BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) {
516 slot->curcmd->error = MMC_ERR_NO_MEMORY;
517 sdhci_finish_data(slot);
518 } else {
519 bcm_sdhci_start_dma_seg(sc);
520 }
521 } else {
522 /* wait for next data by INT */
523
524 /* enable INT */
525 slot->intmask |= SDHCI_INT_DATA_AVAIL |
526 SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
527 bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
528 slot->intmask);
529 }
530 }
531
532 mtx_unlock(&slot->mtx);
533 }
534
535 static void
bcm_sdhci_read_dma(device_t dev,struct sdhci_slot * slot)536 bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot)
537 {
538 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
539 size_t left;
540
541 if (sc->dmamap_seg_count != 0) {
542 device_printf(sc->sc_dev, "DMA in use\n");
543 return;
544 }
545
546 left = min(BCM_SDHCI_BUFFER_SIZE,
547 slot->curcmd->data->len - slot->offset);
548
549 KASSERT((left & 3) == 0,
550 ("%s: len = %d, not word-aligned", __func__, left));
551
552 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
553 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
554 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
555 sc->dmamap_status != 0) {
556 slot->curcmd->error = MMC_ERR_NO_MEMORY;
557 return;
558 }
559
560 /* DMA start */
561 bcm_sdhci_start_dma_seg(sc);
562 }
563
564 static void
bcm_sdhci_write_dma(device_t dev,struct sdhci_slot * slot)565 bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot)
566 {
567 struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
568 size_t left;
569
570 if (sc->dmamap_seg_count != 0) {
571 device_printf(sc->sc_dev, "DMA in use\n");
572 return;
573 }
574
575 left = min(BCM_SDHCI_BUFFER_SIZE,
576 slot->curcmd->data->len - slot->offset);
577
578 KASSERT((left & 3) == 0,
579 ("%s: len = %d, not word-aligned", __func__, left));
580
581 if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
582 (uint8_t *)slot->curcmd->data->data + slot->offset, left,
583 bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
584 sc->dmamap_status != 0) {
585 slot->curcmd->error = MMC_ERR_NO_MEMORY;
586 return;
587 }
588
589 /* DMA start */
590 bcm_sdhci_start_dma_seg(sc);
591 }
592
593 static int
bcm_sdhci_will_handle_transfer(device_t dev,struct sdhci_slot * slot)594 bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
595 {
596 size_t left;
597
598 /*
599 * Do not use DMA for transfers less than block size or with a length
600 * that is not a multiple of four.
601 */
602 left = min(BCM_DMA_BLOCK_SIZE,
603 slot->curcmd->data->len - slot->offset);
604 if (left < BCM_DMA_BLOCK_SIZE)
605 return (0);
606 if (left & 0x03)
607 return (0);
608
609 return (1);
610 }
611
612 static void
bcm_sdhci_start_transfer(device_t dev,struct sdhci_slot * slot,uint32_t * intmask)613 bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
614 uint32_t *intmask)
615 {
616
617 /* DMA transfer FIFO 1KB */
618 if (slot->curcmd->data->flags & MMC_DATA_READ)
619 bcm_sdhci_read_dma(dev, slot);
620 else
621 bcm_sdhci_write_dma(dev, slot);
622 }
623
624 static void
bcm_sdhci_finish_transfer(device_t dev,struct sdhci_slot * slot)625 bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
626 {
627
628 sdhci_finish_data(slot);
629 }
630
631 static device_method_t bcm_sdhci_methods[] = {
632 /* Device interface */
633 DEVMETHOD(device_probe, bcm_sdhci_probe),
634 DEVMETHOD(device_attach, bcm_sdhci_attach),
635 DEVMETHOD(device_detach, bcm_sdhci_detach),
636
637 /* Bus interface */
638 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
639 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
640 DEVMETHOD(bus_print_child, bus_generic_print_child),
641
642 /* MMC bridge interface */
643 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
644 DEVMETHOD(mmcbr_request, sdhci_generic_request),
645 DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
646 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
647 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
648
649 /* Platform transfer methods */
650 DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
651 DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
652 DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
653 /* SDHCI registers accessors */
654 DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
655 DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
656 DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
657 DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
658 DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
659 DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
660 DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
661 DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
662
663 { 0, 0 }
664 };
665
666 static devclass_t bcm_sdhci_devclass;
667
668 static driver_t bcm_sdhci_driver = {
669 "sdhci_bcm",
670 bcm_sdhci_methods,
671 sizeof(struct bcm_sdhci_softc),
672 };
673
674 DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, 0, 0);
675 MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1);
676