1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 #include <stdio.h>
24 #include "sysdep.h"
25 #include "opcode/ppc.h"
26 #include "opintl.h"
27
28 /* This file holds the PowerPC opcode table. The opcode table
29 includes almost all of the extended instruction mnemonics. This
30 permits the disassembler to use them, and simplifies the assembler
31 logic, at the cost of increasing the table size. The table is
32 strictly constant data, so the compiler should be able to put it in
33 the .text section.
34
35 This file also holds the operand table. All knowledge about
36 inserting operands into instructions and vice-versa is kept in this
37 file. */
38
39 /* Local insertion and extraction functions. */
40
41 static unsigned long insert_bat (unsigned long, long, int, const char **);
42 static long extract_bat (unsigned long, int, int *);
43 static unsigned long insert_bba (unsigned long, long, int, const char **);
44 static long extract_bba (unsigned long, int, int *);
45 static unsigned long insert_bdm (unsigned long, long, int, const char **);
46 static long extract_bdm (unsigned long, int, int *);
47 static unsigned long insert_bdp (unsigned long, long, int, const char **);
48 static long extract_bdp (unsigned long, int, int *);
49 static unsigned long insert_bo (unsigned long, long, int, const char **);
50 static long extract_bo (unsigned long, int, int *);
51 static unsigned long insert_boe (unsigned long, long, int, const char **);
52 static long extract_boe (unsigned long, int, int *);
53 static unsigned long insert_fxm (unsigned long, long, int, const char **);
54 static long extract_fxm (unsigned long, int, int *);
55 static unsigned long insert_mbe (unsigned long, long, int, const char **);
56 static long extract_mbe (unsigned long, int, int *);
57 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
58 static long extract_mb6 (unsigned long, int, int *);
59 static long extract_nb (unsigned long, int, int *);
60 static unsigned long insert_nsi (unsigned long, long, int, const char **);
61 static long extract_nsi (unsigned long, int, int *);
62 static unsigned long insert_ral (unsigned long, long, int, const char **);
63 static unsigned long insert_ram (unsigned long, long, int, const char **);
64 static unsigned long insert_raq (unsigned long, long, int, const char **);
65 static unsigned long insert_ras (unsigned long, long, int, const char **);
66 static unsigned long insert_rbs (unsigned long, long, int, const char **);
67 static long extract_rbs (unsigned long, int, int *);
68 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
69 static long extract_sh6 (unsigned long, int, int *);
70 static unsigned long insert_spr (unsigned long, long, int, const char **);
71 static long extract_spr (unsigned long, int, int *);
72 static unsigned long insert_sprg (unsigned long, long, int, const char **);
73 static long extract_sprg (unsigned long, int, int *);
74 static unsigned long insert_tbr (unsigned long, long, int, const char **);
75 static long extract_tbr (unsigned long, int, int *);
76
77 /* The operands table.
78
79 The fields are bitm, shift, insert, extract, flags.
80
81 We used to put parens around the various additions, like the one
82 for BA just below. However, that caused trouble with feeble
83 compilers with a limit on depth of a parenthesized expression, like
84 (reportedly) the compiler in Microsoft Developer Studio 5. So we
85 omit the parens, since the macros are never used in a context where
86 the addition will be ambiguous. */
87
88 const struct powerpc_operand powerpc_operands[] =
89 {
90 /* The zero index is used to indicate the end of the list of
91 operands. */
92 #define UNUSED 0
93 { 0, 0, NULL, NULL, 0 },
94
95 /* The BA field in an XL form instruction. */
96 #define BA UNUSED + 1
97 /* The BI field in a B form or XL form instruction. */
98 #define BI BA
99 #define BI_MASK (0x1f << 16)
100 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
101
102 /* The BA field in an XL form instruction when it must be the same
103 as the BT field in the same instruction. */
104 #define BAT BA + 1
105 { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
106
107 /* The BB field in an XL form instruction. */
108 #define BB BAT + 1
109 #define BB_MASK (0x1f << 11)
110 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
111
112 /* The BB field in an XL form instruction when it must be the same
113 as the BA field in the same instruction. */
114 #define BBA BB + 1
115 { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
116
117 /* The BD field in a B form instruction. The lower two bits are
118 forced to zero. */
119 #define BD BBA + 1
120 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
121
122 /* The BD field in a B form instruction when absolute addressing is
123 used. */
124 #define BDA BD + 1
125 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
126
127 /* The BD field in a B form instruction when the - modifier is used.
128 This sets the y bit of the BO field appropriately. */
129 #define BDM BDA + 1
130 { 0xfffc, 0, insert_bdm, extract_bdm,
131 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
132
133 /* The BD field in a B form instruction when the - modifier is used
134 and absolute address is used. */
135 #define BDMA BDM + 1
136 { 0xfffc, 0, insert_bdm, extract_bdm,
137 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
138
139 /* The BD field in a B form instruction when the + modifier is used.
140 This sets the y bit of the BO field appropriately. */
141 #define BDP BDMA + 1
142 { 0xfffc, 0, insert_bdp, extract_bdp,
143 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
144
145 /* The BD field in a B form instruction when the + modifier is used
146 and absolute addressing is used. */
147 #define BDPA BDP + 1
148 { 0xfffc, 0, insert_bdp, extract_bdp,
149 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
150
151 /* The BF field in an X or XL form instruction. */
152 #define BF BDPA + 1
153 /* The CRFD field in an X form instruction. */
154 #define CRFD BF
155 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
156
157 /* The BF field in an X or XL form instruction. */
158 #define BFF BF + 1
159 { 0x7, 23, NULL, NULL, 0 },
160
161 /* An optional BF field. This is used for comparison instructions,
162 in which an omitted BF field is taken as zero. */
163 #define OBF BFF + 1
164 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
165
166 /* The BFA field in an X or XL form instruction. */
167 #define BFA OBF + 1
168 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
169
170 /* The BO field in a B form instruction. Certain values are
171 illegal. */
172 #define BO BFA + 1
173 #define BO_MASK (0x1f << 21)
174 { 0x1f, 21, insert_bo, extract_bo, 0 },
175
176 /* The BO field in a B form instruction when the + or - modifier is
177 used. This is like the BO field, but it must be even. */
178 #define BOE BO + 1
179 { 0x1e, 21, insert_boe, extract_boe, 0 },
180
181 #define BH BOE + 1
182 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
183
184 /* The BT field in an X or XL form instruction. */
185 #define BT BH + 1
186 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
187
188 /* The condition register number portion of the BI field in a B form
189 or XL form instruction. This is used for the extended
190 conditional branch mnemonics, which set the lower two bits of the
191 BI field. This field is optional. */
192 #define CR BT + 1
193 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
194
195 /* The CRB field in an X form instruction. */
196 #define CRB CR + 1
197 /* The MB field in an M form instruction. */
198 #define MB CRB
199 #define MB_MASK (0x1f << 6)
200 { 0x1f, 6, NULL, NULL, 0 },
201
202 /* The CRFS field in an X form instruction. */
203 #define CRFS CRB + 1
204 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
205
206 /* The CT field in an X form instruction. */
207 #define CT CRFS + 1
208 /* The MO field in an mbar instruction. */
209 #define MO CT
210 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
211
212 /* The D field in a D form instruction. This is a displacement off
213 a register, and implies that the next operand is a register in
214 parentheses. */
215 #define D CT + 1
216 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
217
218 /* The DE field in a DE form instruction. This is like D, but is 12
219 bits only. */
220 #define DE D + 1
221 { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
222
223 /* The DES field in a DES form instruction. This is like DS, but is 14
224 bits only (12 stored.) */
225 #define DES DE + 1
226 { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
227
228 /* The DQ field in a DQ form instruction. This is like D, but the
229 lower four bits are forced to zero. */
230 #define DQ DES + 1
231 { 0xfff0, 0, NULL, NULL,
232 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
233
234 /* The DS field in a DS form instruction. This is like D, but the
235 lower two bits are forced to zero. */
236 #define DS DQ + 1
237 { 0xfffc, 0, NULL, NULL,
238 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
239
240 /* The E field in a wrteei instruction. */
241 #define E DS + 1
242 { 0x1, 15, NULL, NULL, 0 },
243
244 /* The FL1 field in a POWER SC form instruction. */
245 #define FL1 E + 1
246 /* The U field in an X form instruction. */
247 #define U FL1
248 { 0xf, 12, NULL, NULL, 0 },
249
250 /* The FL2 field in a POWER SC form instruction. */
251 #define FL2 FL1 + 1
252 { 0x7, 2, NULL, NULL, 0 },
253
254 /* The FLM field in an XFL form instruction. */
255 #define FLM FL2 + 1
256 { 0xff, 17, NULL, NULL, 0 },
257
258 /* The FRA field in an X or A form instruction. */
259 #define FRA FLM + 1
260 #define FRA_MASK (0x1f << 16)
261 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
262
263 /* The FRB field in an X or A form instruction. */
264 #define FRB FRA + 1
265 #define FRB_MASK (0x1f << 11)
266 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
267
268 /* The FRC field in an A form instruction. */
269 #define FRC FRB + 1
270 #define FRC_MASK (0x1f << 6)
271 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
272
273 /* The FRS field in an X form instruction or the FRT field in a D, X
274 or A form instruction. */
275 #define FRS FRC + 1
276 #define FRT FRS
277 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
278
279 /* The FXM field in an XFX instruction. */
280 #define FXM FRS + 1
281 { 0xff, 12, insert_fxm, extract_fxm, 0 },
282
283 /* Power4 version for mfcr. */
284 #define FXM4 FXM + 1
285 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
286
287 /* The L field in a D or X form instruction. */
288 #define L FXM4 + 1
289 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
290
291 /* The LEV field in a POWER SVC form instruction. */
292 #define SVC_LEV L + 1
293 { 0x7f, 5, NULL, NULL, 0 },
294
295 /* The LEV field in an SC form instruction. */
296 #define LEV SVC_LEV + 1
297 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
298
299 /* The LI field in an I form instruction. The lower two bits are
300 forced to zero. */
301 #define LI LEV + 1
302 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
303
304 /* The LI field in an I form instruction when used as an absolute
305 address. */
306 #define LIA LI + 1
307 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
308
309 /* The LS field in an X (sync) form instruction. */
310 #define LS LIA + 1
311 { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
312
313 /* The ME field in an M form instruction. */
314 #define ME LS + 1
315 #define ME_MASK (0x1f << 1)
316 { 0x1f, 1, NULL, NULL, 0 },
317
318 /* The MB and ME fields in an M form instruction expressed a single
319 operand which is a bitmask indicating which bits to select. This
320 is a two operand form using PPC_OPERAND_NEXT. See the
321 description in opcode/ppc.h for what this means. */
322 #define MBE ME + 1
323 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
324 { -1, 0, insert_mbe, extract_mbe, 0 },
325
326 /* The MB or ME field in an MD or MDS form instruction. The high
327 bit is wrapped to the low end. */
328 #define MB6 MBE + 2
329 #define ME6 MB6
330 #define MB6_MASK (0x3f << 5)
331 { 0x3f, 5, insert_mb6, extract_mb6, 0 },
332
333 /* The NB field in an X form instruction. The value 32 is stored as
334 0. */
335 #define NB MB6 + 1
336 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
337
338 /* The NSI field in a D form instruction. This is the same as the
339 SI field, only negated. */
340 #define NSI NB + 1
341 { 0xffff, 0, insert_nsi, extract_nsi,
342 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
343
344 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
345 #define RA NSI + 1
346 #define RA_MASK (0x1f << 16)
347 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
348
349 /* As above, but 0 in the RA field means zero, not r0. */
350 #define RA0 RA + 1
351 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
352
353 /* The RA field in the DQ form lq instruction, which has special
354 value restrictions. */
355 #define RAQ RA0 + 1
356 { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
357
358 /* The RA field in a D or X form instruction which is an updating
359 load, which means that the RA field may not be zero and may not
360 equal the RT field. */
361 #define RAL RAQ + 1
362 { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
363
364 /* The RA field in an lmw instruction, which has special value
365 restrictions. */
366 #define RAM RAL + 1
367 { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
368
369 /* The RA field in a D or X form instruction which is an updating
370 store or an updating floating point load, which means that the RA
371 field may not be zero. */
372 #define RAS RAM + 1
373 { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
374
375 /* The RA field of the tlbwe instruction, which is optional. */
376 #define RAOPT RAS + 1
377 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
378
379 /* The RB field in an X, XO, M, or MDS form instruction. */
380 #define RB RAOPT + 1
381 #define RB_MASK (0x1f << 11)
382 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
383
384 /* The RB field in an X form instruction when it must be the same as
385 the RS field in the instruction. This is used for extended
386 mnemonics like mr. */
387 #define RBS RB + 1
388 { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
389
390 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
391 instruction or the RT field in a D, DS, X, XFX or XO form
392 instruction. */
393 #define RS RBS + 1
394 #define RT RS
395 #define RT_MASK (0x1f << 21)
396 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
397
398 /* The RS and RT fields of the DS form stq instruction, which have
399 special value restrictions. */
400 #define RSQ RS + 1
401 #define RTQ RSQ
402 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
403
404 /* The RS field of the tlbwe instruction, which is optional. */
405 #define RSO RSQ + 1
406 #define RTO RSO
407 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
408
409 /* The SH field in an X or M form instruction. */
410 #define SH RSO + 1
411 #define SH_MASK (0x1f << 11)
412 /* The other UIMM field in a EVX form instruction. */
413 #define EVUIMM SH
414 { 0x1f, 11, NULL, NULL, 0 },
415
416 /* The SH field in an MD form instruction. This is split. */
417 #define SH6 SH + 1
418 #define SH6_MASK ((0x1f << 11) | (1 << 1))
419 { 0x3f, -1, insert_sh6, extract_sh6, 0 },
420
421 /* The SH field of the tlbwe instruction, which is optional. */
422 #define SHO SH6 + 1
423 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
424
425 /* The SI field in a D form instruction. */
426 #define SI SHO + 1
427 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
428
429 /* The SI field in a D form instruction when we accept a wide range
430 of positive values. */
431 #define SISIGNOPT SI + 1
432 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
433
434 /* The SPR field in an XFX form instruction. This is flipped--the
435 lower 5 bits are stored in the upper 5 and vice- versa. */
436 #define SPR SISIGNOPT + 1
437 #define PMR SPR
438 #define SPR_MASK (0x3ff << 11)
439 { 0x3ff, 11, insert_spr, extract_spr, 0 },
440
441 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
442 #define SPRBAT SPR + 1
443 #define SPRBAT_MASK (0x3 << 17)
444 { 0x3, 17, NULL, NULL, 0 },
445
446 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
447 #define SPRG SPRBAT + 1
448 { 0x1f, 16, insert_sprg, extract_sprg, 0 },
449
450 /* The SR field in an X form instruction. */
451 #define SR SPRG + 1
452 { 0xf, 16, NULL, NULL, 0 },
453
454 /* The STRM field in an X AltiVec form instruction. */
455 #define STRM SR + 1
456 { 0x3, 21, NULL, NULL, 0 },
457
458 /* The SV field in a POWER SC form instruction. */
459 #define SV STRM + 1
460 { 0x3fff, 2, NULL, NULL, 0 },
461
462 /* The TBR field in an XFX form instruction. This is like the SPR
463 field, but it is optional. */
464 #define TBR SV + 1
465 { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
466
467 /* The TO field in a D or X form instruction. */
468 #define TO TBR + 1
469 #define TO_MASK (0x1f << 21)
470 { 0x1f, 21, NULL, NULL, 0 },
471
472 /* The UI field in a D form instruction. */
473 #define UI TO + 1
474 { 0xffff, 0, NULL, NULL, 0 },
475
476 /* The VA field in a VA, VX or VXR form instruction. */
477 #define VA UI + 1
478 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
479
480 /* The VB field in a VA, VX or VXR form instruction. */
481 #define VB VA + 1
482 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
483
484 /* The VC field in a VA form instruction. */
485 #define VC VB + 1
486 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
487
488 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
489 #define VD VC + 1
490 #define VS VD
491 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
492
493 /* The SIMM field in a VX form instruction. */
494 #define SIMM VD + 1
495 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
496
497 /* The UIMM field in a VX form instruction, and TE in Z form. */
498 #define UIMM SIMM + 1
499 #define TE UIMM
500 { 0x1f, 16, NULL, NULL, 0 },
501
502 /* The SHB field in a VA form instruction. */
503 #define SHB UIMM + 1
504 { 0xf, 6, NULL, NULL, 0 },
505
506 /* The other UIMM field in a half word EVX form instruction. */
507 #define EVUIMM_2 SHB + 1
508 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
509
510 /* The other UIMM field in a word EVX form instruction. */
511 #define EVUIMM_4 EVUIMM_2 + 1
512 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
513
514 /* The other UIMM field in a double EVX form instruction. */
515 #define EVUIMM_8 EVUIMM_4 + 1
516 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
517
518 /* The WS field. */
519 #define WS EVUIMM_8 + 1
520 { 0x7, 11, NULL, NULL, 0 },
521
522 /* The L field in an mtmsrd or A form instruction or W in an X form. */
523 #define A_L WS + 1
524 #define W A_L
525 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
526
527 #define RMC A_L + 1
528 { 0x3, 9, NULL, NULL, 0 },
529
530 #define R RMC + 1
531 { 0x1, 16, NULL, NULL, 0 },
532
533 #define SP R + 1
534 { 0x3, 19, NULL, NULL, 0 },
535
536 #define S SP + 1
537 { 0x1, 20, NULL, NULL, 0 },
538
539 /* SH field starting at bit position 16. */
540 #define SH16 S + 1
541 /* The DCM and DGM fields in a Z form instruction. */
542 #define DCM SH16
543 #define DGM DCM
544 { 0x3f, 10, NULL, NULL, 0 },
545
546 /* The EH field in larx instruction. */
547 #define EH SH16 + 1
548 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
549
550 /* The L field in an mtfsf or XFL form instruction. */
551 #define XFL_L EH + 1
552 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
553 };
554
555 const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
556 / sizeof (powerpc_operands[0]));
557
558 /* The functions used to insert and extract complicated operands. */
559
560 /* The BA field in an XL form instruction when it must be the same as
561 the BT field in the same instruction. This operand is marked FAKE.
562 The insertion function just copies the BT field into the BA field,
563 and the extraction function just checks that the fields are the
564 same. */
565
566 static unsigned long
insert_bat(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)567 insert_bat (unsigned long insn,
568 long value ATTRIBUTE_UNUSED,
569 int dialect ATTRIBUTE_UNUSED,
570 const char **errmsg ATTRIBUTE_UNUSED)
571 {
572 return insn | (((insn >> 21) & 0x1f) << 16);
573 }
574
575 static long
extract_bat(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)576 extract_bat (unsigned long insn,
577 int dialect ATTRIBUTE_UNUSED,
578 int *invalid)
579 {
580 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
581 *invalid = 1;
582 return 0;
583 }
584
585 /* The BB field in an XL form instruction when it must be the same as
586 the BA field in the same instruction. This operand is marked FAKE.
587 The insertion function just copies the BA field into the BB field,
588 and the extraction function just checks that the fields are the
589 same. */
590
591 static unsigned long
insert_bba(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)592 insert_bba (unsigned long insn,
593 long value ATTRIBUTE_UNUSED,
594 int dialect ATTRIBUTE_UNUSED,
595 const char **errmsg ATTRIBUTE_UNUSED)
596 {
597 return insn | (((insn >> 16) & 0x1f) << 11);
598 }
599
600 static long
extract_bba(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)601 extract_bba (unsigned long insn,
602 int dialect ATTRIBUTE_UNUSED,
603 int *invalid)
604 {
605 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
606 *invalid = 1;
607 return 0;
608 }
609
610 /* The BD field in a B form instruction when the - modifier is used.
611 This modifier means that the branch is not expected to be taken.
612 For chips built to versions of the architecture prior to version 2
613 (ie. not Power4 compatible), we set the y bit of the BO field to 1
614 if the offset is negative. When extracting, we require that the y
615 bit be 1 and that the offset be positive, since if the y bit is 0
616 we just want to print the normal form of the instruction.
617 Power4 compatible targets use two bits, "a", and "t", instead of
618 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
619 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
620 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
621 for branch on CTR. We only handle the taken/not-taken hint here.
622 Note that we don't relax the conditions tested here when
623 disassembling with -Many because insns using extract_bdm and
624 extract_bdp always occur in pairs. One or the other will always
625 be valid. */
626
627 static unsigned long
insert_bdm(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)628 insert_bdm (unsigned long insn,
629 long value,
630 int dialect,
631 const char **errmsg ATTRIBUTE_UNUSED)
632 {
633 if ((dialect & PPC_OPCODE_POWER4) == 0)
634 {
635 if ((value & 0x8000) != 0)
636 insn |= 1 << 21;
637 }
638 else
639 {
640 if ((insn & (0x14 << 21)) == (0x04 << 21))
641 insn |= 0x02 << 21;
642 else if ((insn & (0x14 << 21)) == (0x10 << 21))
643 insn |= 0x08 << 21;
644 }
645 return insn | (value & 0xfffc);
646 }
647
648 static long
extract_bdm(unsigned long insn,int dialect,int * invalid)649 extract_bdm (unsigned long insn,
650 int dialect,
651 int *invalid)
652 {
653 if ((dialect & PPC_OPCODE_POWER4) == 0)
654 {
655 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
656 *invalid = 1;
657 }
658 else
659 {
660 if ((insn & (0x17 << 21)) != (0x06 << 21)
661 && (insn & (0x1d << 21)) != (0x18 << 21))
662 *invalid = 1;
663 }
664
665 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
666 }
667
668 /* The BD field in a B form instruction when the + modifier is used.
669 This is like BDM, above, except that the branch is expected to be
670 taken. */
671
672 static unsigned long
insert_bdp(unsigned long insn,long value,int dialect,const char ** errmsg ATTRIBUTE_UNUSED)673 insert_bdp (unsigned long insn,
674 long value,
675 int dialect,
676 const char **errmsg ATTRIBUTE_UNUSED)
677 {
678 if ((dialect & PPC_OPCODE_POWER4) == 0)
679 {
680 if ((value & 0x8000) == 0)
681 insn |= 1 << 21;
682 }
683 else
684 {
685 if ((insn & (0x14 << 21)) == (0x04 << 21))
686 insn |= 0x03 << 21;
687 else if ((insn & (0x14 << 21)) == (0x10 << 21))
688 insn |= 0x09 << 21;
689 }
690 return insn | (value & 0xfffc);
691 }
692
693 static long
extract_bdp(unsigned long insn,int dialect,int * invalid)694 extract_bdp (unsigned long insn,
695 int dialect,
696 int *invalid)
697 {
698 if ((dialect & PPC_OPCODE_POWER4) == 0)
699 {
700 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
701 *invalid = 1;
702 }
703 else
704 {
705 if ((insn & (0x17 << 21)) != (0x07 << 21)
706 && (insn & (0x1d << 21)) != (0x19 << 21))
707 *invalid = 1;
708 }
709
710 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
711 }
712
713 /* Check for legal values of a BO field. */
714
715 static int
valid_bo(long value,int dialect,int extract)716 valid_bo (long value, int dialect, int extract)
717 {
718 if ((dialect & PPC_OPCODE_POWER4) == 0)
719 {
720 int valid;
721 /* Certain encodings have bits that are required to be zero.
722 These are (z must be zero, y may be anything):
723 001zy
724 011zy
725 1z00y
726 1z01y
727 1z1zz
728 */
729 switch (value & 0x14)
730 {
731 default:
732 case 0:
733 valid = 1;
734 break;
735 case 0x4:
736 valid = (value & 0x2) == 0;
737 break;
738 case 0x10:
739 valid = (value & 0x8) == 0;
740 break;
741 case 0x14:
742 valid = value == 0x14;
743 break;
744 }
745 /* When disassembling with -Many, accept power4 encodings too. */
746 if (valid
747 || (dialect & PPC_OPCODE_ANY) == 0
748 || !extract)
749 return valid;
750 }
751
752 /* Certain encodings have bits that are required to be zero.
753 These are (z must be zero, a & t may be anything):
754 0000z
755 0001z
756 0100z
757 0101z
758 001at
759 011at
760 1a00t
761 1a01t
762 1z1zz
763 */
764 if ((value & 0x14) == 0)
765 return (value & 0x1) == 0;
766 else if ((value & 0x14) == 0x14)
767 return value == 0x14;
768 else
769 return 1;
770 }
771
772 /* The BO field in a B form instruction. Warn about attempts to set
773 the field to an illegal value. */
774
775 static unsigned long
insert_bo(unsigned long insn,long value,int dialect,const char ** errmsg)776 insert_bo (unsigned long insn,
777 long value,
778 int dialect,
779 const char **errmsg)
780 {
781 if (!valid_bo (value, dialect, 0))
782 *errmsg = _("invalid conditional option");
783 return insn | ((value & 0x1f) << 21);
784 }
785
786 static long
extract_bo(unsigned long insn,int dialect,int * invalid)787 extract_bo (unsigned long insn,
788 int dialect,
789 int *invalid)
790 {
791 long value;
792
793 value = (insn >> 21) & 0x1f;
794 if (!valid_bo (value, dialect, 1))
795 *invalid = 1;
796 return value;
797 }
798
799 /* The BO field in a B form instruction when the + or - modifier is
800 used. This is like the BO field, but it must be even. When
801 extracting it, we force it to be even. */
802
803 static unsigned long
insert_boe(unsigned long insn,long value,int dialect,const char ** errmsg)804 insert_boe (unsigned long insn,
805 long value,
806 int dialect,
807 const char **errmsg)
808 {
809 if (!valid_bo (value, dialect, 0))
810 *errmsg = _("invalid conditional option");
811 else if ((value & 1) != 0)
812 *errmsg = _("attempt to set y bit when using + or - modifier");
813
814 return insn | ((value & 0x1f) << 21);
815 }
816
817 static long
extract_boe(unsigned long insn,int dialect,int * invalid)818 extract_boe (unsigned long insn,
819 int dialect,
820 int *invalid)
821 {
822 long value;
823
824 value = (insn >> 21) & 0x1f;
825 if (!valid_bo (value, dialect, 1))
826 *invalid = 1;
827 return value & 0x1e;
828 }
829
830 /* FXM mask in mfcr and mtcrf instructions. */
831
832 static unsigned long
insert_fxm(unsigned long insn,long value,int dialect,const char ** errmsg)833 insert_fxm (unsigned long insn,
834 long value,
835 int dialect,
836 const char **errmsg)
837 {
838 /* If we're handling the mfocrf and mtocrf insns ensure that exactly
839 one bit of the mask field is set. */
840 if ((insn & (1 << 20)) != 0)
841 {
842 if (value == 0 || (value & -value) != value)
843 {
844 *errmsg = _("invalid mask field");
845 value = 0;
846 }
847 }
848
849 /* If the optional field on mfcr is missing that means we want to use
850 the old form of the instruction that moves the whole cr. In that
851 case we'll have VALUE zero. There doesn't seem to be a way to
852 distinguish this from the case where someone writes mfcr %r3,0. */
853 else if (value == 0)
854 ;
855
856 /* If only one bit of the FXM field is set, we can use the new form
857 of the instruction, which is faster. Unlike the Power4 branch hint
858 encoding, this is not backward compatible. Do not generate the
859 new form unless -mpower4 has been given, or -many and the two
860 operand form of mfcr was used. */
861 else if ((value & -value) == value
862 && ((dialect & PPC_OPCODE_POWER4) != 0
863 || ((dialect & PPC_OPCODE_ANY) != 0
864 && (insn & (0x3ff << 1)) == 19 << 1)))
865 insn |= 1 << 20;
866
867 /* Any other value on mfcr is an error. */
868 else if ((insn & (0x3ff << 1)) == 19 << 1)
869 {
870 *errmsg = _("ignoring invalid mfcr mask");
871 value = 0;
872 }
873
874 return insn | ((value & 0xff) << 12);
875 }
876
877 static long
extract_fxm(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)878 extract_fxm (unsigned long insn,
879 int dialect ATTRIBUTE_UNUSED,
880 int *invalid)
881 {
882 long mask = (insn >> 12) & 0xff;
883
884 /* Is this a Power4 insn? */
885 if ((insn & (1 << 20)) != 0)
886 {
887 /* Exactly one bit of MASK should be set. */
888 if (mask == 0 || (mask & -mask) != mask)
889 *invalid = 1;
890 }
891
892 /* Check that non-power4 form of mfcr has a zero MASK. */
893 else if ((insn & (0x3ff << 1)) == 19 << 1)
894 {
895 if (mask != 0)
896 *invalid = 1;
897 }
898
899 return mask;
900 }
901
902 /* The MB and ME fields in an M form instruction expressed as a single
903 operand which is itself a bitmask. The extraction function always
904 marks it as invalid, since we never want to recognize an
905 instruction which uses a field of this type. */
906
907 static unsigned long
insert_mbe(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)908 insert_mbe (unsigned long insn,
909 long value,
910 int dialect ATTRIBUTE_UNUSED,
911 const char **errmsg)
912 {
913 unsigned long uval, mask;
914 int mb, me, mx, count, last;
915
916 uval = value;
917
918 if (uval == 0)
919 {
920 *errmsg = _("illegal bitmask");
921 return insn;
922 }
923
924 mb = 0;
925 me = 32;
926 if ((uval & 1) != 0)
927 last = 1;
928 else
929 last = 0;
930 count = 0;
931
932 /* mb: location of last 0->1 transition */
933 /* me: location of last 1->0 transition */
934 /* count: # transitions */
935
936 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
937 {
938 if ((uval & mask) && !last)
939 {
940 ++count;
941 mb = mx;
942 last = 1;
943 }
944 else if (!(uval & mask) && last)
945 {
946 ++count;
947 me = mx;
948 last = 0;
949 }
950 }
951 if (me == 0)
952 me = 32;
953
954 if (count != 2 && (count != 0 || ! last))
955 *errmsg = _("illegal bitmask");
956
957 return insn | (mb << 6) | ((me - 1) << 1);
958 }
959
960 static long
extract_mbe(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)961 extract_mbe (unsigned long insn,
962 int dialect ATTRIBUTE_UNUSED,
963 int *invalid)
964 {
965 long ret;
966 int mb, me;
967 int i;
968
969 *invalid = 1;
970
971 mb = (insn >> 6) & 0x1f;
972 me = (insn >> 1) & 0x1f;
973 if (mb < me + 1)
974 {
975 ret = 0;
976 for (i = mb; i <= me; i++)
977 ret |= 1L << (31 - i);
978 }
979 else if (mb == me + 1)
980 ret = ~0;
981 else /* (mb > me + 1) */
982 {
983 ret = ~0;
984 for (i = me + 1; i < mb; i++)
985 ret &= ~(1L << (31 - i));
986 }
987 return ret;
988 }
989
990 /* The MB or ME field in an MD or MDS form instruction. The high bit
991 is wrapped to the low end. */
992
993 static unsigned long
insert_mb6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)994 insert_mb6 (unsigned long insn,
995 long value,
996 int dialect ATTRIBUTE_UNUSED,
997 const char **errmsg ATTRIBUTE_UNUSED)
998 {
999 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1000 }
1001
1002 static long
extract_mb6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1003 extract_mb6 (unsigned long insn,
1004 int dialect ATTRIBUTE_UNUSED,
1005 int *invalid ATTRIBUTE_UNUSED)
1006 {
1007 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1008 }
1009
1010 /* The NB field in an X form instruction. The value 32 is stored as
1011 0. */
1012
1013 static long
extract_nb(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1014 extract_nb (unsigned long insn,
1015 int dialect ATTRIBUTE_UNUSED,
1016 int *invalid ATTRIBUTE_UNUSED)
1017 {
1018 long ret;
1019
1020 ret = (insn >> 11) & 0x1f;
1021 if (ret == 0)
1022 ret = 32;
1023 return ret;
1024 }
1025
1026 /* The NSI field in a D form instruction. This is the same as the SI
1027 field, only negated. The extraction function always marks it as
1028 invalid, since we never want to recognize an instruction which uses
1029 a field of this type. */
1030
1031 static unsigned long
insert_nsi(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1032 insert_nsi (unsigned long insn,
1033 long value,
1034 int dialect ATTRIBUTE_UNUSED,
1035 const char **errmsg ATTRIBUTE_UNUSED)
1036 {
1037 return insn | (-value & 0xffff);
1038 }
1039
1040 static long
extract_nsi(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1041 extract_nsi (unsigned long insn,
1042 int dialect ATTRIBUTE_UNUSED,
1043 int *invalid)
1044 {
1045 *invalid = 1;
1046 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1047 }
1048
1049 /* The RA field in a D or X form instruction which is an updating
1050 load, which means that the RA field may not be zero and may not
1051 equal the RT field. */
1052
1053 static unsigned long
insert_ral(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1054 insert_ral (unsigned long insn,
1055 long value,
1056 int dialect ATTRIBUTE_UNUSED,
1057 const char **errmsg)
1058 {
1059 if (value == 0
1060 || (unsigned long) value == ((insn >> 21) & 0x1f))
1061 *errmsg = "invalid register operand when updating";
1062 return insn | ((value & 0x1f) << 16);
1063 }
1064
1065 /* The RA field in an lmw instruction, which has special value
1066 restrictions. */
1067
1068 static unsigned long
insert_ram(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1069 insert_ram (unsigned long insn,
1070 long value,
1071 int dialect ATTRIBUTE_UNUSED,
1072 const char **errmsg)
1073 {
1074 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1075 *errmsg = _("index register in load range");
1076 return insn | ((value & 0x1f) << 16);
1077 }
1078
1079 /* The RA field in the DQ form lq instruction, which has special
1080 value restrictions. */
1081
1082 static unsigned long
insert_raq(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1083 insert_raq (unsigned long insn,
1084 long value,
1085 int dialect ATTRIBUTE_UNUSED,
1086 const char **errmsg)
1087 {
1088 long rtvalue = (insn & RT_MASK) >> 21;
1089
1090 if (value == rtvalue)
1091 *errmsg = _("source and target register operands must be different");
1092 return insn | ((value & 0x1f) << 16);
1093 }
1094
1095 /* The RA field in a D or X form instruction which is an updating
1096 store or an updating floating point load, which means that the RA
1097 field may not be zero. */
1098
1099 static unsigned long
insert_ras(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg)1100 insert_ras (unsigned long insn,
1101 long value,
1102 int dialect ATTRIBUTE_UNUSED,
1103 const char **errmsg)
1104 {
1105 if (value == 0)
1106 *errmsg = _("invalid register operand when updating");
1107 return insn | ((value & 0x1f) << 16);
1108 }
1109
1110 /* The RB field in an X form instruction when it must be the same as
1111 the RS field in the instruction. This is used for extended
1112 mnemonics like mr. This operand is marked FAKE. The insertion
1113 function just copies the BT field into the BA field, and the
1114 extraction function just checks that the fields are the same. */
1115
1116 static unsigned long
insert_rbs(unsigned long insn,long value ATTRIBUTE_UNUSED,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1117 insert_rbs (unsigned long insn,
1118 long value ATTRIBUTE_UNUSED,
1119 int dialect ATTRIBUTE_UNUSED,
1120 const char **errmsg ATTRIBUTE_UNUSED)
1121 {
1122 return insn | (((insn >> 21) & 0x1f) << 11);
1123 }
1124
1125 static long
extract_rbs(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid)1126 extract_rbs (unsigned long insn,
1127 int dialect ATTRIBUTE_UNUSED,
1128 int *invalid)
1129 {
1130 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1131 *invalid = 1;
1132 return 0;
1133 }
1134
1135 /* The SH field in an MD form instruction. This is split. */
1136
1137 static unsigned long
insert_sh6(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1138 insert_sh6 (unsigned long insn,
1139 long value,
1140 int dialect ATTRIBUTE_UNUSED,
1141 const char **errmsg ATTRIBUTE_UNUSED)
1142 {
1143 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1144 }
1145
1146 static long
extract_sh6(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1147 extract_sh6 (unsigned long insn,
1148 int dialect ATTRIBUTE_UNUSED,
1149 int *invalid ATTRIBUTE_UNUSED)
1150 {
1151 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1152 }
1153
1154 /* The SPR field in an XFX form instruction. This is flipped--the
1155 lower 5 bits are stored in the upper 5 and vice- versa. */
1156
1157 static unsigned long
insert_spr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1158 insert_spr (unsigned long insn,
1159 long value,
1160 int dialect ATTRIBUTE_UNUSED,
1161 const char **errmsg ATTRIBUTE_UNUSED)
1162 {
1163 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1164 }
1165
1166 static long
extract_spr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1167 extract_spr (unsigned long insn,
1168 int dialect ATTRIBUTE_UNUSED,
1169 int *invalid ATTRIBUTE_UNUSED)
1170 {
1171 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1172 }
1173
1174 /* Some dialects have 8 SPRG registers instead of the standard 4. */
1175
1176 static unsigned long
insert_sprg(unsigned long insn,long value,int dialect,const char ** errmsg)1177 insert_sprg (unsigned long insn,
1178 long value,
1179 int dialect,
1180 const char **errmsg)
1181 {
1182 /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1183 as a synonym. If ever a 405 specific dialect is added this
1184 check should use that instead. */
1185 if (value > 7
1186 || (value > 3
1187 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1188 *errmsg = _("invalid sprg number");
1189
1190 /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1191 user mode. Anything else must use spr 272..279. */
1192 if (value <= 3 || (insn & 0x100) != 0)
1193 value |= 0x10;
1194
1195 return insn | ((value & 0x17) << 16);
1196 }
1197
1198 static long
extract_sprg(unsigned long insn,int dialect,int * invalid)1199 extract_sprg (unsigned long insn,
1200 int dialect,
1201 int *invalid)
1202 {
1203 unsigned long val = (insn >> 16) & 0x1f;
1204
1205 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279
1206 If not BOOKE or 405, then both use only 272..275. */
1207 if (val <= 3
1208 || (val < 0x10 && (insn & 0x100) != 0)
1209 || (val - 0x10 > 3
1210 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1211 *invalid = 1;
1212 return val & 7;
1213 }
1214
1215 /* The TBR field in an XFX instruction. This is just like SPR, but it
1216 is optional. When TBR is omitted, it must be inserted as 268 (the
1217 magic number of the TB register). These functions treat 0
1218 (indicating an omitted optional operand) as 268. This means that
1219 ``mftb 4,0'' is not handled correctly. This does not matter very
1220 much, since the architecture manual does not define mftb as
1221 accepting any values other than 268 or 269. */
1222
1223 #define TB (268)
1224
1225 static unsigned long
insert_tbr(unsigned long insn,long value,int dialect ATTRIBUTE_UNUSED,const char ** errmsg ATTRIBUTE_UNUSED)1226 insert_tbr (unsigned long insn,
1227 long value,
1228 int dialect ATTRIBUTE_UNUSED,
1229 const char **errmsg ATTRIBUTE_UNUSED)
1230 {
1231 if (value == 0)
1232 value = TB;
1233 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1234 }
1235
1236 static long
extract_tbr(unsigned long insn,int dialect ATTRIBUTE_UNUSED,int * invalid ATTRIBUTE_UNUSED)1237 extract_tbr (unsigned long insn,
1238 int dialect ATTRIBUTE_UNUSED,
1239 int *invalid ATTRIBUTE_UNUSED)
1240 {
1241 long ret;
1242
1243 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1244 if (ret == TB)
1245 ret = 0;
1246 return ret;
1247 }
1248
1249 /* Macros used to form opcodes. */
1250
1251 /* The main opcode. */
1252 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1253 #define OP_MASK OP (0x3f)
1254
1255 /* The main opcode combined with a trap code in the TO field of a D
1256 form instruction. Used for extended mnemonics for the trap
1257 instructions. */
1258 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1259 #define OPTO_MASK (OP_MASK | TO_MASK)
1260
1261 /* The main opcode combined with a comparison size bit in the L field
1262 of a D form or X form instruction. Used for extended mnemonics for
1263 the comparison instructions. */
1264 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1265 #define OPL_MASK OPL (0x3f,1)
1266
1267 /* An A form instruction. */
1268 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1269 #define A_MASK A (0x3f, 0x1f, 1)
1270
1271 /* An A_MASK with the FRB field fixed. */
1272 #define AFRB_MASK (A_MASK | FRB_MASK)
1273
1274 /* An A_MASK with the FRC field fixed. */
1275 #define AFRC_MASK (A_MASK | FRC_MASK)
1276
1277 /* An A_MASK with the FRA and FRC fields fixed. */
1278 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1279
1280 /* An AFRAFRC_MASK, but with L bit clear. */
1281 #define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1282
1283 /* A B form instruction. */
1284 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1285 #define B_MASK B (0x3f, 1, 1)
1286
1287 /* A B form instruction setting the BO field. */
1288 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1289 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1290
1291 /* A BBO_MASK with the y bit of the BO field removed. This permits
1292 matching a conditional branch regardless of the setting of the y
1293 bit. Similarly for the 'at' bits used for power4 branch hints. */
1294 #define Y_MASK (((unsigned long) 1) << 21)
1295 #define AT1_MASK (((unsigned long) 3) << 21)
1296 #define AT2_MASK (((unsigned long) 9) << 21)
1297 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1298 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1299
1300 /* A B form instruction setting the BO field and the condition bits of
1301 the BI field. */
1302 #define BBOCB(op, bo, cb, aa, lk) \
1303 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1304 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1305
1306 /* A BBOCB_MASK with the y bit of the BO field removed. */
1307 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1308 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1309 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1310
1311 /* A BBOYCB_MASK in which the BI field is fixed. */
1312 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1313 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1314
1315 /* An Context form instruction. */
1316 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1317 #define CTX_MASK CTX(0x3f, 0x7)
1318
1319 /* An User Context form instruction. */
1320 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1321 #define UCTX_MASK UCTX(0x3f, 0x1f)
1322
1323 /* The main opcode mask with the RA field clear. */
1324 #define DRA_MASK (OP_MASK | RA_MASK)
1325
1326 /* A DS form instruction. */
1327 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1328 #define DS_MASK DSO (0x3f, 3)
1329
1330 /* A DE form instruction. */
1331 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1332 #define DE_MASK DEO (0x3e, 0xf)
1333
1334 /* An EVSEL form instruction. */
1335 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1336 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1337
1338 /* An M form instruction. */
1339 #define M(op, rc) (OP (op) | ((rc) & 1))
1340 #define M_MASK M (0x3f, 1)
1341
1342 /* An M form instruction with the ME field specified. */
1343 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1344
1345 /* An M_MASK with the MB and ME fields fixed. */
1346 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1347
1348 /* An M_MASK with the SH and ME fields fixed. */
1349 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1350
1351 /* An MD form instruction. */
1352 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1353 #define MD_MASK MD (0x3f, 0x7, 1)
1354
1355 /* An MD_MASK with the MB field fixed. */
1356 #define MDMB_MASK (MD_MASK | MB6_MASK)
1357
1358 /* An MD_MASK with the SH field fixed. */
1359 #define MDSH_MASK (MD_MASK | SH6_MASK)
1360
1361 /* An MDS form instruction. */
1362 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1363 #define MDS_MASK MDS (0x3f, 0xf, 1)
1364
1365 /* An MDS_MASK with the MB field fixed. */
1366 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1367
1368 /* An SC form instruction. */
1369 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1370 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1371
1372 /* An VX form instruction. */
1373 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1374
1375 /* The mask for an VX form instruction. */
1376 #define VX_MASK VX(0x3f, 0x7ff)
1377
1378 /* An VA form instruction. */
1379 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1380
1381 /* The mask for an VA form instruction. */
1382 #define VXA_MASK VXA(0x3f, 0x3f)
1383
1384 /* An VXR form instruction. */
1385 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1386
1387 /* The mask for a VXR form instruction. */
1388 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1389
1390 /* An X form instruction. */
1391 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1392
1393 /* A Z form instruction. */
1394 #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1395
1396 /* An X form instruction with the RC bit specified. */
1397 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1398
1399 /* A Z form instruction with the RC bit specified. */
1400 #define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1401
1402 /* The mask for an X form instruction. */
1403 #define X_MASK XRC (0x3f, 0x3ff, 1)
1404
1405 /* The mask for a Z form instruction. */
1406 #define Z_MASK ZRC (0x3f, 0x1ff, 1)
1407 #define Z2_MASK ZRC (0x3f, 0xff, 1)
1408
1409 /* An X_MASK with the RA field fixed. */
1410 #define XRA_MASK (X_MASK | RA_MASK)
1411
1412 /* An XRA_MASK with the W field clear. */
1413 #define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1414
1415 /* An X_MASK with the RB field fixed. */
1416 #define XRB_MASK (X_MASK | RB_MASK)
1417
1418 /* An X_MASK with the RT field fixed. */
1419 #define XRT_MASK (X_MASK | RT_MASK)
1420
1421 /* An XRT_MASK mask with the L bits clear. */
1422 #define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1423
1424 /* An X_MASK with the RA and RB fields fixed. */
1425 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1426
1427 /* An XRARB_MASK, but with the L bit clear. */
1428 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1429
1430 /* An X_MASK with the RT and RA fields fixed. */
1431 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1432
1433 /* An XRTRA_MASK, but with L bit clear. */
1434 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1435
1436 /* An X form instruction with the L bit specified. */
1437 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1438
1439 /* The mask for an X form comparison instruction. */
1440 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1441
1442 /* The mask for an X form comparison instruction with the L field
1443 fixed. */
1444 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1445
1446 /* An X form trap instruction with the TO field specified. */
1447 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1448 #define XTO_MASK (X_MASK | TO_MASK)
1449
1450 /* An X form tlb instruction with the SH field specified. */
1451 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1452 #define XTLB_MASK (X_MASK | SH_MASK)
1453
1454 /* An X form sync instruction. */
1455 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1456
1457 /* An X form sync instruction with everything filled in except the LS field. */
1458 #define XSYNC_MASK (0xff9fffff)
1459
1460 /* An X_MASK, but with the EH bit clear. */
1461 #define XEH_MASK (X_MASK & ~((unsigned long )1))
1462
1463 /* An X form AltiVec dss instruction. */
1464 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1465 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1466
1467 /* An XFL form instruction. */
1468 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1469 #define XFL_MASK XFL (0x3f, 0x3ff, 1)
1470
1471 /* An X form isel instruction. */
1472 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1473 #define XISEL_MASK XISEL(0x3f, 0x1f)
1474
1475 /* An XL form instruction with the LK field set to 0. */
1476 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1477
1478 /* An XL form instruction which uses the LK field. */
1479 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1480
1481 /* The mask for an XL form instruction. */
1482 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1483
1484 /* An XL form instruction which explicitly sets the BO field. */
1485 #define XLO(op, bo, xop, lk) \
1486 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1487 #define XLO_MASK (XL_MASK | BO_MASK)
1488
1489 /* An XL form instruction which explicitly sets the y bit of the BO
1490 field. */
1491 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1492 #define XLYLK_MASK (XL_MASK | Y_MASK)
1493
1494 /* An XL form instruction which sets the BO field and the condition
1495 bits of the BI field. */
1496 #define XLOCB(op, bo, cb, xop, lk) \
1497 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1498 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1499
1500 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1501 #define XLBB_MASK (XL_MASK | BB_MASK)
1502 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1503 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1504
1505 /* A mask for branch instructions using the BH field. */
1506 #define XLBH_MASK (XL_MASK | (0x1c << 11))
1507
1508 /* An XL_MASK with the BO and BB fields fixed. */
1509 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1510
1511 /* An XL_MASK with the BO, BI and BB fields fixed. */
1512 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1513
1514 /* An XO form instruction. */
1515 #define XO(op, xop, oe, rc) \
1516 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1517 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1518
1519 /* An XO_MASK with the RB field fixed. */
1520 #define XORB_MASK (XO_MASK | RB_MASK)
1521
1522 /* An XS form instruction. */
1523 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1524 #define XS_MASK XS (0x3f, 0x1ff, 1)
1525
1526 /* A mask for the FXM version of an XFX form instruction. */
1527 #define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1528
1529 /* An XFX form instruction with the FXM field filled in. */
1530 #define XFXM(op, xop, fxm, p4) \
1531 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1532 | ((unsigned long)(p4) << 20))
1533
1534 /* An XFX form instruction with the SPR field filled in. */
1535 #define XSPR(op, xop, spr) \
1536 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1537 #define XSPR_MASK (X_MASK | SPR_MASK)
1538
1539 /* An XFX form instruction with the SPR field filled in except for the
1540 SPRBAT field. */
1541 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1542
1543 /* An XFX form instruction with the SPR field filled in except for the
1544 SPRG field. */
1545 #define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1546
1547 /* An X form instruction with everything filled in except the E field. */
1548 #define XE_MASK (0xffff7fff)
1549
1550 /* An X form user context instruction. */
1551 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1552 #define XUC_MASK XUC(0x3f, 0x1f)
1553
1554 /* The BO encodings used in extended conditional branch mnemonics. */
1555 #define BODNZF (0x0)
1556 #define BODNZFP (0x1)
1557 #define BODZF (0x2)
1558 #define BODZFP (0x3)
1559 #define BODNZT (0x8)
1560 #define BODNZTP (0x9)
1561 #define BODZT (0xa)
1562 #define BODZTP (0xb)
1563
1564 #define BOF (0x4)
1565 #define BOFP (0x5)
1566 #define BOFM4 (0x6)
1567 #define BOFP4 (0x7)
1568 #define BOT (0xc)
1569 #define BOTP (0xd)
1570 #define BOTM4 (0xe)
1571 #define BOTP4 (0xf)
1572
1573 #define BODNZ (0x10)
1574 #define BODNZP (0x11)
1575 #define BODZ (0x12)
1576 #define BODZP (0x13)
1577 #define BODNZM4 (0x18)
1578 #define BODNZP4 (0x19)
1579 #define BODZM4 (0x1a)
1580 #define BODZP4 (0x1b)
1581
1582 #define BOU (0x14)
1583
1584 /* The BI condition bit encodings used in extended conditional branch
1585 mnemonics. */
1586 #define CBLT (0)
1587 #define CBGT (1)
1588 #define CBEQ (2)
1589 #define CBSO (3)
1590
1591 /* The TO encodings used in extended trap mnemonics. */
1592 #define TOLGT (0x1)
1593 #define TOLLT (0x2)
1594 #define TOEQ (0x4)
1595 #define TOLGE (0x5)
1596 #define TOLNL (0x5)
1597 #define TOLLE (0x6)
1598 #define TOLNG (0x6)
1599 #define TOGT (0x8)
1600 #define TOGE (0xc)
1601 #define TONL (0xc)
1602 #define TOLT (0x10)
1603 #define TOLE (0x14)
1604 #define TONG (0x14)
1605 #define TONE (0x18)
1606 #define TOU (0x1f)
1607
1608 /* Smaller names for the flags so each entry in the opcodes table will
1609 fit on a single line. */
1610 #undef PPC
1611 #define PPC PPC_OPCODE_PPC
1612 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1613 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1614 #define POWER4 PPC_OPCODE_POWER4
1615 #define POWER5 PPC_OPCODE_POWER5
1616 #define POWER6 PPC_OPCODE_POWER6
1617 #define CELL PPC_OPCODE_CELL
1618 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1619 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1620 #define PPC403 PPC_OPCODE_403
1621 #define PPC405 PPC403
1622 #define PPC440 PPC_OPCODE_440
1623 #define PPC750 PPC
1624 #define PPC860 PPC
1625 #define PPCVEC PPC_OPCODE_ALTIVEC
1626 #define POWER PPC_OPCODE_POWER
1627 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1628 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1629 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1630 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1631 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1632 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1633 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1634 #define MFDEC1 PPC_OPCODE_POWER
1635 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1636 #define BOOKE PPC_OPCODE_BOOKE
1637 #define BOOKE64 PPC_OPCODE_BOOKE64
1638 #define CLASSIC PPC_OPCODE_CLASSIC
1639 #define PPCE300 PPC_OPCODE_E300
1640 #define PPCSPE PPC_OPCODE_SPE
1641 #define PPCISEL PPC_OPCODE_ISEL
1642 #define PPCEFS PPC_OPCODE_EFS
1643 #define PPCBRLK PPC_OPCODE_BRLOCK
1644 #define PPCPMR PPC_OPCODE_PMR
1645 #define PPCCHLK PPC_OPCODE_CACHELCK
1646 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1647 #define PPCRFMCI PPC_OPCODE_RFMCI
1648
1649 /* The opcode table.
1650
1651 The format of the opcode table is:
1652
1653 NAME OPCODE MASK FLAGS { OPERANDS }
1654
1655 NAME is the name of the instruction.
1656 OPCODE is the instruction opcode.
1657 MASK is the opcode mask; this is used to tell the disassembler
1658 which bits in the actual opcode must match OPCODE.
1659 FLAGS are flags indicated what processors support the instruction.
1660 OPERANDS is the list of operands.
1661
1662 The disassembler reads the table in order and prints the first
1663 instruction which matches, so this table is sorted to put more
1664 specific instructions before more general instructions. It is also
1665 sorted by major opcode. */
1666
1667 const struct powerpc_opcode powerpc_opcodes[] = {
1668 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1669 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1670 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1671 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1672 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1673 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1674 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1675 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1676 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1677 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1678 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1679 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1680 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1681 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1682 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1683 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1684
1685 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1686 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1687 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1688 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1689 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1690 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1691 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1692 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1693 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1694 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1695 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1696 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1697 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1698 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1699 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1700 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1701 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1702 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1703 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1704 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1705 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1706 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1707 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1708 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1709 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1710 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1711 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1712 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1713 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1714 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1715
1716 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1717 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1718 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1719 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1720 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1721 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1722 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1723 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1724 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1725 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1726 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1727 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1728 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1729 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1730 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1731 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1732 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1733 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1734 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1735 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1736 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1737 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1738 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1739 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1740 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1741 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1742 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1743 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1744 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1745 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1746 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1747 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1748 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1749 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1750 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1751 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1752 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1753 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1754 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1755 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1756 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1757 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1758 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1759 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1760 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1761 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1762 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1763 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1764 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1765 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1766 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1767 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1768 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1769 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1770 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1771 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1772 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1773 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1774 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1775 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1776 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1777 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1778 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1779 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1780 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1781 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1782 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1783 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1784 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1785 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1786 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1787 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1788 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1789 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1790 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1791 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1792 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1793 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1794 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1795 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1796 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1797 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1798 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1799 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1800 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1801 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1802
1803 /* Double-precision opcodes. */
1804 /* Some of these conflict with AltiVec, so move them before, since
1805 PPCVEC includes the PPC_OPCODE_PPC set. */
1806 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
1807 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1808 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1809 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1810 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1811 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1812 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
1813 { "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } },
1814 { "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1815 { "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1816 { "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1817 { "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1818 { "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1819 { "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } },
1820 { "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } },
1821 { "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } },
1822 { "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } },
1823 { "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } },
1824 { "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } },
1825 { "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } },
1826 { "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } },
1827 { "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } },
1828 { "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } },
1829 { "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } },
1830 { "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } },
1831 { "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } },
1832 { "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } },
1833 { "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } },
1834 { "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } },
1835 /* End of double-precision opcodes. */
1836
1837 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1838 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1839 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1840 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1841 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1842 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1843 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1844 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1845 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1846 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1847 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1848 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1849 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1850 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1851 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1852 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1853 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1854 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1855 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1856 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1857 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1858 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1859 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1860 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1861 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1862 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1863 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1864 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1865 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1866 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1867 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1868 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1869 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1870 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1871 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1872 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1873 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1874 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1875 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1876 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1877 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1878 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1879 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1880 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1881 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1882 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1883 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1884 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1885 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1886 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
1887 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
1888 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1889 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
1890 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
1891 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
1892 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
1893 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
1894 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
1895 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
1896 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1897 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1898 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
1899 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
1900 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
1901 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
1902 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
1903 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
1904 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
1905 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1906 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
1907 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
1908 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
1909 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
1910 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
1911 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
1912 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1913 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1914 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1915 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1916 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1917 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1918 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
1919 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
1920 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
1921 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
1922 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
1923 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
1924 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
1925 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
1926 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
1927 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
1928 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
1929 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1930 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
1931 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
1932 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
1933 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
1934 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
1935 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
1936 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
1937 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
1938 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
1939 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
1940 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
1941 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
1942 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
1943 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
1944 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
1945 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
1946 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
1947 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
1948 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
1949 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
1950 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
1951 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
1952 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
1953 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
1954 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
1955 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1956 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1957 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
1958 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
1959 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
1960 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1961 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
1963 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
1964 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
1974 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
1975 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
1981 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
1982 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
1986 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
1987 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
1988 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
1989 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
1990 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
1991 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
1992
1993 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
1994 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
1995 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
1996 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
1997 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
1998 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
1999 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2000 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2001 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2002 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2003 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2004 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2005 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2006
2007 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2008
2009 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2010 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2011 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2012 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2013 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2014 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2015 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2016 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2017 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2018 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2019
2020 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2021 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2022 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2023 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2024 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2025 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2026 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2027 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2028 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2029 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2030 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2031 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2032 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2033 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2034
2035 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2036 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2037 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2038 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2039 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2040 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2041
2042 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2043 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2044 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2045 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2046 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2047 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2048 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2049 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2050 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2051 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2052 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2053 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2054 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2055 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2056 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2057 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2058 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2059 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2060 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2061 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2062 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2063 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2064
2065 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2066 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2067 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2068 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2069 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2070 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2071 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2072 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2073 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2074 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2075 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2076 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2077 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2078 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2079
2080 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2081 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2082 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2083 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2084 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2085 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2086 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2087 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2088 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2089 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2090 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2091 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2092 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2093 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2094 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2095 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2096 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2097 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2098 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2099 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2100 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2101 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2102 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2103
2104 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2105 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2106 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2107 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2108 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2109 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2110 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2111 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2112 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2113 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2114 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2115 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2116 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2117 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2118 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2119 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2120 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2121 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2122 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2123 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2124 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2125 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2126 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2127
2128 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2129 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2130 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2132 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2135 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2136 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2137 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2138 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2139 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2140 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2141 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2142 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2143 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2144
2145 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2146 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2147 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2148 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2149 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2151 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2152 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2153 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2154 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2155 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2156 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2157
2158 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2159 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2160 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2161 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2162 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2163 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2164 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2165 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2166 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2167 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2168 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2169 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2170
2171 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2172 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2173 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2174 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2176 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2177
2178 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2179 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2180 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2181 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2182 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2183 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2184
2185 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2187 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2188 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2189 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2190 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2191 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2193
2194 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2195 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2196
2197 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2198 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2199 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2200 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2201
2202 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2203 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2205 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2206
2207 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2208 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2209 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2210 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2211 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2212 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2213 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2214 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2215
2216 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2217 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2218 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2219 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2220
2221 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2222 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2223 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2224 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2225
2226 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2227 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2228 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2229 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2230
2231 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2232 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2233 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2234 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2235
2236 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2237
2238 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2239 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2240
2241 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2242 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2243
2244 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2245 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2246
2247 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2248
2249 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2250 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2251 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2252 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2253
2254 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2255 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2256 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2257 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2258
2259 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2260 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2261 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2262 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2263
2264 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2265 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2266 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2267
2268 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2269 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2270 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2271
2272 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2273 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2274 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2275 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2276 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2277 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2278
2279 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2280 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2281 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2282 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2283 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2284
2285 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2286 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2287 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2288 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2289 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2290 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2291 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2292 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2293 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2294 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2295 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2296 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2297 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2298 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2299 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2300 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2301 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2302 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2303 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2304 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2305 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2306 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2307 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2308 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2309 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2310 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2311 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2312 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2313 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2314 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2315 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2316 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2317 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2318 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2319 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2320 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2321 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2322 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2323 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2324 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2325 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2326 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2327 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2328 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2329 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2330 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2331 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2332 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2333 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2334 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2335 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2336 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2337 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2338 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2339 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2340 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2341 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2342 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2343 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2344 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2345 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2346 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2347 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2348 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2349 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2350 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2351 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2352 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2353 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2354 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2355 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2356 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2357 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2358 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2359 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2360 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2361 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2362 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2363 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2364 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2365 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2366 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2367 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2368 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2369 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2370 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2371 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2372 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2373 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2374 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2375 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2376 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2377 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2378 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2379 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2380 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2381 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2382 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2383 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2384 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2385 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2386 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2387 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2388 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2389 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2390 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2391 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2392 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2393 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2394 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2395 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2396 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2397 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2398 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2399 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2400 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2401 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2402 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2403 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2404 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2405 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2406 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2407 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2408 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2409 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2410 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2411 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2412 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2413 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2414 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2415 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2416 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2417 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2418 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2419 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2420 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2421 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2422 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2423 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2424 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2425 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2426 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2427 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2428 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2429 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2430 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2431 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2432 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2433 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2434 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2435 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2436 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2437 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2438 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2439 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2440 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2441 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2442 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2443 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2444 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2445 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2446 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2447 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2448 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2449 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2450 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2451 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2452 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2453 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2454 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2455 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2456 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2457 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2458 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2459 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2460 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2461 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2462 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2463 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2464 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2465 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2466 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2467 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2468 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2469 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2470 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2471 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2472 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2473 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2474 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2475 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2476 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2477 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2478 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2479 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2480 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2481 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2482 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2483 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2484 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2485 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2486 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2487 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2488 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2489 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2490 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2491 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2492 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2493 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2494 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2495 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2496 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2497 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2498 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2499 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2500 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2501 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2502 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2503 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2504 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2505 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2506 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2507 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2508 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2509 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2510 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2511 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2512 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2513 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2514 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2515 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2516 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2517 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2518 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2519 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2520 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2521 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2522 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2523 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2524 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2525 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2526 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2527 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2528 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2529 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2530 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2531 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2532 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2533 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2534 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2535 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2536 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2537 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2538 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2539 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2540 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2541 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2542 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2543 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2544 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2545 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2546 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2547 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2548 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2549
2550 { "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
2551 { "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2552 { "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
2553 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2554 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2555
2556 { "b", B(18,0,0), B_MASK, COM, { LI } },
2557 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2558 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2559 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2560
2561 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2562
2563 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2564 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2565 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2566 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2567 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2568 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2569 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2570 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2571 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2572 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2573 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2574 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2575 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2576 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2577 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2578 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2579 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2580 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2581 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2582 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2583 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2584 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2585 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2586 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2587 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2588 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2589 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2590 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2591 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2592 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2593 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2594 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2595 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2596 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2597 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2598 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2599 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2600 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2601 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2602 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2603 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2604 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2605 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2606 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2607 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2608 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2609 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2610 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2611 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2612 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2613 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2614 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2615 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2616 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2617 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2618 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2619 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2620 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2621 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2622 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2623 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2624 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2625 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2626 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2627 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2628 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2629 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2630 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2631 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2632 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2633 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2634 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2635 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2636 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2637 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2638 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2639 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2640 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2641 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2642 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2643 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2644 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2645 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2646 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2647 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2648 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2649 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2650 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2651 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2652 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2653 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2654 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2655 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2656 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2657 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2658 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2659 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2660 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2661 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2662 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2663 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2664 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2665 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2666 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2667 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2668 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2669 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2670 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2671 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2672 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2673 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2674 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2675 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2676 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2677 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2678 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2679 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2680 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2681 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2682 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2683 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2684 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2685 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2686 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2687 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2688 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2689 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2690 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2691 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2692 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2693 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2694 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2695 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2696 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2697 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2698 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2699 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2700 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2701 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2702 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2703 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2704 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2705 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2706 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2707 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2708 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2709 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2710 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2711 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2712 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2713 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2714 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2715 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2716 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2717 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2718 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2719 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2720 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2721 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2722 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2723 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2725 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2728 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2729 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2730 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2731 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2732 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2733 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2734 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2735 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2736 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2737 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2738 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2739 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2740 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2741 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2742 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2743 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2744 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2745 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2746 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2747 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2748 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2749 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2750 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2751 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2752 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2753 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2754 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2755 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2756 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2757 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2758 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2759 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2760 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2761 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2762 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2763 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2764 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2765 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2766 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2767 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2768 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2769 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2770 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2771 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2772 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2773 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2774 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2775 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2776 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2777 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2778 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2779 { "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2780 { "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2781 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2782 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2783 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2784 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2785
2786 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2787
2788 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2789 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2790 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2791
2792 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2793 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2794
2795 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2796
2797 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2798
2799 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2800 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2801
2802 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2803 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2804
2805 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2806
2807 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2808
2809 { "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } },
2810
2811 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2812 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2813
2814 { "doze", XL(19,402), 0xffffffff, POWER6, { 0 } },
2815
2816 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2817
2818 { "nap", XL(19,434), 0xffffffff, POWER6, { 0 } },
2819
2820 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2821 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2822
2823 { "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } },
2824 { "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } },
2825
2826 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2827 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2828 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2829 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2834 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2835 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2836 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2837 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2838 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2839 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2840 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2841 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2842 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2843 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2844 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2845 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2846 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2847 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2848 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2849 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2850 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2851 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2852 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2853 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2854 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2855 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2856 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2857 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2858 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2859 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2860 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2861 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2862 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2863 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2864 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2865 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2866 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2867 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2868 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2869 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2870 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2871 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2872 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2873 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2874 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2875 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2876 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2877 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2878 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2879 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2880 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2881 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2882 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2883 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2884 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2885 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2886 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2887 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2888 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2889 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2890 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2891 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2892 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2893 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2894 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2895 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2896 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2897 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2898 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2899 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2900 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2901 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2902 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2903 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2904 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2905 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2906 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2907 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2908 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2909 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2910 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2911 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2912 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2913 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2914 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2915 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2916 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2917 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2918 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2919 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2920 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2921 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2922 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2923 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2924 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2925 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2926 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2927 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2928 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2929 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2930 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2931 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2932 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2933 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2934 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2936 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2938 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2939 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2942 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2943 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2944 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2946 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2947 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2948 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2949 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2950 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2951 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2952 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2953 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2954 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2955 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2956 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2957 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2958 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
2959 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2960 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
2961 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
2962 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
2963 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
2964 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2965 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
2966 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
2967 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
2968 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2969 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2970 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2971 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2972 { "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2973 { "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } },
2974 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
2975 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
2976 { "bcctre", XLLK(19,529,0), XLBB_MASK, BOOKE64, { BO, BI } },
2977 { "bcctrel", XLLK(19,529,1), XLBB_MASK, BOOKE64, { BO, BI } },
2978
2979 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2980 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2981
2982 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2983 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2984
2985 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
2986 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2987 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2988 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2989 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
2990 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
2991 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
2992 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
2993
2994 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2995 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
2996
2997 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
2998 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
2999 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3000 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3001
3002 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3003 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3004 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3005 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3006 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3007 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3008
3009 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3010 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3011 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3012
3013 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3014 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3015
3016 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3017 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3018
3019 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3020 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3021
3022 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3023 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3024
3025 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3026 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3027
3028 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3029 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3030 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3031 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3032 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3033 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3034
3035 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3036 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3037
3038 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3039 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3040
3041 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3042 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3043
3044 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3045 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3046 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3047 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3048
3049 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3050 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3051
3052 { "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3053 { "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3054 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3055 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3056
3057 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3058 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3059 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3060 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3061 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3062 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3063 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3064 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3065 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3066 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3067 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3068 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3069 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3070 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3071 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3072 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3073 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3074 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3075 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3076 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3077 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3078 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3079 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3080 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3081 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3082 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3083 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3084 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3085 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3086 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3087 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3088
3089 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3090 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3091 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3092 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3093 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3094 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3095 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3096 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3097 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3098 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3099 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3100 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3101
3102 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3103 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3104
3105 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3106 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3107 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3108 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3109 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3110 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3111 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3112 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3113
3114 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3115 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3116
3117 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3118 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3119 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3120 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3121
3122 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3123 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3124 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3125
3126 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3127
3128 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3129
3130 { "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } },
3131 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3132
3133 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3134 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3135
3136 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3137 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3138 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3139 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3140
3141 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3142 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3143 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3144 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3145
3146 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3147 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3148
3149 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3150 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3151
3152 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3153 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3154
3155 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3156
3157 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3158
3159 { "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3160 { "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3161 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3162 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3163
3164 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3165 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3166 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3167 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3168 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3169 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3170 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3171 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3172
3173 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3174
3175 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3176
3177 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3178 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3179
3180 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3181
3182 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3183
3184 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3185 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3186
3187 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3188 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3189
3190 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3191 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3192 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3193 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3194 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3195 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3196 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3197 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3198 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3199 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3200 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3201 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3202 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3203 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3204 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3205
3206 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3207 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3208
3209 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3210 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3211
3212 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3213 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3214
3215 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3216
3217 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3218
3219 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3220
3221 { "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } },
3222 { "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, L } },
3223
3224 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3225
3226 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3227
3228 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3229
3230 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3231 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3232 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3233 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3234
3235 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3236 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3237 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3238 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3239
3240 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3241
3242 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3243
3244 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3245
3246 { "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
3247
3248 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3249 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3250 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3251 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3252
3253 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3254
3255 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3256
3257 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3258
3259 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3260
3261 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3262 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3263 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3264 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3265 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3266 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3267 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3268 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3269
3270 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3271 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3272 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3273 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3274 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3275 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3276 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3277 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3278
3279 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3280
3281 { "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } },
3282 { "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }},
3283 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3284
3285 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3286
3287 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } },
3288
3289 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } },
3290
3291 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } },
3292 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3293
3294 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } },
3295
3296 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } },
3297
3298 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3299 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3300
3301 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3302 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3303
3304 { "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } },
3305
3306 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3307
3308 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3309 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3310
3311 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, A_L } },
3312
3313 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3314
3315 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3316 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } },
3317
3318 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3319 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3320
3321 { "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } },
3322
3323 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3324
3325 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3326 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3327 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3328 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3329 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3330 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3331 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3332 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3333
3334 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3335 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3336 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3337 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3338 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3339 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3340 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3341 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3342
3343 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3344
3345 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } },
3346
3347 { "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } },
3348
3349 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3350 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3351
3352 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3353 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3354
3355 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } },
3356
3357 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3358
3359 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3360 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3361 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3362 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3363 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3364 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3365 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3366 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3367
3368 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3369 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3370 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3371 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3372
3373 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3374 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3375 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3376 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3377 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3378 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3379 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3380 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3381
3382 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3383 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3384 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3385 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3386 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3387 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3388 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3389 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3390
3391 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3392 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3393 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3394
3395 { "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } },
3396
3397 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3398
3399 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3400 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3401
3402 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3403
3404 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3405
3406 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3407
3408 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3409 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3410 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3411 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3412
3413 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3414 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3415 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3416 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3417 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3418 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3419 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3420 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3421
3422 { "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } },
3423
3424 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3425
3426 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3427 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3428
3429 { "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } },
3430
3431 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3432
3433 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3434 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3435
3436 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3437
3438 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3439
3440 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3441 { "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } },
3442
3443 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3444
3445 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3446
3447 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3448 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3449
3450 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3451
3452 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3453 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3454 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3455 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3456 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3457 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3458 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3459 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3460 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3461 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3462 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3463 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3464 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3465 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3466 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3467 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3468 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3469 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3470 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3471 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3472 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3473 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3474 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3475 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3476 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3477 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3478 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3479 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3480 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3481 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3482 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3483 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3484 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3485 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3486 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3487
3488 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3489 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3490 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3491 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3492
3493 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3494
3495 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3496 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3497 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3498 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3499 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3500 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3501 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3502 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3503 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3504 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3505 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3506 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3507 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3508 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3509 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3510 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3511 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3512 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3513 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3514 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3515 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3516 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3517 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3518 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3519 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3520 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3521 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3522 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3523 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3524 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3525 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3526 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3527 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3528 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3529 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3530 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3531 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3532 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3533 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3534 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3535 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3536 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3537 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3538 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3539 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3540 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3541 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3542 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3543 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3544 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3545 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3546 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3547 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3548 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3549 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3550 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3551 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3552 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3553 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3554 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3555 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3556 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3557 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3558 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3559 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3560 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3561 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3562 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3563 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3564 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3565 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3566 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3567 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3568 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3569 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3570 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3571 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3572 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3573 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3574 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3575 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3576 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3577 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3578 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3579 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3580 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3581 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3582 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3583 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3584 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3585 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3586 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3587 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3588 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3589 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3590 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3591 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3592 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3593 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3594 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3595 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3596 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3597 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3598 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3599 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3600 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3601 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3602 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3603 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3604 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3605 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3606 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3607 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3608 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3609 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3610 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3611 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3612 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3613 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3614 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3615 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3616 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3617 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3618 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3619 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3620 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3621 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3622 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3623 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3624 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3625 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3626 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3627 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3628 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3629 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3630 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3631 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3632 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3633 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3634 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3635 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3636 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3637 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3638 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3639 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3640 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3641 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3642 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3643 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3644 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3645 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3646 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3647 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3648 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3649 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3650 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3651 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3652 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3653 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3654 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3655 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3656 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3657 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3658 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3659 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3660 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3661 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3662 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3663 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3664 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3665 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3666 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3667 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3668 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3669 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3670 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3671 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3672 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3673 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3674 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3675 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3676 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3677 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3678 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3679 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3680 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3681 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3682 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3683
3684 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3685
3686 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3687 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3688
3689 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3690
3691 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3692
3693 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3694 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3695
3696 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3697
3698 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3699 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3700 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3701 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3702
3703 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3704 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3705 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3706 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3707
3708 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3709
3710 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3711
3712 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3713
3714 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3715
3716 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3717
3718 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3719
3720 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3721 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3722
3723 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3724 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3725
3726 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3727
3728 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3729
3730 { "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } },
3731
3732 { "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } },
3733
3734 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3735
3736 { "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } },
3737
3738 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3739
3740 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3741
3742 { "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } },
3743
3744 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3745
3746 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3747 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3748
3749 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3750 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3751
3752 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } },
3753
3754 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3755
3756 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3757
3758 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3759
3760 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3761
3762 { "cctpl", 0x7c210b78, 0xffffffff, CELL, { 0 }},
3763 { "cctpm", 0x7c421378, 0xffffffff, CELL, { 0 }},
3764 { "cctph", 0x7c631b78, 0xffffffff, CELL, { 0 }},
3765 { "db8cyc", 0x7f9ce378, 0xffffffff, CELL, { 0 }},
3766 { "db10cyc", 0x7fbdeb78, 0xffffffff, CELL, { 0 }},
3767 { "db12cyc", 0x7fdef378, 0xffffffff, CELL, { 0 }},
3768 { "db16cyc", 0x7ffffb78, 0xffffffff, CELL, { 0 }},
3769 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3770 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3771 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3772 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3773
3774 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3775 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3776 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3777 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3778 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3779 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3780 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3781 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3782 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3783 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3784 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3785 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3786 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3787 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3788 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3789 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3790 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3791 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3792 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3793 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3794 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3795 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3796 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3797 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3798 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3799 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3800 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3801 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3802 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3803 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3804 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3805 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3806 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3807 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3808 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3809
3810 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3811 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3812
3813 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3814 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3815 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3816 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3817
3818 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3819 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3820
3821 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3822 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3823 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3824 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3825
3826 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3827 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3828 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3829 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3830 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3831 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3832 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3833 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3834 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3835 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3836 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3837 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3838 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3839 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3840 { "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } },
3841 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3842 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3843 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3844 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3845 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3846 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3847 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3848 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3849 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3850 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3851 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3852 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3853 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3854 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3855 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3856 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3857 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3858 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3859 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3860 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3861 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3862 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3863 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3864 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3865 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3866 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3867 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3868 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3869 { "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } },
3870 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3871 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3872 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3873 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3874 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3875 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3876 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3877 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3878 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3879 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3880 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3881 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3882 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3883 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3884 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3885 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3886 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3887 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3888 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3889 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3890 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3891 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3892 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3893 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3894 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3895 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3896 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3897 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3898 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3899 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3900 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3901 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3902 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3903 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3904 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3905 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3906 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3907 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3908 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3909 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3910 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3911 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3912 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3913 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3914 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3915 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3916 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3917 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3918 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3919 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3920 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
3921 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
3922 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
3923 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
3924 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
3925 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
3926 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
3927 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
3928 { "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } },
3929 { "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } },
3930 { "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } },
3931 { "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } },
3932 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3933 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3934 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3935 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
3936 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
3937 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
3938 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
3939 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
3940 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
3941 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
3942 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
3943 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
3944 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
3945 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
3946 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
3947 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
3948 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
3949 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
3950 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
3951 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
3952 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
3953 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
3954 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
3955 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
3956 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
3957 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
3958 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
3959 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
3960 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
3961 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
3962 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
3963 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
3964 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
3965 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
3966 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
3967 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
3968 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
3969 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
3970 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
3971 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
3972 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
3973 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
3974 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
3975 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
3976 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
3977 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
3978 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
3979
3980 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
3981
3982 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
3983 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
3984
3985 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
3986
3987 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
3988
3989 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
3990
3991 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
3992
3993 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
3994 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3995 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
3996 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
3997 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3998 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
3999
4000 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4001 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4002 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4003 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4004
4005 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4006 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4007
4008 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4009 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4010 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4011 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4012
4013 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4014
4015 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4016
4017 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4018
4019 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4020
4021 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4022
4023 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4024 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4025
4026 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4027
4028 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4029
4030 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4031 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4032
4033 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4034 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4035
4036 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } },
4037
4038 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4039 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4040 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4041 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4042
4043 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4044 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4045
4046 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4047 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4048
4049 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4050 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4051
4052 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4053
4054 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } },
4055
4056 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4057
4058 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4059
4060 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4061
4062 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4063
4064 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4065
4066 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4067 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4068
4069 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4070 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4071 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4072 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4073 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4074
4075 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } },
4076
4077 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } },
4078
4079 { "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } },
4080
4081 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4082
4083 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4084
4085 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4086
4087 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4088
4089 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4090
4091 { "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } },
4092
4093 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } },
4094 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } },
4095
4096 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } },
4097 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } },
4098
4099 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } },
4100
4101 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4102 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4103
4104 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4105 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4106
4107 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } },
4108
4109 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } },
4110
4111 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4112
4113 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4114 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4115
4116 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4117
4118 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } },
4119 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } },
4120
4121 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } },
4122
4123 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4124 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4125
4126 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4127 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4128
4129 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } },
4130
4131 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4132
4133 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4134
4135 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4136
4137 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4138 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4139
4140 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4141
4142 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4143
4144 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4145 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4146
4147 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4148
4149 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4150
4151 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4152 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4153 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4154 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4155
4156 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4157 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4158
4159 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4160
4161 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4162 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4163
4164 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4165
4166 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4167
4168 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4169 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4170
4171 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4172 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4173 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4174 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4175
4176 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4177
4178 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4179
4180 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4181 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4182
4183 { "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } },
4184
4185 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4186
4187 { "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4188 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } },
4189 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RTO, RA, RB } },
4190 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RTO, RA, RB } },
4191
4192 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4193
4194 { "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } },
4195
4196 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } },
4197
4198 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4199 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4200
4201 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4202 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4203
4204 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4205 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4206 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4207 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4208
4209 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } },
4210
4211 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } },
4212
4213 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4214 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4215 { "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4216
4217 { "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } },
4218
4219 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4220 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4221
4222 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4223 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4224
4225 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4226
4227 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4228
4229 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4230 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4231 { "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } },
4232 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4233
4234 { "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } },
4235
4236 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4237
4238 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } },
4239
4240 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4241 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4242
4243 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4244
4245 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4246 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } },
4247
4248 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4249
4250 { "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } },
4251
4252 { "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } },
4253 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4254 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4255
4256 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4257
4258 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4259 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4260 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4261 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4262 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4263 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4264 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4265 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4266 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4267 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4268 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4269 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4270
4271 /* New load/store left/right index vector instructions that are in the Cell only. */
4272 { "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
4273 { "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
4274 { "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } },
4275 { "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } },
4276 { "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } },
4277 { "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } },
4278 { "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } },
4279 { "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } },
4280
4281 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4282 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4283
4284 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4285 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4286
4287 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4288
4289 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4290
4291 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } },
4292 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } },
4293
4294 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4295 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } },
4296
4297 { "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } },
4298
4299 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4300
4301 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4302
4303 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4304
4305 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4306
4307 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4308
4309 { "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } },
4310
4311 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4312
4313 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4314 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4315
4316 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } },
4317 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } },
4318
4319 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } },
4320
4321 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4322
4323 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } },
4324
4325 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4326
4327 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } },
4328
4329 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4330
4331 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } },
4332
4333 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4334
4335 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4336
4337 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } },
4338
4339 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } },
4340
4341 { "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } },
4342
4343 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4344 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4345 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4346 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4347 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4348 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4349 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4350 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4351 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4352 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4353 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4354 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4355 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } },
4356 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4357
4358 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4359
4360 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4361
4362 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4363
4364 { "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4365 { "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4366
4367 { "dqua", ZRC(59,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4368 { "dqua.", ZRC(59,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4369
4370 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4371 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4372
4373 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4374 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4375
4376 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4377 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4378
4379 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4380 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4381
4382 { "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4383 { "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4384
4385 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4386 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4387
4388 { "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4389 { "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } },
4390
4391 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4392 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4393
4394 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4395 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4396
4397 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4398 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4399
4400 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4401 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4402
4403 { "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4404 { "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4405
4406 { "drrnd", ZRC(59,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4407 { "drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4408
4409 { "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4410 { "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4411
4412 { "dquai", ZRC(59,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4413 { "dquai.", ZRC(59,67,1), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4414
4415 { "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4416 { "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4417
4418 { "drintx", ZRC(59,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4419 { "drintx.", ZRC(59,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4420
4421 { "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } },
4422
4423 { "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } },
4424 { "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4425 { "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4426
4427 { "drintn", ZRC(59,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4428 { "drintn.", ZRC(59,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4429
4430 { "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } },
4431 { "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } },
4432
4433 { "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } },
4434 { "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } },
4435
4436 { "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4437 { "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4438
4439 { "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } },
4440 { "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } },
4441
4442 { "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4443 { "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4444
4445 { "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4446 { "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4447
4448 { "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } },
4449
4450 { "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } },
4451
4452 { "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } },
4453 { "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } },
4454
4455 { "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } },
4456 { "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } },
4457
4458 { "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4459 { "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4460
4461 { "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4462 { "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4463
4464 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4465
4466 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4467
4468 { "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } },
4469
4470 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4471 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4472 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4473 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4474 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } },
4475 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4476 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } },
4477 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4478 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4479 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4480 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } },
4481 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4482
4483 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } },
4484
4485 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4486
4487 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } },
4488
4489 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4490
4491 { "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4492 { "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4493
4494 { "dquaq", ZRC(63,3,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4495 { "dquaq.", ZRC(63,3,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4496
4497 { "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4498 { "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4499
4500 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4501 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4502
4503 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4504 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4505 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4506 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4507
4508 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4509 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4510 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4511 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4512
4513 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4514 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4515 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4516 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4517
4518 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4519 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4520 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4521 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4522
4523 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4524 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4525 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4526 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4527
4528 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4529 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4530
4531 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4532 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4533
4534 { "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4535 { "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } },
4536
4537 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4538 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4539 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4540 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4541
4542 { "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4543 { "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } },
4544
4545 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4546 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4547 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4548 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4549
4550 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4551 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4552 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4553 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4554
4555 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4556 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4557 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4558 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4559
4560 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4561 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4562 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4563 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4564
4565 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4566
4567 { "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4568 { "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4569
4570 { "drrndq", ZRC(63,35,0), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4571 { "drrndq.", ZRC(63,35,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4572
4573 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4574 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4575
4576 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4577 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4578
4579 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4580
4581 { "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4582 { "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4583
4584 { "dquaiq", ZRC(63,67,0), Z2_MASK, POWER6, { TE, FRT, FRB, RMC } },
4585 { "dquaiq.", ZRC(63,67,1), Z2_MASK, POWER6, { FRT, FRA, FRB, RMC } },
4586
4587 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4588 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4589
4590 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4591 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4592
4593 { "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4594 { "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } },
4595
4596 { "drintxq", ZRC(63,99,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4597 { "drintxq.",ZRC(63,99,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4598
4599 { "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
4600
4601 { "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4602 { "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
4603
4604 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4605 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4606
4607 { "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } },
4608 { "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } },
4609 { "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } },
4610
4611 { "drintnq", ZRC(63,227,0), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4612 { "drintnq.",ZRC(63,227,1), Z2_MASK, POWER6, { R, FRT, FRB, RMC } },
4613
4614 { "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } },
4615 { "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } },
4616
4617 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4618 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4619
4620 { "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } },
4621 { "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } },
4622
4623 { "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } },
4624 { "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } },
4625
4626 { "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } },
4627 { "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } },
4628
4629 { "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } },
4630 { "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } },
4631 { "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } },
4632 { "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } },
4633 { "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } },
4634 { "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } },
4635 { "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } },
4636 { "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } },
4637
4638 { "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4639 { "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4640
4641 { "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4642 { "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4643
4644 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4645 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4646
4647 { "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } },
4648
4649 { "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
4650
4651 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4652 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
4653
4654 { "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
4655 { "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
4656
4657 { "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } },
4658 { "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } },
4659
4660 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4661 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4662
4663 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4664 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4665
4666 { "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } },
4667 { "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } },
4668
4669 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4670 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4671
4672 { "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } },
4673 { "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } },
4674
4675 };
4676
4677 const int powerpc_num_opcodes =
4678 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4679
4680 /* The macro table. This is only used by the assembler. */
4681
4682 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4683 when x=0; 32-x when x is between 1 and 31; are negative if x is
4684 negative; and are 32 or more otherwise. This is what you want
4685 when, for instance, you are emulating a right shift by a
4686 rotate-left-and-mask, because the underlying instructions support
4687 shifts of size 0 but not shifts of size 32. By comparison, when
4688 extracting x bits from some word you want to use just 32-x, because
4689 the underlying instructions don't support extracting 0 bits but do
4690 support extracting the whole word (32 bits in this case). */
4691
4692 const struct powerpc_macro powerpc_macros[] = {
4693 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4694 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4695 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4696 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4697 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4698 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4699 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4700 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4701 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4702 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4703 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4704 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4705 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4706 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4707 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4708 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4709
4710 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4711 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4712 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4713 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4714 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4715 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4716 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4717 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4718 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4719 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4720 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4721 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4722 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4723 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4724 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4725 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4726 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4727 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4728 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4729 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4730 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4731 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4732 };
4733
4734 const int powerpc_num_macros =
4735 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
4736