1 /* $OpenBSD: if_sk.c,v 1.200 2024/11/05 18:58:59 miod Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
35 */
36
37 /*
38 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
39 *
40 * Permission to use, copy, modify, and distribute this software for any
41 * purpose with or without fee is hereby granted, provided that the above
42 * copyright notice and this permission notice appear in all copies.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
45 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
47 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
48 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
49 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
50 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
51 */
52
53 /*
54 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
55 * the SK-984x series adapters, both single port and dual port.
56 * References:
57 * The XaQti XMAC II datasheet,
58 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
59 * The SysKonnect GEnesis manual, http://www.syskonnect.com
60 *
61 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
62 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
63 * convenience to others until Vitesse corrects this problem:
64 *
65 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
66 *
67 * Written by Bill Paul <wpaul@ee.columbia.edu>
68 * Department of Electrical Engineering
69 * Columbia University, New York City
70 */
71
72 /*
73 * The SysKonnect gigabit ethernet adapters consist of two main
74 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
75 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
76 * components and a PHY while the GEnesis controller provides a PCI
77 * interface with DMA support. Each card may have between 512K and
78 * 2MB of SRAM on board depending on the configuration.
79 *
80 * The SysKonnect GEnesis controller can have either one or two XMAC
81 * chips connected to it, allowing single or dual port NIC configurations.
82 * SysKonnect has the distinction of being the only vendor on the market
83 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
84 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
85 * XMAC registers. This driver takes advantage of these features to allow
86 * both XMACs to operate as independent interfaces.
87 */
88
89 #include "bpfilter.h"
90
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
94 #include <sys/mbuf.h>
95 #include <sys/malloc.h>
96 #include <sys/timeout.h>
97 #include <sys/device.h>
98 #include <sys/queue.h>
99
100 #include <net/if.h>
101
102 #include <netinet/in.h>
103 #include <netinet/if_ether.h>
104
105 #include <net/if_media.h>
106
107 #if NBPFILTER > 0
108 #include <net/bpf.h>
109 #endif
110
111 #include <dev/mii/mii.h>
112 #include <dev/mii/miivar.h>
113 #include <dev/mii/brgphyreg.h>
114
115 #include <dev/pci/pcireg.h>
116 #include <dev/pci/pcivar.h>
117 #include <dev/pci/pcidevs.h>
118
119 #include <dev/pci/if_skreg.h>
120 #include <dev/pci/if_skvar.h>
121
122 int skc_probe(struct device *, void *, void *);
123 void skc_attach(struct device *, struct device *self, void *aux);
124 int skc_detach(struct device *, int);
125 int skc_activate(struct device *, int);
126 int sk_probe(struct device *, void *, void *);
127 void sk_attach(struct device *, struct device *self, void *aux);
128 int sk_detach(struct device *, int);
129 int sk_activate(struct device *, int);
130 int skcprint(void *, const char *);
131 int sk_intr(void *);
132 void sk_intr_bcom(struct sk_if_softc *);
133 void sk_intr_xmac(struct sk_if_softc *);
134 void sk_intr_yukon(struct sk_if_softc *);
135 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
136 void sk_rxeof(struct sk_if_softc *);
137 void sk_txeof(struct sk_if_softc *);
138 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *);
139 void sk_start(struct ifnet *);
140 int sk_ioctl(struct ifnet *, u_long, caddr_t);
141 void sk_init(void *);
142 void sk_init_xmac(struct sk_if_softc *);
143 void sk_init_yukon(struct sk_if_softc *);
144 void sk_stop(struct sk_if_softc *, int softonly);
145 void sk_watchdog(struct ifnet *);
146 int sk_ifmedia_upd(struct ifnet *);
147 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
148 void skc_reset(struct sk_softc *);
149 int sk_newbuf(struct sk_if_softc *);
150 int sk_reset(struct sk_if_softc *);
151 int sk_init_rx_ring(struct sk_if_softc *);
152 void sk_fill_rx_ring(struct sk_if_softc *);
153 int sk_init_tx_ring(struct sk_if_softc *);
154
155 int sk_xmac_miibus_readreg(struct device *, int, int);
156 void sk_xmac_miibus_writereg(struct device *, int, int, int);
157 void sk_xmac_miibus_statchg(struct device *);
158
159 int sk_marv_miibus_readreg(struct device *, int, int);
160 void sk_marv_miibus_writereg(struct device *, int, int, int);
161 void sk_marv_miibus_statchg(struct device *);
162
163 void sk_setfilt(struct sk_if_softc *, caddr_t, int);
164 void sk_iff(struct sk_if_softc *);
165 void sk_iff_xmac(struct sk_if_softc *);
166 void sk_iff_yukon(struct sk_if_softc *);
167
168 void sk_tick(void *);
169 void sk_yukon_tick(void *);
170
171 #ifdef SK_DEBUG
172 #define DPRINTF(x) if (skdebug) printf x
173 #define DPRINTFN(n,x) if (skdebug >= (n)) printf x
174 int skdebug = 0;
175
176 void sk_dump_txdesc(struct sk_tx_desc *, int);
177 void sk_dump_mbuf(struct mbuf *);
178 void sk_dump_bytes(const char *, int);
179 #else
180 #define DPRINTF(x)
181 #define DPRINTFN(n,x)
182 #endif
183
184 /* supported device vendors */
185 const struct pci_matchid skc_devices[] = {
186 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940 },
187 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940B },
188 { PCI_VENDOR_CNET, PCI_PRODUCT_CNET_GIGACARD },
189 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_A1 },
190 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_B1 },
191 { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064 },
192 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON },
193 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_YUKON_BELKIN },
194 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX },
195 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 },
196 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9821 },
197 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9843 }
198 };
199
200 #define SK_LINKSYS_EG1032_SUBID 0x00151737
201
202 static inline u_int32_t
sk_win_read_4(struct sk_softc * sc,u_int32_t reg)203 sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
204 {
205 return CSR_READ_4(sc, reg);
206 }
207
208 static inline u_int16_t
sk_win_read_2(struct sk_softc * sc,u_int32_t reg)209 sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
210 {
211 return CSR_READ_2(sc, reg);
212 }
213
214 static inline u_int8_t
sk_win_read_1(struct sk_softc * sc,u_int32_t reg)215 sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
216 {
217 return CSR_READ_1(sc, reg);
218 }
219
220 static inline void
sk_win_write_4(struct sk_softc * sc,u_int32_t reg,u_int32_t x)221 sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
222 {
223 CSR_WRITE_4(sc, reg, x);
224 }
225
226 static inline void
sk_win_write_2(struct sk_softc * sc,u_int32_t reg,u_int16_t x)227 sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
228 {
229 CSR_WRITE_2(sc, reg, x);
230 }
231
232 static inline void
sk_win_write_1(struct sk_softc * sc,u_int32_t reg,u_int8_t x)233 sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
234 {
235 CSR_WRITE_1(sc, reg, x);
236 }
237
238 int
sk_xmac_miibus_readreg(struct device * dev,int phy,int reg)239 sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)
240 {
241 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
242 int i;
243
244 DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
245
246 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
247 return (0);
248
249 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
250 SK_XM_READ_2(sc_if, XM_PHY_DATA);
251 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
252 for (i = 0; i < SK_TIMEOUT; i++) {
253 DELAY(1);
254 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
255 XM_MMUCMD_PHYDATARDY)
256 break;
257 }
258
259 if (i == SK_TIMEOUT) {
260 printf("%s: phy failed to come ready\n",
261 sc_if->sk_dev.dv_xname);
262 return (0);
263 }
264 }
265 DELAY(1);
266 return (SK_XM_READ_2(sc_if, XM_PHY_DATA));
267 }
268
269 void
sk_xmac_miibus_writereg(struct device * dev,int phy,int reg,int val)270 sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
271 {
272 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
273 int i;
274
275 DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
276
277 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
278 for (i = 0; i < SK_TIMEOUT; i++) {
279 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
280 break;
281 }
282
283 if (i == SK_TIMEOUT) {
284 printf("%s: phy failed to come ready\n",
285 sc_if->sk_dev.dv_xname);
286 return;
287 }
288
289 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
290 for (i = 0; i < SK_TIMEOUT; i++) {
291 DELAY(1);
292 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
293 break;
294 }
295
296 if (i == SK_TIMEOUT)
297 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
298 }
299
300 void
sk_xmac_miibus_statchg(struct device * dev)301 sk_xmac_miibus_statchg(struct device *dev)
302 {
303 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
304 struct mii_data *mii = &sc_if->sk_mii;
305
306 DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
307
308 /*
309 * If this is a GMII PHY, manually set the XMAC's
310 * duplex mode accordingly.
311 */
312 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
313 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
314 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
315 else
316 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
317 }
318 }
319
320 int
sk_marv_miibus_readreg(struct device * dev,int phy,int reg)321 sk_marv_miibus_readreg(struct device *dev, int phy, int reg)
322 {
323 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
324 u_int16_t val;
325 int i;
326
327 if (phy != 0 ||
328 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
329 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
330 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
331 phy, reg));
332 return (0);
333 }
334
335 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
336 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
337
338 for (i = 0; i < SK_TIMEOUT; i++) {
339 DELAY(1);
340 val = SK_YU_READ_2(sc_if, YUKON_SMICR);
341 if (val & YU_SMICR_READ_VALID)
342 break;
343 }
344
345 if (i == SK_TIMEOUT) {
346 printf("%s: phy failed to come ready\n",
347 sc_if->sk_dev.dv_xname);
348 return (0);
349 }
350
351 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
352 SK_TIMEOUT));
353
354 val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
355
356 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
357 phy, reg, val));
358
359 return (val);
360 }
361
362 void
sk_marv_miibus_writereg(struct device * dev,int phy,int reg,int val)363 sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
364 {
365 struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
366 int i;
367
368 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
369 phy, reg, val));
370
371 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
372 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
373 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
374
375 for (i = 0; i < SK_TIMEOUT; i++) {
376 DELAY(1);
377 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
378 break;
379 }
380
381 if (i == SK_TIMEOUT)
382 printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
383 }
384
385 void
sk_marv_miibus_statchg(struct device * dev)386 sk_marv_miibus_statchg(struct device *dev)
387 {
388 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
389 SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
390 }
391
392 void
sk_setfilt(struct sk_if_softc * sc_if,caddr_t addr,int slot)393 sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
394 {
395 int base = XM_RXFILT_ENTRY(slot);
396
397 SK_XM_WRITE_2(sc_if, base, letoh16(*(u_int16_t *)(&addr[0])));
398 SK_XM_WRITE_2(sc_if, base + 2, letoh16(*(u_int16_t *)(&addr[2])));
399 SK_XM_WRITE_2(sc_if, base + 4, letoh16(*(u_int16_t *)(&addr[4])));
400 }
401
402 void
sk_iff(struct sk_if_softc * sc_if)403 sk_iff(struct sk_if_softc *sc_if)
404 {
405 struct sk_softc *sc = sc_if->sk_softc;
406
407 if (SK_IS_GENESIS(sc))
408 sk_iff_xmac(sc_if);
409 else
410 sk_iff_yukon(sc_if);
411 }
412
413 void
sk_iff_xmac(struct sk_if_softc * sc_if)414 sk_iff_xmac(struct sk_if_softc *sc_if)
415 {
416 struct ifnet *ifp = &sc_if->arpcom.ac_if;
417 struct arpcom *ac = &sc_if->arpcom;
418 struct ether_multi *enm;
419 struct ether_multistep step;
420 u_int32_t reg, hashes[2];
421 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
422 int h, i;
423
424 reg = SK_XM_READ_4(sc_if, XM_MODE);
425 reg &= ~(XM_MODE_RX_NOBROAD | XM_MODE_RX_PROMISC | XM_MODE_RX_USE_HASH |
426 XM_MODE_RX_USE_PERFECT | XM_MODE_RX_USE_STATION);
427 ifp->if_flags &= ~IFF_ALLMULTI;
428
429 /*
430 * Always accept frames destined to our station address.
431 */
432 reg |= XM_MODE_RX_USE_STATION;
433
434 /* don't use perfect filter. */
435 for (i = 1; i < XM_RXFILT_MAX; i++)
436 sk_setfilt(sc_if, (caddr_t)&dummy, i);
437
438 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
439 ifp->if_flags |= IFF_ALLMULTI;
440 if (ifp->if_flags & IFF_PROMISC)
441 reg |= XM_MODE_RX_PROMISC;
442 else
443 reg |= XM_MODE_RX_USE_HASH;
444 hashes[0] = hashes[1] = 0xFFFFFFFF;
445 } else {
446 reg |= XM_MODE_RX_USE_HASH;
447 /* Program new filter. */
448 bzero(hashes, sizeof(hashes));
449
450 ETHER_FIRST_MULTI(step, ac, enm);
451 while (enm != NULL) {
452 h = ether_crc32_le(enm->enm_addrlo,
453 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1);
454
455 if (h < 32)
456 hashes[0] |= (1 << h);
457 else
458 hashes[1] |= (1 << (h - 32));
459
460 ETHER_NEXT_MULTI(step, enm);
461 }
462 }
463
464 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
465 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
466 SK_XM_WRITE_4(sc_if, XM_MODE, reg);
467 }
468
469 void
sk_iff_yukon(struct sk_if_softc * sc_if)470 sk_iff_yukon(struct sk_if_softc *sc_if)
471 {
472 struct ifnet *ifp = &sc_if->arpcom.ac_if;
473 struct arpcom *ac = &sc_if->arpcom;
474 struct ether_multi *enm;
475 struct ether_multistep step;
476 u_int32_t hashes[2];
477 u_int16_t rcr;
478 int h;
479
480 rcr = SK_YU_READ_2(sc_if, YUKON_RCR);
481 rcr &= ~(YU_RCR_MUFLEN | YU_RCR_UFLEN);
482 ifp->if_flags &= ~IFF_ALLMULTI;
483
484 /*
485 * Always accept frames destined to our station address.
486 */
487 rcr |= YU_RCR_UFLEN;
488
489 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) {
490 ifp->if_flags |= IFF_ALLMULTI;
491 if (ifp->if_flags & IFF_PROMISC)
492 rcr &= ~YU_RCR_UFLEN;
493 else
494 rcr |= YU_RCR_MUFLEN;
495 hashes[0] = hashes[1] = 0xFFFFFFFF;
496 } else {
497 rcr |= YU_RCR_MUFLEN;
498 /* Program new filter. */
499 bzero(hashes, sizeof(hashes));
500
501 ETHER_FIRST_MULTI(step, ac, enm);
502 while (enm != NULL) {
503 h = ether_crc32_be(enm->enm_addrlo,
504 ETHER_ADDR_LEN) & ((1 << SK_HASH_BITS) - 1);
505
506 if (h < 32)
507 hashes[0] |= (1 << h);
508 else
509 hashes[1] |= (1 << (h - 32));
510
511 ETHER_NEXT_MULTI(step, enm);
512 }
513 }
514
515 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
516 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
517 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
518 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
519 SK_YU_WRITE_2(sc_if, YUKON_RCR, rcr);
520 }
521
522 int
sk_init_rx_ring(struct sk_if_softc * sc_if)523 sk_init_rx_ring(struct sk_if_softc *sc_if)
524 {
525 struct sk_chain_data *cd = &sc_if->sk_cdata;
526 struct sk_ring_data *rd = sc_if->sk_rdata;
527 int i, nexti;
528
529 bzero(rd->sk_rx_ring, sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
530
531 for (i = 0; i < SK_RX_RING_CNT; i++) {
532 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
533 if (i == (SK_RX_RING_CNT - 1))
534 nexti = 0;
535 else
536 nexti = i + 1;
537 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti];
538 htolem32(&rd->sk_rx_ring[i].sk_next,
539 SK_RX_RING_ADDR(sc_if, nexti));
540 }
541
542 sc_if->sk_cdata.sk_rx_prod = 0;
543 sc_if->sk_cdata.sk_rx_cons = 0;
544
545 if_rxr_init(&sc_if->sk_cdata.sk_rx_ring, 2, SK_RX_RING_CNT);
546
547 sk_fill_rx_ring(sc_if);
548
549 return (0);
550 }
551
552 void
sk_fill_rx_ring(struct sk_if_softc * sc_if)553 sk_fill_rx_ring(struct sk_if_softc *sc_if)
554 {
555 struct if_rxring *rxr = &sc_if->sk_cdata.sk_rx_ring;
556 u_int slots;
557
558 for (slots = if_rxr_get(rxr, SK_RX_RING_CNT); slots > 0; slots--) {
559 if (sk_newbuf(sc_if) == ENOBUFS)
560 break;
561 }
562 if_rxr_put(rxr, slots);
563 }
564
565 int
sk_init_tx_ring(struct sk_if_softc * sc_if)566 sk_init_tx_ring(struct sk_if_softc *sc_if)
567 {
568 struct sk_softc *sc = sc_if->sk_softc;
569 struct sk_chain_data *cd = &sc_if->sk_cdata;
570 struct sk_ring_data *rd = sc_if->sk_rdata;
571 bus_dmamap_t dmamap;
572 struct sk_txmap_entry *entry;
573 int i, nexti;
574
575 bzero(sc_if->sk_rdata->sk_tx_ring,
576 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
577
578 SIMPLEQ_INIT(&sc_if->sk_txmap_head);
579 for (i = 0; i < SK_TX_RING_CNT; i++) {
580 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
581 if (i == (SK_TX_RING_CNT - 1))
582 nexti = 0;
583 else
584 nexti = i + 1;
585 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
586 htolem32(&rd->sk_tx_ring[i].sk_next,
587 SK_TX_RING_ADDR(sc_if, nexti));
588
589 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
590 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap))
591 return (ENOBUFS);
592
593 entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
594 if (!entry) {
595 bus_dmamap_destroy(sc->sc_dmatag, dmamap);
596 return (ENOBUFS);
597 }
598 entry->dmamap = dmamap;
599 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
600 }
601
602 sc_if->sk_cdata.sk_tx_prod = 0;
603 sc_if->sk_cdata.sk_tx_cons = 0;
604 sc_if->sk_cdata.sk_tx_cnt = 0;
605
606 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT,
607 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
608
609 return (0);
610 }
611
612 int
sk_newbuf(struct sk_if_softc * sc_if)613 sk_newbuf(struct sk_if_softc *sc_if)
614 {
615 struct mbuf *m;
616 struct sk_chain *c;
617 struct sk_rx_desc *r;
618 bus_dmamap_t dmamap;
619 u_int prod;
620 int error;
621 uint64_t dva;
622
623 m = MCLGETL(NULL, M_DONTWAIT, SK_JLEN);
624 if (m == NULL)
625 return (ENOBUFS);
626
627 m->m_len = m->m_pkthdr.len = SK_JLEN;
628 m_adj(m, ETHER_ALIGN);
629
630 prod = sc_if->sk_cdata.sk_rx_prod;
631 dmamap = sc_if->sk_cdata.sk_rx_map[prod];
632
633 error = bus_dmamap_load_mbuf(sc_if->sk_softc->sc_dmatag, dmamap, m,
634 BUS_DMA_READ|BUS_DMA_NOWAIT);
635 if (error) {
636 m_freem(m);
637 return (ENOBUFS);
638 }
639
640 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
641 dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
642
643 c = &sc_if->sk_cdata.sk_rx_chain[prod];
644 c->sk_mbuf = m;
645
646 r = c->sk_desc;
647 dva = dmamap->dm_segs[0].ds_addr;
648 htolem32(&r->sk_data_lo, dva);
649 htolem32(&r->sk_data_hi, dva >> 32);
650 htolem32(&r->sk_ctl, dmamap->dm_segs[0].ds_len | SK_RXSTAT);
651
652 SK_CDRXSYNC(sc_if, prod, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
653
654 SK_INC(prod, SK_RX_RING_CNT);
655 sc_if->sk_cdata.sk_rx_prod = prod;
656
657 return (0);
658 }
659
660 /*
661 * Set media options.
662 */
663 int
sk_ifmedia_upd(struct ifnet * ifp)664 sk_ifmedia_upd(struct ifnet *ifp)
665 {
666 struct sk_if_softc *sc_if = ifp->if_softc;
667
668 mii_mediachg(&sc_if->sk_mii);
669 return (0);
670 }
671
672 /*
673 * Report current media status.
674 */
675 void
sk_ifmedia_sts(struct ifnet * ifp,struct ifmediareq * ifmr)676 sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
677 {
678 struct sk_if_softc *sc_if = ifp->if_softc;
679
680 mii_pollstat(&sc_if->sk_mii);
681 ifmr->ifm_active = sc_if->sk_mii.mii_media_active;
682 ifmr->ifm_status = sc_if->sk_mii.mii_media_status;
683 }
684
685 int
sk_ioctl(struct ifnet * ifp,u_long command,caddr_t data)686 sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
687 {
688 struct sk_if_softc *sc_if = ifp->if_softc;
689 struct ifreq *ifr = (struct ifreq *) data;
690 struct mii_data *mii;
691 int s, error = 0;
692
693 s = splnet();
694
695 switch(command) {
696 case SIOCSIFADDR:
697 ifp->if_flags |= IFF_UP;
698 if (!(ifp->if_flags & IFF_RUNNING))
699 sk_init(sc_if);
700 break;
701
702 case SIOCSIFFLAGS:
703 if (ifp->if_flags & IFF_UP) {
704 if (ifp->if_flags & IFF_RUNNING)
705 error = ENETRESET;
706 else
707 sk_init(sc_if);
708 } else {
709 if (ifp->if_flags & IFF_RUNNING)
710 sk_stop(sc_if, 0);
711 }
712 break;
713
714 case SIOCGIFMEDIA:
715 case SIOCSIFMEDIA:
716 mii = &sc_if->sk_mii;
717 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
718 break;
719
720 case SIOCGIFRXR:
721 error = if_rxr_ioctl((struct if_rxrinfo *)ifr->ifr_data,
722 NULL, SK_JLEN, &sc_if->sk_cdata.sk_rx_ring);
723
724 break;
725
726 default:
727 error = ether_ioctl(ifp, &sc_if->arpcom, command, data);
728 }
729
730 if (error == ENETRESET) {
731 if (ifp->if_flags & IFF_RUNNING)
732 sk_iff(sc_if);
733 error = 0;
734 }
735
736 splx(s);
737 return (error);
738 }
739
740 /*
741 * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
742 * IDs against our list and return a device name if we find a match.
743 */
744 int
skc_probe(struct device * parent,void * match,void * aux)745 skc_probe(struct device *parent, void *match, void *aux)
746 {
747 struct pci_attach_args *pa = aux;
748 pci_chipset_tag_t pc = pa->pa_pc;
749 pcireg_t subid;
750
751 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
752
753 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS &&
754 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 &&
755 subid == SK_LINKSYS_EG1032_SUBID)
756 return (1);
757
758 return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices,
759 nitems(skc_devices)));
760 }
761
762 /*
763 * Force the GEnesis into reset, then bring it out of reset.
764 */
765 void
skc_reset(struct sk_softc * sc)766 skc_reset(struct sk_softc *sc)
767 {
768 u_int32_t imtimer_ticks;
769
770 DPRINTFN(2, ("skc_reset\n"));
771
772 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
773 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
774 if (SK_IS_YUKON(sc))
775 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
776
777 DELAY(1000);
778 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
779 DELAY(2);
780 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
781 if (SK_IS_YUKON(sc))
782 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
783
784 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
785 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
786 CSR_READ_2(sc, SK_LINK_CTRL)));
787
788 if (SK_IS_GENESIS(sc)) {
789 /* Configure packet arbiter */
790 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
791 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
792 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
793 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
794 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
795 }
796
797 /* Enable RAM interface */
798 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
799
800 /*
801 * Configure interrupt moderation. The moderation timer
802 * defers interrupts specified in the interrupt moderation
803 * timer mask based on the timeout specified in the interrupt
804 * moderation timer init register. Each bit in the timer
805 * register represents one tick, so to specify a timeout in
806 * microseconds, we have to multiply by the correct number of
807 * ticks-per-microsecond.
808 */
809 switch (sc->sk_type) {
810 case SK_GENESIS:
811 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
812 break;
813 default:
814 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
815 break;
816 }
817 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100));
818 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
819 SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
820 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
821 }
822
823 int
sk_probe(struct device * parent,void * match,void * aux)824 sk_probe(struct device *parent, void *match, void *aux)
825 {
826 struct skc_attach_args *sa = aux;
827
828 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
829 return (0);
830
831 switch (sa->skc_type) {
832 case SK_GENESIS:
833 case SK_YUKON:
834 case SK_YUKON_LITE:
835 case SK_YUKON_LP:
836 return (1);
837 }
838
839 return (0);
840 }
841
842 /*
843 * Each XMAC chip is attached as a separate logical IP interface.
844 * Single port cards will have only one logical interface of course.
845 */
846 void
sk_attach(struct device * parent,struct device * self,void * aux)847 sk_attach(struct device *parent, struct device *self, void *aux)
848 {
849 struct sk_if_softc *sc_if = (struct sk_if_softc *) self;
850 struct sk_softc *sc = (struct sk_softc *)parent;
851 struct skc_attach_args *sa = aux;
852 struct ifnet *ifp;
853 caddr_t kva;
854 int i, error;
855
856 sc_if->sk_port = sa->skc_port;
857 sc_if->sk_softc = sc;
858 sc->sk_if[sa->skc_port] = sc_if;
859
860 if (sa->skc_port == SK_PORT_A)
861 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
862 if (sa->skc_port == SK_PORT_B)
863 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
864
865 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
866
867 /*
868 * Get station address for this interface. Note that
869 * dual port cards actually come with three station
870 * addresses: one for each port, plus an extra. The
871 * extra one is used by the SysKonnect driver software
872 * as a 'virtual' station address for when both ports
873 * are operating in failover mode. Currently we don't
874 * use this extra address.
875 */
876 for (i = 0; i < ETHER_ADDR_LEN; i++)
877 sc_if->arpcom.ac_enaddr[i] =
878 sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
879
880 printf(": address %s\n",
881 ether_sprintf(sc_if->arpcom.ac_enaddr));
882
883 /*
884 * Set up RAM buffer addresses. The NIC will have a certain
885 * amount of SRAM on it, somewhere between 512K and 2MB. We
886 * need to divide this up a) between the transmitter and
887 * receiver and b) between the two XMACs, if this is a
888 * dual port NIC. Our algorithm is to divide up the memory
889 * evenly so that everyone gets a fair share.
890 */
891 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
892 u_int32_t chunk, val;
893
894 chunk = sc->sk_ramsize / 2;
895 val = sc->sk_rboff / sizeof(u_int64_t);
896 sc_if->sk_rx_ramstart = val;
897 val += (chunk / sizeof(u_int64_t));
898 sc_if->sk_rx_ramend = val - 1;
899 sc_if->sk_tx_ramstart = val;
900 val += (chunk / sizeof(u_int64_t));
901 sc_if->sk_tx_ramend = val - 1;
902 } else {
903 u_int32_t chunk, val;
904
905 chunk = sc->sk_ramsize / 4;
906 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
907 sizeof(u_int64_t);
908 sc_if->sk_rx_ramstart = val;
909 val += (chunk / sizeof(u_int64_t));
910 sc_if->sk_rx_ramend = val - 1;
911 sc_if->sk_tx_ramstart = val;
912 val += (chunk / sizeof(u_int64_t));
913 sc_if->sk_tx_ramend = val - 1;
914 }
915
916 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
917 " tx_ramstart=%#x tx_ramend=%#x\n",
918 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
919 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
920
921 /* Read and save PHY type */
922 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
923
924 /* Set PHY address */
925 if (SK_IS_GENESIS(sc)) {
926 switch (sc_if->sk_phytype) {
927 case SK_PHYTYPE_XMAC:
928 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
929 break;
930 case SK_PHYTYPE_BCOM:
931 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
932 break;
933 default:
934 printf("%s: unsupported PHY type: %d\n",
935 sc->sk_dev.dv_xname, sc_if->sk_phytype);
936 return;
937 }
938 }
939
940 if (SK_IS_YUKON(sc)) {
941 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
942 sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
943 /* not initialized, punt */
944 sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
945
946 sc->sk_coppertype = 1;
947 }
948
949 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
950
951 if (!(sc->sk_coppertype))
952 sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
953 }
954
955 /* Allocate the descriptor queues. */
956 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data),
957 PAGE_SIZE, 0, &sc_if->sk_ring_seg, 1, &sc_if->sk_ring_nseg,
958 BUS_DMA_NOWAIT | BUS_DMA_ZERO)) {
959 printf(": can't alloc rx buffers\n");
960 goto fail;
961 }
962 if (bus_dmamem_map(sc->sc_dmatag, &sc_if->sk_ring_seg,
963 sc_if->sk_ring_nseg, sizeof(struct sk_ring_data),
964 &kva, BUS_DMA_NOWAIT)) {
965 printf(": can't map dma buffers (%lu bytes)\n",
966 (ulong)sizeof(struct sk_ring_data));
967 goto fail_1;
968 }
969 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1,
970 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT,
971 &sc_if->sk_ring_map)) {
972 printf(": can't create dma map\n");
973 goto fail_2;
974 }
975 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
976 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) {
977 printf(": can't load dma map\n");
978 goto fail_3;
979 }
980 sc_if->sk_rdata = (struct sk_ring_data *)kva;
981
982 for (i = 0; i < SK_RX_RING_CNT; i++) {
983 error = bus_dmamap_create(sc->sc_dmatag, SK_JLEN, 1,
984 SK_JLEN, 0, 0, &sc_if->sk_cdata.sk_rx_map[i]);
985 if (error != 0) {
986 printf(": unable to create rx DMA map %d, "
987 "error = %d\n", i, error);
988 goto fail_4;
989 }
990 }
991
992 ifp = &sc_if->arpcom.ac_if;
993 ifp->if_softc = sc_if;
994 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
995 ifp->if_ioctl = sk_ioctl;
996 ifp->if_start = sk_start;
997 ifp->if_watchdog = sk_watchdog;
998 ifp->if_hardmtu = SK_JUMBO_MTU;
999 ifq_init_maxlen(&ifp->if_snd, SK_TX_RING_CNT - 1);
1000 bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
1001
1002 ifp->if_capabilities = IFCAP_VLAN_MTU;
1003
1004 if (sk_reset(sc_if) == -1) {
1005 printf(": unknown device type %d\n", sc_if->sk_softc->sk_type);
1006 /* dealloc jumbo on error */
1007 goto fail_3;
1008 }
1009
1010 DPRINTFN(2, ("sk_attach: 1\n"));
1011
1012 sc_if->sk_mii.mii_ifp = ifp;
1013 if (SK_IS_GENESIS(sc)) {
1014 sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg;
1015 sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg;
1016 sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg;
1017 } else {
1018 sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg;
1019 sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg;
1020 sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg;
1021 }
1022
1023 ifmedia_init(&sc_if->sk_mii.mii_media, 0,
1024 sk_ifmedia_upd, sk_ifmedia_sts);
1025 if (SK_IS_GENESIS(sc)) {
1026 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
1027 MII_OFFSET_ANY, 0);
1028 } else {
1029 mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
1030 MII_OFFSET_ANY, MIIF_DOPAUSE);
1031 }
1032 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
1033 printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname);
1034 ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
1035 0, NULL);
1036 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL);
1037 } else
1038 ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
1039
1040 if (SK_IS_GENESIS(sc)) {
1041 timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if);
1042 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1043 } else
1044 timeout_set(&sc_if->sk_tick_ch, sk_yukon_tick, sc_if);
1045
1046 /*
1047 * Call MI attach routines.
1048 */
1049 if_attach(ifp);
1050 ether_ifattach(ifp);
1051
1052 DPRINTFN(2, ("sk_attach: end\n"));
1053 return;
1054 fail_4:
1055 for (i = 0; i < SK_RX_RING_CNT; i++) {
1056 if (sc_if->sk_cdata.sk_rx_map[i] == NULL)
1057 continue;
1058
1059 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_map[i]);
1060 }
1061 fail_3:
1062 bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data));
1063 fail_2:
1064 bus_dmamem_free(sc->sc_dmatag, &sc_if->sk_ring_seg, sc_if->sk_ring_nseg);
1065 fail_1:
1066 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1067 fail:
1068 sc->sk_if[sa->skc_port] = NULL;
1069 }
1070
1071 int
sk_reset(struct sk_if_softc * sc_if)1072 sk_reset(struct sk_if_softc *sc_if)
1073 {
1074 /*
1075 * Do miibus setup.
1076 */
1077 switch (sc_if->sk_softc->sk_type) {
1078 case SK_GENESIS:
1079 sk_init_xmac(sc_if);
1080 break;
1081 case SK_YUKON:
1082 case SK_YUKON_LITE:
1083 case SK_YUKON_LP:
1084 sk_init_yukon(sc_if);
1085 break;
1086 default:
1087 return (-1);
1088 }
1089 return (0);
1090 }
1091
1092 int
sk_detach(struct device * self,int flags)1093 sk_detach(struct device *self, int flags)
1094 {
1095 struct sk_if_softc *sc_if = (struct sk_if_softc *)self;
1096 struct sk_softc *sc = sc_if->sk_softc;
1097 struct ifnet *ifp= &sc_if->arpcom.ac_if;
1098
1099 if (sc->sk_if[sc_if->sk_port] == NULL)
1100 return (0);
1101
1102 sk_stop(sc_if, 1);
1103
1104 /* Detach any PHYs we might have. */
1105 if (LIST_FIRST(&sc_if->sk_mii.mii_phys) != NULL)
1106 mii_detach(&sc_if->sk_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1107
1108 /* Delete any remaining media. */
1109 ifmedia_delete_instance(&sc_if->sk_mii.mii_media, IFM_INST_ANY);
1110
1111 ether_ifdetach(ifp);
1112 if_detach(ifp);
1113
1114 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc_if->sk_rdata,
1115 sizeof(struct sk_ring_data));
1116 bus_dmamem_free(sc->sc_dmatag,
1117 &sc_if->sk_ring_seg, sc_if->sk_ring_nseg);
1118 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1119 sc->sk_if[sc_if->sk_port] = NULL;
1120
1121 return (0);
1122 }
1123
1124 int
sk_activate(struct device * self,int act)1125 sk_activate(struct device *self, int act)
1126 {
1127 struct sk_if_softc *sc_if = (void *)self;
1128 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1129
1130 switch (act) {
1131 case DVACT_RESUME:
1132 sk_reset(sc_if);
1133 if (ifp->if_flags & IFF_RUNNING)
1134 sk_init(sc_if);
1135 break;
1136 }
1137 return (0);
1138 }
1139
1140 int
skcprint(void * aux,const char * pnp)1141 skcprint(void *aux, const char *pnp)
1142 {
1143 struct skc_attach_args *sa = aux;
1144
1145 if (pnp)
1146 printf("sk port %c at %s",
1147 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
1148 else
1149 printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
1150 return (UNCONF);
1151 }
1152
1153 /*
1154 * Attach the interface. Allocate softc structures, do ifmedia
1155 * setup and ethernet/BPF attach.
1156 */
1157 void
skc_attach(struct device * parent,struct device * self,void * aux)1158 skc_attach(struct device *parent, struct device *self, void *aux)
1159 {
1160 struct sk_softc *sc = (struct sk_softc *)self;
1161 struct pci_attach_args *pa = aux;
1162 struct skc_attach_args skca;
1163 pci_chipset_tag_t pc = pa->pa_pc;
1164 pcireg_t memtype;
1165 pci_intr_handle_t ih;
1166 const char *intrstr = NULL;
1167 u_int8_t skrs;
1168 char *revstr = NULL;
1169
1170 DPRINTFN(2, ("begin skc_attach\n"));
1171
1172 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
1173
1174 /*
1175 * Map control/status registers.
1176 */
1177 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
1178 if (pci_mapreg_map(pa, SK_PCI_LOMEM, memtype, 0, &sc->sk_btag,
1179 &sc->sk_bhandle, NULL, &sc->sk_bsize, 0)) {
1180 printf(": can't map mem space\n");
1181 return;
1182 }
1183
1184 sc->sc_dmatag = pa->pa_dmat;
1185
1186 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1187 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1188 sc->sk_pc = pc;
1189
1190 /* bail out here if chip is not recognized */
1191 if (! SK_IS_GENESIS(sc) && ! SK_IS_YUKON(sc)) {
1192 printf(": unknown chip type: %d\n", sc->sk_type);
1193 goto fail_1;
1194 }
1195 DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1196
1197 /* Allocate interrupt */
1198 if (pci_intr_map(pa, &ih)) {
1199 printf(": couldn't map interrupt\n");
1200 goto fail_1;
1201 }
1202
1203 intrstr = pci_intr_string(pc, ih);
1204 sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc,
1205 self->dv_xname);
1206 if (sc->sk_intrhand == NULL) {
1207 printf(": couldn't establish interrupt");
1208 if (intrstr != NULL)
1209 printf(" at %s", intrstr);
1210 printf("\n");
1211 goto fail_1;
1212 }
1213
1214 /* Reset the adapter. */
1215 skc_reset(sc);
1216
1217 skrs = sk_win_read_1(sc, SK_EPROM0);
1218 if (SK_IS_GENESIS(sc)) {
1219 /* Read and save RAM size and RAMbuffer offset */
1220 switch(skrs) {
1221 case SK_RAMSIZE_512K_64:
1222 sc->sk_ramsize = 0x80000;
1223 sc->sk_rboff = SK_RBOFF_0;
1224 break;
1225 case SK_RAMSIZE_1024K_64:
1226 sc->sk_ramsize = 0x100000;
1227 sc->sk_rboff = SK_RBOFF_80000;
1228 break;
1229 case SK_RAMSIZE_1024K_128:
1230 sc->sk_ramsize = 0x100000;
1231 sc->sk_rboff = SK_RBOFF_0;
1232 break;
1233 case SK_RAMSIZE_2048K_128:
1234 sc->sk_ramsize = 0x200000;
1235 sc->sk_rboff = SK_RBOFF_0;
1236 break;
1237 default:
1238 printf(": unknown ram size: %d\n", skrs);
1239 goto fail_2;
1240 break;
1241 }
1242 } else {
1243 if (skrs == 0x00)
1244 sc->sk_ramsize = 0x20000;
1245 else
1246 sc->sk_ramsize = skrs * (1<<12);
1247 sc->sk_rboff = SK_RBOFF_0;
1248 }
1249
1250 DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
1251 sc->sk_ramsize, sc->sk_ramsize / 1024, sc->sk_rboff));
1252
1253 /* Read and save physical media type */
1254 sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
1255
1256 if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
1257 sc->sk_coppertype = 1;
1258 else
1259 sc->sk_coppertype = 0;
1260
1261 switch (sc->sk_type) {
1262 case SK_GENESIS:
1263 sc->sk_name = "GEnesis";
1264 break;
1265 case SK_YUKON:
1266 sc->sk_name = "Yukon";
1267 break;
1268 case SK_YUKON_LITE:
1269 sc->sk_name = "Yukon Lite";
1270 break;
1271 case SK_YUKON_LP:
1272 sc->sk_name = "Yukon LP";
1273 break;
1274 default:
1275 sc->sk_name = "Yukon (Unknown)";
1276 }
1277
1278 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1279 if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
1280 u_int32_t flashaddr;
1281 u_int8_t testbyte;
1282
1283 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1284
1285 /* test Flash-Address Register */
1286 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1287 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1288
1289 if (testbyte != 0) {
1290 /* This is a Yukon Lite Rev A0 */
1291 sc->sk_type = SK_YUKON_LITE;
1292 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1293 /* restore Flash-Address Register */
1294 sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1295 }
1296 }
1297
1298 if (sc->sk_type == SK_YUKON_LITE) {
1299 switch (sc->sk_rev) {
1300 case SK_YUKON_LITE_REV_A0:
1301 revstr = "A0";
1302 break;
1303 case SK_YUKON_LITE_REV_A1:
1304 revstr = "A1";
1305 break;
1306 case SK_YUKON_LITE_REV_A3:
1307 revstr = "A3";
1308 break;
1309 default:
1310 ;
1311 }
1312 }
1313
1314 /* Announce the product name. */
1315 printf(", %s", sc->sk_name);
1316 if (revstr != NULL)
1317 printf(" rev. %s", revstr);
1318 printf(" (0x%x): %s\n", sc->sk_rev, intrstr);
1319
1320 sc->sk_macs = 1;
1321
1322 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC))
1323 sc->sk_macs++;
1324
1325 skca.skc_port = SK_PORT_A;
1326 skca.skc_type = sc->sk_type;
1327 skca.skc_rev = sc->sk_rev;
1328 (void)config_found(&sc->sk_dev, &skca, skcprint);
1329
1330 if (sc->sk_macs > 1) {
1331 skca.skc_port = SK_PORT_B;
1332 skca.skc_type = sc->sk_type;
1333 skca.skc_rev = sc->sk_rev;
1334 (void)config_found(&sc->sk_dev, &skca, skcprint);
1335 }
1336
1337 /* Turn on the 'driver is loaded' LED. */
1338 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1339
1340 return;
1341
1342 fail_2:
1343 pci_intr_disestablish(pc, sc->sk_intrhand);
1344 fail_1:
1345 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize);
1346 }
1347
1348 int
skc_detach(struct device * self,int flags)1349 skc_detach(struct device *self, int flags)
1350 {
1351 struct sk_softc *sc = (struct sk_softc *)self;
1352 int rv;
1353
1354 if (sc->sk_intrhand)
1355 pci_intr_disestablish(sc->sk_pc, sc->sk_intrhand);
1356
1357 rv = config_detach_children(self, flags);
1358 if (rv != 0)
1359 return (rv);
1360
1361 if (sc->sk_bsize > 0)
1362 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, sc->sk_bsize);
1363
1364 return(0);
1365 }
1366
1367 int
skc_activate(struct device * self,int act)1368 skc_activate(struct device *self, int act)
1369 {
1370 struct sk_softc *sc = (void *)self;
1371 int rv = 0;
1372
1373 switch (act) {
1374 case DVACT_RESUME:
1375 skc_reset(sc);
1376 rv = config_activate_children(self, act);
1377 break;
1378 default:
1379 rv = config_activate_children(self, act);
1380 break;
1381 }
1382 return (rv);
1383 }
1384
1385 int
sk_encap(struct sk_if_softc * sc_if,struct mbuf * m_head,u_int32_t * txidx)1386 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
1387 {
1388 struct sk_softc *sc = sc_if->sk_softc;
1389 struct sk_tx_desc *f = NULL;
1390 u_int32_t frag, cur, sk_ctl;
1391 int i;
1392 struct sk_txmap_entry *entry;
1393 bus_dmamap_t txmap;
1394 uint64_t dva;
1395
1396 DPRINTFN(2, ("sk_encap\n"));
1397
1398 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
1399 if (entry == NULL) {
1400 DPRINTFN(2, ("sk_encap: no txmap available\n"));
1401 return (ENOBUFS);
1402 }
1403 txmap = entry->dmamap;
1404
1405 cur = frag = *txidx;
1406
1407 switch (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1408 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)) {
1409 case 0:
1410 break;
1411
1412 case EFBIG: /* mbuf chain is too fragmented */
1413 if (m_defrag(m_head, M_DONTWAIT) == 0 &&
1414 bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1415 BUS_DMA_STREAMING | BUS_DMA_NOWAIT) == 0)
1416 break;
1417 default:
1418 return (1);
1419 }
1420
1421 /* Sync the DMA map. */
1422 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1423 BUS_DMASYNC_PREWRITE);
1424
1425 for (i = 0; i < txmap->dm_nsegs; i++) {
1426 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1427 dva = txmap->dm_segs[i].ds_addr;
1428 htolem32(&f->sk_data_lo, dva);
1429 htolem32(&f->sk_data_hi, dva >> 32);
1430 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT;
1431 if (i == 0)
1432 sk_ctl |= SK_TXCTL_FIRSTFRAG;
1433 else
1434 sk_ctl |= SK_TXCTL_OWN;
1435 htolem32(&f->sk_ctl, sk_ctl);
1436 cur = frag;
1437 SK_INC(frag, SK_TX_RING_CNT);
1438 }
1439
1440 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1441 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
1442
1443 sc_if->sk_cdata.sk_tx_map[cur] = entry;
1444 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1445 htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
1446
1447 /* Sync descriptors before handing to chip */
1448 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
1449 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1450
1451 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |=
1452 htole32(SK_TXCTL_OWN);
1453
1454 /* Sync first descriptor to hand it off */
1455 SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1456
1457 sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
1458
1459 #ifdef SK_DEBUG
1460 if (skdebug >= 2) {
1461 struct sk_tx_desc *desc;
1462 u_int32_t idx;
1463 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1464 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1465 sk_dump_txdesc(desc, idx);
1466 }
1467 }
1468 #endif
1469
1470 *txidx = frag;
1471
1472 DPRINTFN(2, ("sk_encap: completed successfully\n"));
1473
1474 return (0);
1475 }
1476
1477 void
sk_start(struct ifnet * ifp)1478 sk_start(struct ifnet *ifp)
1479 {
1480 struct sk_if_softc *sc_if = ifp->if_softc;
1481 struct sk_softc *sc = sc_if->sk_softc;
1482 struct mbuf *m_head = NULL;
1483 u_int32_t idx = sc_if->sk_cdata.sk_tx_prod;
1484 int post = 0;
1485
1486 DPRINTFN(2, ("sk_start\n"));
1487
1488 for (;;) {
1489 if (sc_if->sk_cdata.sk_tx_cnt + SK_NTXSEG + 1 >
1490 SK_TX_RING_CNT) {
1491 ifq_set_oactive(&ifp->if_snd);
1492 break;
1493 }
1494
1495 m_head = ifq_dequeue(&ifp->if_snd);
1496 if (m_head == NULL)
1497 break;
1498
1499 /*
1500 * Pack the data into the transmit ring. If we
1501 * don't have room, set the OACTIVE flag and wait
1502 * for the NIC to drain the ring.
1503 */
1504 if (sk_encap(sc_if, m_head, &idx)) {
1505 m_freem(m_head);
1506 continue;
1507 }
1508
1509 /* now we are committed to transmit the packet */
1510
1511 /*
1512 * If there's a BPF listener, bounce a copy of this frame
1513 * to him.
1514 */
1515 #if NBPFILTER > 0
1516 if (ifp->if_bpf)
1517 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
1518 #endif
1519
1520 post = 1;
1521 }
1522 if (post == 0)
1523 return;
1524
1525 /* Transmit */
1526 sc_if->sk_cdata.sk_tx_prod = idx;
1527 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1528
1529 /* Set a timeout in case the chip goes out to lunch. */
1530 ifp->if_timer = SK_TX_TIMEOUT;
1531 }
1532
1533
1534 void
sk_watchdog(struct ifnet * ifp)1535 sk_watchdog(struct ifnet *ifp)
1536 {
1537 struct sk_if_softc *sc_if = ifp->if_softc;
1538
1539 /*
1540 * Reclaim first as there is a possibility of losing Tx completion
1541 * interrupts.
1542 */
1543 sk_txeof(sc_if);
1544 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1545 printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname);
1546
1547 ifp->if_oerrors++;
1548
1549 sk_init(sc_if);
1550 }
1551 }
1552
1553 static __inline int
sk_rxvalid(struct sk_softc * sc,u_int32_t stat,u_int32_t len)1554 sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
1555 {
1556 if (sc->sk_type == SK_GENESIS) {
1557 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
1558 XM_RXSTAT_BYTES(stat) != len)
1559 return (0);
1560 } else {
1561 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
1562 YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
1563 YU_RXSTAT_JABBER)) != 0 ||
1564 (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
1565 YU_RXSTAT_BYTES(stat) != len)
1566 return (0);
1567 }
1568
1569 return (1);
1570 }
1571
1572 void
sk_rxeof(struct sk_if_softc * sc_if)1573 sk_rxeof(struct sk_if_softc *sc_if)
1574 {
1575 struct sk_softc *sc = sc_if->sk_softc;
1576 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1577 struct if_rxring *rxr = &sc_if->sk_cdata.sk_rx_ring;
1578 struct mbuf *m;
1579 struct mbuf_list ml = MBUF_LIST_INITIALIZER();
1580 struct sk_chain *cur_rx;
1581 struct sk_rx_desc *cur_desc;
1582 int cur, total_len = 0;
1583 u_int32_t rxstat, sk_ctl;
1584 bus_dmamap_t dmamap;
1585
1586 DPRINTFN(2, ("sk_rxeof\n"));
1587
1588 cur = sc_if->sk_cdata.sk_rx_cons;
1589 while (if_rxr_inuse(rxr) > 0) {
1590 /* Sync the descriptor */
1591 SK_CDRXSYNC(sc_if, cur,
1592 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1593
1594 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
1595 if (cur_rx->sk_mbuf == NULL)
1596 break;
1597
1598 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur];
1599 sk_ctl = lemtoh32(&cur_desc->sk_ctl);
1600 if ((sk_ctl & SK_RXCTL_OWN) != 0)
1601 break;
1602
1603 dmamap = sc_if->sk_cdata.sk_rx_map[cur];
1604
1605 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
1606 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
1607 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap);
1608
1609 m = cur_rx->sk_mbuf;
1610 cur_rx->sk_mbuf = NULL;
1611 if_rxr_put(rxr, 1);
1612 SK_INC(cur, SK_RX_RING_CNT);
1613
1614 total_len = SK_RXBYTES(sk_ctl);
1615 rxstat = lemtoh32(&cur_desc->sk_xmac_rxstat);
1616
1617 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
1618 SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
1619 SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
1620 total_len < SK_MIN_FRAMELEN ||
1621 total_len > SK_JUMBO_FRAMELEN ||
1622 sk_rxvalid(sc, rxstat, total_len) == 0) {
1623 ifp->if_ierrors++;
1624 m_freem(m);
1625 continue;
1626 }
1627
1628 m->m_pkthdr.len = m->m_len = total_len;
1629
1630 ml_enqueue(&ml, m);
1631 }
1632 sc_if->sk_cdata.sk_rx_cons = cur;
1633
1634 if (ifiq_input(&ifp->if_rcv, &ml))
1635 if_rxr_livelocked(rxr);
1636
1637 sk_fill_rx_ring(sc_if);
1638
1639 }
1640
1641 void
sk_txeof(struct sk_if_softc * sc_if)1642 sk_txeof(struct sk_if_softc *sc_if)
1643 {
1644 struct sk_softc *sc = sc_if->sk_softc;
1645 struct sk_tx_desc *cur_tx;
1646 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1647 u_int32_t idx, sk_ctl;
1648 struct sk_txmap_entry *entry;
1649
1650 DPRINTFN(2, ("sk_txeof\n"));
1651
1652 /*
1653 * Go through our tx ring and free mbufs for those
1654 * frames that have been sent.
1655 */
1656 idx = sc_if->sk_cdata.sk_tx_cons;
1657 while (idx != sc_if->sk_cdata.sk_tx_prod) {
1658 SK_CDTXSYNC(sc_if, idx, 1,
1659 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1660
1661 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
1662 sk_ctl = lemtoh32(&cur_tx->sk_ctl);
1663 #ifdef SK_DEBUG
1664 if (skdebug >= 2)
1665 sk_dump_txdesc(cur_tx, idx);
1666 #endif
1667 if (sk_ctl & SK_TXCTL_OWN) {
1668 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD);
1669 break;
1670 }
1671 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
1672 entry = sc_if->sk_cdata.sk_tx_map[idx];
1673
1674 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
1675 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
1676
1677 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
1678 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1679
1680 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
1681 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
1682 link);
1683 sc_if->sk_cdata.sk_tx_map[idx] = NULL;
1684 }
1685 sc_if->sk_cdata.sk_tx_cnt--;
1686 SK_INC(idx, SK_TX_RING_CNT);
1687 }
1688 ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? SK_TX_TIMEOUT : 0;
1689
1690 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
1691 ifq_clr_oactive(&ifp->if_snd);
1692
1693 sc_if->sk_cdata.sk_tx_cons = idx;
1694 }
1695
1696 void
sk_tick(void * xsc_if)1697 sk_tick(void *xsc_if)
1698 {
1699 struct sk_if_softc *sc_if = xsc_if;
1700 struct mii_data *mii = &sc_if->sk_mii;
1701 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1702 int i;
1703
1704 DPRINTFN(2, ("sk_tick\n"));
1705
1706 if (!(ifp->if_flags & IFF_UP))
1707 return;
1708
1709 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1710 sk_intr_bcom(sc_if);
1711 return;
1712 }
1713
1714 /*
1715 * According to SysKonnect, the correct way to verify that
1716 * the link has come back up is to poll bit 0 of the GPIO
1717 * register three times. This pin has the signal from the
1718 * link sync pin connected to it; if we read the same link
1719 * state 3 times in a row, we know the link is up.
1720 */
1721 for (i = 0; i < 3; i++) {
1722 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
1723 break;
1724 }
1725
1726 if (i != 3) {
1727 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1728 return;
1729 }
1730
1731 /* Turn the GP0 interrupt back on. */
1732 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1733 SK_XM_READ_2(sc_if, XM_ISR);
1734 mii_tick(mii);
1735 timeout_del(&sc_if->sk_tick_ch);
1736 }
1737
1738 void
sk_yukon_tick(void * xsc_if)1739 sk_yukon_tick(void *xsc_if)
1740 {
1741 struct sk_if_softc *sc_if = xsc_if;
1742 struct mii_data *mii = &sc_if->sk_mii;
1743 int s;
1744
1745 s = splnet();
1746 mii_tick(mii);
1747 splx(s);
1748 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1749 }
1750
1751 void
sk_intr_bcom(struct sk_if_softc * sc_if)1752 sk_intr_bcom(struct sk_if_softc *sc_if)
1753 {
1754 struct mii_data *mii = &sc_if->sk_mii;
1755 struct ifnet *ifp = &sc_if->arpcom.ac_if;
1756 int status;
1757
1758 DPRINTFN(2, ("sk_intr_bcom\n"));
1759
1760 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1761
1762 /*
1763 * Read the PHY interrupt register to make sure
1764 * we clear any pending interrupts.
1765 */
1766 status = sk_xmac_miibus_readreg((struct device *)sc_if,
1767 SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
1768
1769 if (!(ifp->if_flags & IFF_RUNNING)) {
1770 sk_init_xmac(sc_if);
1771 return;
1772 }
1773
1774 if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
1775 int lstat;
1776 lstat = sk_xmac_miibus_readreg((struct device *)sc_if,
1777 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS);
1778
1779 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
1780 mii_mediachg(mii);
1781 /* Turn off the link LED. */
1782 SK_IF_WRITE_1(sc_if, 0,
1783 SK_LINKLED1_CTL, SK_LINKLED_OFF);
1784 sc_if->sk_link = 0;
1785 } else if (status & BRGPHY_ISR_LNK_CHG) {
1786 sk_xmac_miibus_writereg((struct device *)sc_if,
1787 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00);
1788 mii_tick(mii);
1789 sc_if->sk_link = 1;
1790 /* Turn on the link LED. */
1791 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
1792 SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
1793 SK_LINKLED_BLINK_OFF);
1794 } else {
1795 mii_tick(mii);
1796 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1797 }
1798 }
1799
1800 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
1801 }
1802
1803 void
sk_intr_xmac(struct sk_if_softc * sc_if)1804 sk_intr_xmac(struct sk_if_softc *sc_if)
1805 {
1806 u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR);
1807
1808 DPRINTFN(2, ("sk_intr_xmac\n"));
1809
1810 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
1811 if (status & XM_ISR_GP0_SET) {
1812 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
1813 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1814 }
1815
1816 if (status & XM_ISR_AUTONEG_DONE) {
1817 timeout_add_sec(&sc_if->sk_tick_ch, 1);
1818 }
1819 }
1820
1821 if (status & XM_IMR_TX_UNDERRUN)
1822 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
1823
1824 if (status & XM_IMR_RX_OVERRUN)
1825 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
1826 }
1827
1828 void
sk_intr_yukon(struct sk_if_softc * sc_if)1829 sk_intr_yukon(struct sk_if_softc *sc_if)
1830 {
1831 u_int8_t status;
1832
1833 status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
1834 /* RX overrun */
1835 if ((status & SK_GMAC_INT_RX_OVER) != 0) {
1836 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
1837 SK_RFCTL_RX_FIFO_OVER);
1838 }
1839 /* TX underrun */
1840 if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
1841 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
1842 SK_TFCTL_TX_FIFO_UNDER);
1843 }
1844
1845 DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
1846 }
1847
1848 int
sk_intr(void * xsc)1849 sk_intr(void *xsc)
1850 {
1851 struct sk_softc *sc = xsc;
1852 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
1853 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
1854 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
1855 u_int32_t status;
1856 int claimed = 0;
1857
1858 status = CSR_READ_4(sc, SK_ISSR);
1859 if (status == 0 || status == 0xffffffff)
1860 return (0);
1861
1862 if (sc_if0 != NULL)
1863 ifp0 = &sc_if0->arpcom.ac_if;
1864 if (sc_if1 != NULL)
1865 ifp1 = &sc_if1->arpcom.ac_if;
1866
1867 for (; (status &= sc->sk_intrmask) != 0;) {
1868 claimed = 1;
1869
1870 /* Handle receive interrupts first. */
1871 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
1872 sk_rxeof(sc_if0);
1873 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
1874 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1875 }
1876 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
1877 sk_rxeof(sc_if1);
1878 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
1879 SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
1880 }
1881
1882 /* Then transmit interrupts. */
1883 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
1884 sk_txeof(sc_if0);
1885 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
1886 SK_TXBMU_CLR_IRQ_EOF);
1887 }
1888 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
1889 sk_txeof(sc_if1);
1890 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
1891 SK_TXBMU_CLR_IRQ_EOF);
1892 }
1893
1894 /* Then MAC interrupts. */
1895 if (sc_if0 && (status & SK_ISR_MAC1) &&
1896 (ifp0->if_flags & IFF_RUNNING)) {
1897 if (SK_IS_GENESIS(sc))
1898 sk_intr_xmac(sc_if0);
1899 else
1900 sk_intr_yukon(sc_if0);
1901 }
1902
1903 if (sc_if1 && (status & SK_ISR_MAC2) &&
1904 (ifp1->if_flags & IFF_RUNNING)) {
1905 if (SK_IS_GENESIS(sc))
1906 sk_intr_xmac(sc_if1);
1907 else
1908 sk_intr_yukon(sc_if1);
1909
1910 }
1911
1912 if (status & SK_ISR_EXTERNAL_REG) {
1913 if (sc_if0 != NULL &&
1914 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
1915 sk_intr_bcom(sc_if0);
1916
1917 if (sc_if1 != NULL &&
1918 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
1919 sk_intr_bcom(sc_if1);
1920 }
1921 status = CSR_READ_4(sc, SK_ISSR);
1922 }
1923
1924 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
1925
1926 if (ifp0 != NULL && !ifq_empty(&ifp0->if_snd))
1927 sk_start(ifp0);
1928 if (ifp1 != NULL && !ifq_empty(&ifp1->if_snd))
1929 sk_start(ifp1);
1930
1931 return (claimed);
1932 }
1933
1934 void
sk_init_xmac(struct sk_if_softc * sc_if)1935 sk_init_xmac(struct sk_if_softc *sc_if)
1936 {
1937 struct sk_softc *sc = sc_if->sk_softc;
1938 struct sk_bcom_hack bhack[] = {
1939 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
1940 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
1941 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1942 { 0, 0 } };
1943
1944 DPRINTFN(2, ("sk_init_xmac\n"));
1945
1946 /* Unreset the XMAC. */
1947 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
1948 DELAY(1000);
1949
1950 /* Reset the XMAC's internal state. */
1951 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
1952
1953 /* Save the XMAC II revision */
1954 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
1955
1956 /*
1957 * Perform additional initialization for external PHYs,
1958 * namely for the 1000baseTX cards that use the XMAC's
1959 * GMII mode.
1960 */
1961 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
1962 int i = 0;
1963 u_int32_t val;
1964
1965 /* Take PHY out of reset. */
1966 val = sk_win_read_4(sc, SK_GPIO);
1967 if (sc_if->sk_port == SK_PORT_A)
1968 val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
1969 else
1970 val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
1971 sk_win_write_4(sc, SK_GPIO, val);
1972
1973 /* Enable GMII mode on the XMAC. */
1974 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
1975
1976 sk_xmac_miibus_writereg((struct device *)sc_if,
1977 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET);
1978 DELAY(10000);
1979 sk_xmac_miibus_writereg((struct device *)sc_if,
1980 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0);
1981
1982 /*
1983 * Early versions of the BCM5400 apparently have
1984 * a bug that requires them to have their reserved
1985 * registers initialized to some magic values. I don't
1986 * know what the numbers do, I'm just the messenger.
1987 */
1988 if (sk_xmac_miibus_readreg((struct device *)sc_if,
1989 SK_PHYADDR_BCOM, 0x03) == 0x6041) {
1990 while(bhack[i].reg) {
1991 sk_xmac_miibus_writereg((struct device *)sc_if,
1992 SK_PHYADDR_BCOM, bhack[i].reg,
1993 bhack[i].val);
1994 i++;
1995 }
1996 }
1997 }
1998
1999 /* Set station address */
2000 SK_XM_WRITE_2(sc_if, XM_PAR0,
2001 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])));
2002 SK_XM_WRITE_2(sc_if, XM_PAR1,
2003 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])));
2004 SK_XM_WRITE_2(sc_if, XM_PAR2,
2005 letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])));
2006
2007 /* We don't need the FCS appended to the packet. */
2008 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2009
2010 /* We want short frames padded to 60 bytes. */
2011 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2012
2013 /*
2014 * Enable the reception of all error frames. This is
2015 * a necessary evil due to the design of the XMAC. The
2016 * XMAC's receive FIFO is only 8K in size, however jumbo
2017 * frames can be up to 9000 bytes in length. When bad
2018 * frame filtering is enabled, the XMAC's RX FIFO operates
2019 * in 'store and forward' mode. For this to work, the
2020 * entire frame has to fit into the FIFO, but that means
2021 * that jumbo frames larger than 8192 bytes will be
2022 * truncated. Disabling all bad frame filtering causes
2023 * the RX FIFO to operate in streaming mode, in which
2024 * case the XMAC will start transferring frames out of the
2025 * RX FIFO as soon as the FIFO threshold is reached.
2026 */
2027 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
2028 XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
2029 XM_MODE_RX_INRANGELEN);
2030
2031 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2032
2033 /*
2034 * Bump up the transmit threshold. This helps hold off transmit
2035 * underruns when we're blasting traffic from both ports at once.
2036 */
2037 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2038
2039 /* Program promiscuous mode and multicast filters. */
2040 sk_iff(sc_if);
2041
2042 /* Clear and enable interrupts */
2043 SK_XM_READ_2(sc_if, XM_ISR);
2044 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2045 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2046 else
2047 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2048
2049 /* Configure MAC arbiter */
2050 switch(sc_if->sk_xmac_rev) {
2051 case XM_XMAC_REV_B2:
2052 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2053 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2054 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2055 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2056 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2057 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2058 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2059 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2060 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2061 break;
2062 case XM_XMAC_REV_C1:
2063 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2064 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2065 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2066 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2067 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2068 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2069 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2070 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2071 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2072 break;
2073 default:
2074 break;
2075 }
2076 sk_win_write_2(sc, SK_MACARB_CTL,
2077 SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
2078
2079 sc_if->sk_link = 1;
2080 }
2081
2082 void
sk_init_yukon(struct sk_if_softc * sc_if)2083 sk_init_yukon(struct sk_if_softc *sc_if)
2084 {
2085 u_int32_t phy, v;
2086 u_int16_t reg;
2087 struct sk_softc *sc;
2088 int i;
2089
2090 sc = sc_if->sk_softc;
2091
2092 DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
2093 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2094
2095 if (sc->sk_type == SK_YUKON_LITE &&
2096 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2097 /*
2098 * Workaround code for COMA mode, set PHY reset.
2099 * Otherwise it will not correctly take chip out of
2100 * powerdown (coma)
2101 */
2102 v = sk_win_read_4(sc, SK_GPIO);
2103 v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
2104 sk_win_write_4(sc, SK_GPIO, v);
2105 }
2106
2107 DPRINTFN(6, ("sk_init_yukon: 1\n"));
2108
2109 /* GMAC and GPHY Reset */
2110 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2111 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2112 DELAY(1000);
2113
2114 DPRINTFN(6, ("sk_init_yukon: 2\n"));
2115
2116 if (sc->sk_type == SK_YUKON_LITE &&
2117 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2118 /*
2119 * Workaround code for COMA mode, clear PHY reset
2120 */
2121 v = sk_win_read_4(sc, SK_GPIO);
2122 v |= SK_GPIO_DIR9;
2123 v &= ~SK_GPIO_DAT9;
2124 sk_win_write_4(sc, SK_GPIO, v);
2125 }
2126
2127 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2128 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2129
2130 if (sc->sk_coppertype)
2131 phy |= SK_GPHY_COPPER;
2132 else
2133 phy |= SK_GPHY_FIBER;
2134
2135 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2136
2137 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2138 DELAY(1000);
2139 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2140 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2141 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2142
2143 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2144 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2145
2146 DPRINTFN(6, ("sk_init_yukon: 3\n"));
2147
2148 /* unused read of the interrupt source register */
2149 DPRINTFN(6, ("sk_init_yukon: 4\n"));
2150 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2151
2152 DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2153 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2154 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2155
2156 /* MIB Counter Clear Mode set */
2157 reg |= YU_PAR_MIB_CLR;
2158 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2159 DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2160 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2161
2162 /* MIB Counter Clear Mode clear */
2163 DPRINTFN(6, ("sk_init_yukon: 5\n"));
2164 reg &= ~YU_PAR_MIB_CLR;
2165 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2166
2167 /* receive control reg */
2168 DPRINTFN(6, ("sk_init_yukon: 7\n"));
2169 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
2170
2171 /* transmit parameter register */
2172 DPRINTFN(6, ("sk_init_yukon: 8\n"));
2173 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2174 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
2175
2176 /* serial mode register */
2177 DPRINTFN(6, ("sk_init_yukon: 9\n"));
2178 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2179 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO | YU_SMR_IPG_DATA(0x1e));
2180
2181 DPRINTFN(6, ("sk_init_yukon: 10\n"));
2182 /* Setup Yukon's address */
2183 for (i = 0; i < 3; i++) {
2184 /* Write Source Address 1 (unicast filter) */
2185 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2186 sc_if->arpcom.ac_enaddr[i * 2] |
2187 sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
2188 }
2189
2190 for (i = 0; i < 3; i++) {
2191 reg = sk_win_read_2(sc_if->sk_softc,
2192 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2193 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2194 }
2195
2196 /* Program promiscuous mode and multicast filters. */
2197 DPRINTFN(6, ("sk_init_yukon: 11\n"));
2198 sk_iff(sc_if);
2199
2200 /* enable interrupt mask for counter overflows */
2201 DPRINTFN(6, ("sk_init_yukon: 12\n"));
2202 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2203 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2204 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2205
2206 /* Configure RX MAC FIFO Flush Mask */
2207 v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
2208 YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
2209 YU_RXSTAT_JABBER;
2210 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
2211
2212 /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
2213 if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
2214 v = SK_TFCTL_OPERATION_ON;
2215 else
2216 v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
2217 /* Configure RX MAC FIFO */
2218 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2219 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
2220
2221 /* Increase flush threshold to 64 bytes */
2222 SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
2223 SK_RFCTL_FIFO_THRESHOLD + 1);
2224
2225 /* Configure TX MAC FIFO */
2226 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2227 SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2228
2229 DPRINTFN(6, ("sk_init_yukon: end\n"));
2230 }
2231
2232 /*
2233 * Note that to properly initialize any part of the GEnesis chip,
2234 * you first have to take it out of reset mode.
2235 */
2236 void
sk_init(void * xsc_if)2237 sk_init(void *xsc_if)
2238 {
2239 struct sk_if_softc *sc_if = xsc_if;
2240 struct sk_softc *sc = sc_if->sk_softc;
2241 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2242 struct mii_data *mii = &sc_if->sk_mii;
2243 int s;
2244
2245 DPRINTFN(2, ("sk_init\n"));
2246
2247 s = splnet();
2248
2249 /* Cancel pending I/O and free all RX/TX buffers. */
2250 sk_stop(sc_if, 0);
2251
2252 if (SK_IS_GENESIS(sc)) {
2253 /* Configure LINK_SYNC LED */
2254 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2255 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2256 SK_LINKLED_LINKSYNC_ON);
2257
2258 /* Configure RX LED */
2259 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2260 SK_RXLEDCTL_COUNTER_START);
2261
2262 /* Configure TX LED */
2263 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2264 SK_TXLEDCTL_COUNTER_START);
2265 }
2266
2267 /*
2268 * Configure descriptor poll timer
2269 *
2270 * SK-NET GENESIS data sheet says that possibility of losing Start
2271 * transmit command due to CPU/cache related interim storage problems
2272 * under certain conditions. The document recommends a polling
2273 * mechanism to send a Start transmit command to initiate transfer
2274 * of ready descriptors regularly. To cope with this issue sk(4) now
2275 * enables descriptor poll timer to initiate descriptor processing
2276 * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
2277 * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
2278 * command instead of waiting for next descriptor polling time.
2279 * The same rule may apply to Rx side too but it seems that is not
2280 * needed at the moment.
2281 * Since sk(4) uses descriptor polling as a last resort there is no
2282 * need to set smaller polling time than maximum allowable one.
2283 */
2284 SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
2285
2286 /* Configure I2C registers */
2287
2288 /* Configure XMAC(s) */
2289 switch (sc->sk_type) {
2290 case SK_GENESIS:
2291 sk_init_xmac(sc_if);
2292 break;
2293 case SK_YUKON:
2294 case SK_YUKON_LITE:
2295 case SK_YUKON_LP:
2296 sk_init_yukon(sc_if);
2297 break;
2298 }
2299 mii_mediachg(mii);
2300
2301 if (SK_IS_GENESIS(sc)) {
2302 /* Configure MAC FIFOs */
2303 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2304 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2305 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2306
2307 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2308 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2309 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2310 }
2311
2312 /* Configure transmit arbiter(s) */
2313 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2314 SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
2315
2316 /* Configure RAMbuffers */
2317 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2318 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2319 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2320 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2321 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2322 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2323
2324 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2325 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2326 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2327 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2328 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2329 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2330 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2331
2332 /* Configure BMUs */
2333 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2334 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2335 SK_RX_RING_ADDR(sc_if, 0));
2336 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2337
2338 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2339 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2340 SK_TX_RING_ADDR(sc_if, 0));
2341 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2342
2343 /* Init descriptors */
2344 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2345 printf("%s: initialization failed: no "
2346 "memory for rx buffers\n", sc_if->sk_dev.dv_xname);
2347 sk_stop(sc_if, 0);
2348 splx(s);
2349 return;
2350 }
2351
2352 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2353 printf("%s: initialization failed: no "
2354 "memory for tx buffers\n", sc_if->sk_dev.dv_xname);
2355 sk_stop(sc_if, 0);
2356 splx(s);
2357 return;
2358 }
2359
2360 /* Configure interrupt handling */
2361 CSR_READ_4(sc, SK_ISSR);
2362 if (sc_if->sk_port == SK_PORT_A)
2363 sc->sk_intrmask |= SK_INTRS1;
2364 else
2365 sc->sk_intrmask |= SK_INTRS2;
2366
2367 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2368
2369 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2370
2371 /* Start BMUs. */
2372 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2373
2374 if (SK_IS_GENESIS(sc)) {
2375 /* Enable XMACs TX and RX state machines */
2376 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2377 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2378 XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
2379 }
2380
2381 if (SK_IS_YUKON(sc)) {
2382 u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2383 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2384 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2385 }
2386
2387 /* Activate descriptor polling timer */
2388 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
2389 /* start transfer of Tx descriptors */
2390 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2391
2392 ifp->if_flags |= IFF_RUNNING;
2393 ifq_clr_oactive(&ifp->if_snd);
2394
2395 if (SK_IS_YUKON(sc))
2396 timeout_add_sec(&sc_if->sk_tick_ch, 1);
2397
2398 splx(s);
2399 }
2400
2401 void
sk_stop(struct sk_if_softc * sc_if,int softonly)2402 sk_stop(struct sk_if_softc *sc_if, int softonly)
2403 {
2404 struct sk_softc *sc = sc_if->sk_softc;
2405 struct ifnet *ifp = &sc_if->arpcom.ac_if;
2406 bus_dmamap_t dmamap;
2407 struct sk_txmap_entry *dma;
2408 int i;
2409 u_int32_t val;
2410
2411 DPRINTFN(2, ("sk_stop\n"));
2412
2413 timeout_del(&sc_if->sk_tick_ch);
2414
2415 ifp->if_flags &= ~IFF_RUNNING;
2416 ifq_clr_oactive(&ifp->if_snd);
2417
2418 if (!softonly) {
2419 /* stop Tx descriptor polling timer */
2420 SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
2421 /* stop transfer of Tx descriptors */
2422 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
2423 for (i = 0; i < SK_TIMEOUT; i++) {
2424 val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
2425 if (!(val & SK_TXBMU_TX_STOP))
2426 break;
2427 DELAY(1);
2428 }
2429 if (i == SK_TIMEOUT) {
2430 printf("%s: cannot stop transfer of Tx descriptors\n",
2431 sc_if->sk_dev.dv_xname);
2432 }
2433 /* stop transfer of Rx descriptors */
2434 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
2435 for (i = 0; i < SK_TIMEOUT; i++) {
2436 val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
2437 if (!(val & SK_RXBMU_RX_STOP))
2438 break;
2439 DELAY(1);
2440 }
2441 if (i == SK_TIMEOUT) {
2442 printf("%s: cannot stop transfer of Rx descriptors\n",
2443 sc_if->sk_dev.dv_xname);
2444 }
2445
2446 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2447 u_int32_t val;
2448
2449 /* Put PHY back into reset. */
2450 val = sk_win_read_4(sc, SK_GPIO);
2451 if (sc_if->sk_port == SK_PORT_A) {
2452 val |= SK_GPIO_DIR0;
2453 val &= ~SK_GPIO_DAT0;
2454 } else {
2455 val |= SK_GPIO_DIR2;
2456 val &= ~SK_GPIO_DAT2;
2457 }
2458 sk_win_write_4(sc, SK_GPIO, val);
2459 }
2460
2461 /* Turn off various components of this interface. */
2462 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2463 switch (sc->sk_type) {
2464 case SK_GENESIS:
2465 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL,
2466 SK_TXMACCTL_XMAC_RESET);
2467 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2468 break;
2469 case SK_YUKON:
2470 case SK_YUKON_LITE:
2471 case SK_YUKON_LP:
2472 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2473 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2474 break;
2475 }
2476 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2477 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2478 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2479 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2480 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2481 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2482 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2483 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2484 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2485
2486 /* Disable interrupts */
2487 if (sc_if->sk_port == SK_PORT_A)
2488 sc->sk_intrmask &= ~SK_INTRS1;
2489 else
2490 sc->sk_intrmask &= ~SK_INTRS2;
2491 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2492
2493 SK_XM_READ_2(sc_if, XM_ISR);
2494 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2495 }
2496
2497 /* Free RX and TX mbufs still in the queues. */
2498 for (i = 0; i < SK_RX_RING_CNT; i++) {
2499 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
2500 dmamap = sc_if->sk_cdata.sk_rx_map[i];
2501 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
2502 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2503 bus_dmamap_unload(sc_if->sk_softc->sc_dmatag, dmamap);
2504 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2505 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2506 }
2507 }
2508
2509 for (i = 0; i < SK_TX_RING_CNT; i++) {
2510 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
2511 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2512 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2513 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head,
2514 sc_if->sk_cdata.sk_tx_map[i], link);
2515 sc_if->sk_cdata.sk_tx_map[i] = 0;
2516 }
2517 }
2518
2519 while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) {
2520 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
2521 bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap);
2522 free(dma, M_DEVBUF, 0);
2523 }
2524 }
2525
2526 const struct cfattach skc_ca = {
2527 sizeof(struct sk_softc), skc_probe, skc_attach, skc_detach,
2528 skc_activate
2529 };
2530
2531 struct cfdriver skc_cd = {
2532 NULL, "skc", DV_DULL
2533 };
2534
2535 const struct cfattach sk_ca = {
2536 sizeof(struct sk_if_softc), sk_probe, sk_attach, sk_detach,
2537 sk_activate
2538 };
2539
2540 struct cfdriver sk_cd = {
2541 NULL, "sk", DV_IFNET
2542 };
2543
2544 #ifdef SK_DEBUG
2545 void
sk_dump_txdesc(struct sk_tx_desc * desc,int idx)2546 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
2547 {
2548 #define DESC_PRINT(X) \
2549 if (X) \
2550 printf("txdesc[%d]." #X "=%#x\n", idx, X);
2551
2552 DESC_PRINT(letoh32(desc->sk_ctl));
2553 DESC_PRINT(letoh32(desc->sk_next));
2554 DESC_PRINT(letoh32(desc->sk_data_lo));
2555 DESC_PRINT(letoh32(desc->sk_data_hi));
2556 DESC_PRINT(letoh32(desc->sk_xmac_txstat));
2557 DESC_PRINT(letoh16(desc->sk_rsvd0));
2558 DESC_PRINT(letoh16(desc->sk_rsvd1));
2559 #undef PRINT
2560 }
2561
2562 void
sk_dump_bytes(const char * data,int len)2563 sk_dump_bytes(const char *data, int len)
2564 {
2565 int c, i, j;
2566
2567 for (i = 0; i < len; i += 16) {
2568 printf("%08x ", i);
2569 c = len - i;
2570 if (c > 16) c = 16;
2571
2572 for (j = 0; j < c; j++) {
2573 printf("%02x ", data[i + j] & 0xff);
2574 if ((j & 0xf) == 7 && j > 0)
2575 printf(" ");
2576 }
2577
2578 for (; j < 16; j++)
2579 printf(" ");
2580 printf(" ");
2581
2582 for (j = 0; j < c; j++) {
2583 int ch = data[i + j] & 0xff;
2584 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
2585 }
2586
2587 printf("\n");
2588
2589 if (c < 16)
2590 break;
2591 }
2592 }
2593
2594 void
sk_dump_mbuf(struct mbuf * m)2595 sk_dump_mbuf(struct mbuf *m)
2596 {
2597 int count = m->m_pkthdr.len;
2598
2599 printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len);
2600
2601 while (count > 0 && m) {
2602 printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n",
2603 m, m->m_data, m->m_len);
2604 sk_dump_bytes(mtod(m, char *), m->m_len);
2605
2606 count -= m->m_len;
2607 m = m->m_next;
2608 }
2609 }
2610 #endif
2611