1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/bsearch.h>
25 #include <linux/pci.h>
26 #include <linux/slab.h>
27 #include "kfd_priv.h"
28 #include "kfd_device_queue_manager.h"
29 #include "kfd_pm4_headers_vi.h"
30 #include "kfd_pm4_headers_aldebaran.h"
31 #include "cwsr_trap_handler.h"
32 #include "amdgpu_amdkfd.h"
33 #include "kfd_smi_events.h"
34 #include "kfd_svm.h"
35 #include "kfd_migrate.h"
36 #include "amdgpu.h"
37 #include "amdgpu_xcp.h"
38
39 #define MQD_SIZE_ALIGNED 768
40
41 /*
42 * kfd_locked is used to lock the kfd driver during suspend or reset
43 * once locked, kfd driver will stop any further GPU execution.
44 * create process (open) will return -EAGAIN.
45 */
46 static int kfd_locked;
47
48 #ifdef CONFIG_DRM_AMDGPU_CIK
49 extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50 #endif
51 extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52 extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53 extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54 extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55 extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56 extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57 extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58 extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59 extern const struct kfd2kgd_calls gfx_v12_kfd2kgd;
60
61 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
62 unsigned int chunk_size);
63 static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
64
65 static int kfd_resume(struct kfd_node *kfd);
66
kfd_device_info_set_sdma_info(struct kfd_dev * kfd)67 static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
68 {
69 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);
70
71 switch (sdma_version) {
72 case IP_VERSION(4, 0, 0):/* VEGA10 */
73 case IP_VERSION(4, 0, 1):/* VEGA12 */
74 case IP_VERSION(4, 1, 0):/* RAVEN */
75 case IP_VERSION(4, 1, 1):/* RAVEN */
76 case IP_VERSION(4, 1, 2):/* RENOIR */
77 case IP_VERSION(5, 2, 1):/* VANGOGH */
78 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
79 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
80 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
81 kfd->device_info.num_sdma_queues_per_engine = 2;
82 break;
83 case IP_VERSION(4, 2, 0):/* VEGA20 */
84 case IP_VERSION(4, 2, 2):/* ARCTURUS */
85 case IP_VERSION(4, 4, 0):/* ALDEBARAN */
86 case IP_VERSION(4, 4, 2):
87 case IP_VERSION(4, 4, 5):
88 case IP_VERSION(5, 0, 0):/* NAVI10 */
89 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
90 case IP_VERSION(5, 0, 2):/* NAVI14 */
91 case IP_VERSION(5, 0, 5):/* NAVI12 */
92 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
93 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
94 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
95 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
96 case IP_VERSION(6, 0, 0):
97 case IP_VERSION(6, 0, 1):
98 case IP_VERSION(6, 0, 2):
99 case IP_VERSION(6, 0, 3):
100 case IP_VERSION(6, 1, 0):
101 case IP_VERSION(6, 1, 1):
102 case IP_VERSION(6, 1, 2):
103 case IP_VERSION(7, 0, 0):
104 case IP_VERSION(7, 0, 1):
105 kfd->device_info.num_sdma_queues_per_engine = 8;
106 break;
107 default:
108 dev_warn(kfd_device,
109 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
110 sdma_version);
111 kfd->device_info.num_sdma_queues_per_engine = 8;
112 }
113
114 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
115
116 switch (sdma_version) {
117 case IP_VERSION(6, 0, 0):
118 case IP_VERSION(6, 0, 1):
119 case IP_VERSION(6, 0, 2):
120 case IP_VERSION(6, 0, 3):
121 case IP_VERSION(6, 1, 0):
122 case IP_VERSION(6, 1, 1):
123 case IP_VERSION(6, 1, 2):
124 case IP_VERSION(7, 0, 0):
125 case IP_VERSION(7, 0, 1):
126 /* Reserve 1 for paging and 1 for gfx */
127 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
128 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
129 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
130 kfd->adev->sdma.num_instances *
131 kfd->device_info.num_reserved_sdma_queues_per_engine);
132 break;
133 default:
134 break;
135 }
136 }
137
kfd_device_info_set_event_interrupt_class(struct kfd_dev * kfd)138 static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
139 {
140 uint32_t gc_version = KFD_GC_VERSION(kfd);
141
142 switch (gc_version) {
143 case IP_VERSION(9, 0, 1): /* VEGA10 */
144 case IP_VERSION(9, 1, 0): /* RAVEN */
145 case IP_VERSION(9, 2, 1): /* VEGA12 */
146 case IP_VERSION(9, 2, 2): /* RAVEN */
147 case IP_VERSION(9, 3, 0): /* RENOIR */
148 case IP_VERSION(9, 4, 0): /* VEGA20 */
149 case IP_VERSION(9, 4, 1): /* ARCTURUS */
150 case IP_VERSION(9, 4, 2): /* ALDEBARAN */
151 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
152 break;
153 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
154 case IP_VERSION(9, 4, 4): /* GC 9.4.4 */
155 kfd->device_info.event_interrupt_class =
156 &event_interrupt_class_v9_4_3;
157 break;
158 case IP_VERSION(10, 3, 1): /* VANGOGH */
159 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
160 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
161 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
162 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
163 case IP_VERSION(10, 1, 4):
164 case IP_VERSION(10, 1, 10): /* NAVI10 */
165 case IP_VERSION(10, 1, 2): /* NAVI12 */
166 case IP_VERSION(10, 1, 1): /* NAVI14 */
167 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
168 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
169 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
170 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
171 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
172 break;
173 case IP_VERSION(11, 0, 0):
174 case IP_VERSION(11, 0, 1):
175 case IP_VERSION(11, 0, 2):
176 case IP_VERSION(11, 0, 3):
177 case IP_VERSION(11, 0, 4):
178 case IP_VERSION(11, 5, 0):
179 case IP_VERSION(11, 5, 1):
180 case IP_VERSION(11, 5, 2):
181 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
182 break;
183 case IP_VERSION(12, 0, 0):
184 case IP_VERSION(12, 0, 1):
185 /* GFX12_TODO: Change to v12 version. */
186 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
187 break;
188 default:
189 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
190 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
191 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
192 }
193 }
194
kfd_device_info_init(struct kfd_dev * kfd,bool vf,uint32_t gfx_target_version)195 static void kfd_device_info_init(struct kfd_dev *kfd,
196 bool vf, uint32_t gfx_target_version)
197 {
198 uint32_t gc_version = KFD_GC_VERSION(kfd);
199 uint32_t asic_type = kfd->adev->asic_type;
200
201 kfd->device_info.max_pasid_bits = 16;
202 kfd->device_info.max_no_of_hqd = 24;
203 kfd->device_info.num_of_watch_points = 4;
204 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
205 kfd->device_info.gfx_target_version = gfx_target_version;
206
207 if (KFD_IS_SOC15(kfd)) {
208 kfd->device_info.doorbell_size = 8;
209 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
210 kfd->device_info.supports_cwsr = true;
211
212 kfd_device_info_set_sdma_info(kfd);
213
214 kfd_device_info_set_event_interrupt_class(kfd);
215
216 if (gc_version < IP_VERSION(11, 0, 0)) {
217 /* Navi2x+, Navi1x+ */
218 if (gc_version == IP_VERSION(10, 3, 6))
219 kfd->device_info.no_atomic_fw_version = 14;
220 else if (gc_version == IP_VERSION(10, 3, 7))
221 kfd->device_info.no_atomic_fw_version = 3;
222 else if (gc_version >= IP_VERSION(10, 3, 0))
223 kfd->device_info.no_atomic_fw_version = 92;
224 else if (gc_version >= IP_VERSION(10, 1, 1))
225 kfd->device_info.no_atomic_fw_version = 145;
226
227 /* Navi1x+ */
228 if (gc_version >= IP_VERSION(10, 1, 1))
229 kfd->device_info.needs_pci_atomics = true;
230 } else if (gc_version < IP_VERSION(12, 0, 0)) {
231 /*
232 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
233 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
234 * PCIe atomics support.
235 */
236 kfd->device_info.needs_pci_atomics = true;
237 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
238 } else if (gc_version < IP_VERSION(13, 0, 0)) {
239 kfd->device_info.needs_pci_atomics = true;
240 kfd->device_info.no_atomic_fw_version = 2090;
241 } else {
242 kfd->device_info.needs_pci_atomics = true;
243 }
244 } else {
245 kfd->device_info.doorbell_size = 4;
246 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
247 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
248 kfd->device_info.num_sdma_queues_per_engine = 2;
249
250 if (asic_type != CHIP_KAVERI &&
251 asic_type != CHIP_HAWAII &&
252 asic_type != CHIP_TONGA)
253 kfd->device_info.supports_cwsr = true;
254
255 if (asic_type != CHIP_HAWAII && !vf)
256 kfd->device_info.needs_pci_atomics = true;
257 }
258 }
259
kgd2kfd_probe(struct amdgpu_device * adev,bool vf)260 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
261 {
262 struct kfd_dev *kfd = NULL;
263 const struct kfd2kgd_calls *f2g = NULL;
264 uint32_t gfx_target_version = 0;
265
266 switch (adev->asic_type) {
267 #ifdef CONFIG_DRM_AMDGPU_CIK
268 case CHIP_KAVERI:
269 gfx_target_version = 70000;
270 if (!vf)
271 f2g = &gfx_v7_kfd2kgd;
272 break;
273 #endif
274 case CHIP_CARRIZO:
275 gfx_target_version = 80001;
276 if (!vf)
277 f2g = &gfx_v8_kfd2kgd;
278 break;
279 #ifdef CONFIG_DRM_AMDGPU_CIK
280 case CHIP_HAWAII:
281 gfx_target_version = 70001;
282 if (!amdgpu_exp_hw_support)
283 pr_info(
284 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
285 );
286 else if (!vf)
287 f2g = &gfx_v7_kfd2kgd;
288 break;
289 #endif
290 case CHIP_TONGA:
291 gfx_target_version = 80002;
292 if (!vf)
293 f2g = &gfx_v8_kfd2kgd;
294 break;
295 case CHIP_FIJI:
296 case CHIP_POLARIS10:
297 gfx_target_version = 80003;
298 f2g = &gfx_v8_kfd2kgd;
299 break;
300 case CHIP_POLARIS11:
301 case CHIP_POLARIS12:
302 case CHIP_VEGAM:
303 gfx_target_version = 80003;
304 if (!vf)
305 f2g = &gfx_v8_kfd2kgd;
306 break;
307 default:
308 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
309 /* Vega 10 */
310 case IP_VERSION(9, 0, 1):
311 gfx_target_version = 90000;
312 f2g = &gfx_v9_kfd2kgd;
313 break;
314 /* Raven */
315 case IP_VERSION(9, 1, 0):
316 case IP_VERSION(9, 2, 2):
317 gfx_target_version = 90002;
318 if (!vf)
319 f2g = &gfx_v9_kfd2kgd;
320 break;
321 /* Vega12 */
322 case IP_VERSION(9, 2, 1):
323 gfx_target_version = 90004;
324 if (!vf)
325 f2g = &gfx_v9_kfd2kgd;
326 break;
327 /* Renoir */
328 case IP_VERSION(9, 3, 0):
329 gfx_target_version = 90012;
330 if (!vf)
331 f2g = &gfx_v9_kfd2kgd;
332 break;
333 /* Vega20 */
334 case IP_VERSION(9, 4, 0):
335 gfx_target_version = 90006;
336 if (!vf)
337 f2g = &gfx_v9_kfd2kgd;
338 break;
339 /* Arcturus */
340 case IP_VERSION(9, 4, 1):
341 gfx_target_version = 90008;
342 f2g = &arcturus_kfd2kgd;
343 break;
344 /* Aldebaran */
345 case IP_VERSION(9, 4, 2):
346 gfx_target_version = 90010;
347 f2g = &aldebaran_kfd2kgd;
348 break;
349 case IP_VERSION(9, 4, 3):
350 gfx_target_version = adev->rev_id >= 1 ? 90402
351 : adev->flags & AMD_IS_APU ? 90400
352 : 90401;
353 f2g = &gc_9_4_3_kfd2kgd;
354 break;
355 case IP_VERSION(9, 4, 4):
356 gfx_target_version = 90402;
357 f2g = &gc_9_4_3_kfd2kgd;
358 break;
359 /* Navi10 */
360 case IP_VERSION(10, 1, 10):
361 gfx_target_version = 100100;
362 if (!vf)
363 f2g = &gfx_v10_kfd2kgd;
364 break;
365 /* Navi12 */
366 case IP_VERSION(10, 1, 2):
367 gfx_target_version = 100101;
368 f2g = &gfx_v10_kfd2kgd;
369 break;
370 /* Navi14 */
371 case IP_VERSION(10, 1, 1):
372 gfx_target_version = 100102;
373 if (!vf)
374 f2g = &gfx_v10_kfd2kgd;
375 break;
376 /* Cyan Skillfish */
377 case IP_VERSION(10, 1, 3):
378 case IP_VERSION(10, 1, 4):
379 gfx_target_version = 100103;
380 if (!vf)
381 f2g = &gfx_v10_kfd2kgd;
382 break;
383 /* Sienna Cichlid */
384 case IP_VERSION(10, 3, 0):
385 gfx_target_version = 100300;
386 f2g = &gfx_v10_3_kfd2kgd;
387 break;
388 /* Navy Flounder */
389 case IP_VERSION(10, 3, 2):
390 gfx_target_version = 100301;
391 f2g = &gfx_v10_3_kfd2kgd;
392 break;
393 /* Van Gogh */
394 case IP_VERSION(10, 3, 1):
395 gfx_target_version = 100303;
396 if (!vf)
397 f2g = &gfx_v10_3_kfd2kgd;
398 break;
399 /* Dimgrey Cavefish */
400 case IP_VERSION(10, 3, 4):
401 gfx_target_version = 100302;
402 f2g = &gfx_v10_3_kfd2kgd;
403 break;
404 /* Beige Goby */
405 case IP_VERSION(10, 3, 5):
406 gfx_target_version = 100304;
407 f2g = &gfx_v10_3_kfd2kgd;
408 break;
409 /* Yellow Carp */
410 case IP_VERSION(10, 3, 3):
411 gfx_target_version = 100305;
412 if (!vf)
413 f2g = &gfx_v10_3_kfd2kgd;
414 break;
415 case IP_VERSION(10, 3, 6):
416 case IP_VERSION(10, 3, 7):
417 gfx_target_version = 100306;
418 if (!vf)
419 f2g = &gfx_v10_3_kfd2kgd;
420 break;
421 case IP_VERSION(11, 0, 0):
422 gfx_target_version = 110000;
423 f2g = &gfx_v11_kfd2kgd;
424 break;
425 case IP_VERSION(11, 0, 1):
426 case IP_VERSION(11, 0, 4):
427 gfx_target_version = 110003;
428 f2g = &gfx_v11_kfd2kgd;
429 break;
430 case IP_VERSION(11, 0, 2):
431 gfx_target_version = 110002;
432 f2g = &gfx_v11_kfd2kgd;
433 break;
434 case IP_VERSION(11, 0, 3):
435 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
436 gfx_target_version = 110001;
437 f2g = &gfx_v11_kfd2kgd;
438 break;
439 case IP_VERSION(11, 5, 0):
440 gfx_target_version = 110500;
441 f2g = &gfx_v11_kfd2kgd;
442 break;
443 case IP_VERSION(11, 5, 1):
444 gfx_target_version = 110501;
445 f2g = &gfx_v11_kfd2kgd;
446 break;
447 case IP_VERSION(11, 5, 2):
448 gfx_target_version = 110502;
449 f2g = &gfx_v11_kfd2kgd;
450 break;
451 case IP_VERSION(12, 0, 0):
452 gfx_target_version = 120000;
453 f2g = &gfx_v12_kfd2kgd;
454 break;
455 case IP_VERSION(12, 0, 1):
456 gfx_target_version = 120001;
457 f2g = &gfx_v12_kfd2kgd;
458 break;
459 default:
460 break;
461 }
462 break;
463 }
464
465 if (!f2g) {
466 if (amdgpu_ip_version(adev, GC_HWIP, 0))
467 dev_info(kfd_device,
468 "GC IP %06x %s not supported in kfd\n",
469 amdgpu_ip_version(adev, GC_HWIP, 0),
470 vf ? "VF" : "");
471 else
472 dev_info(kfd_device, "%s %s not supported in kfd\n",
473 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
474 return NULL;
475 }
476
477 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
478 if (!kfd)
479 return NULL;
480
481 kfd->adev = adev;
482 kfd_device_info_init(kfd, vf, gfx_target_version);
483 kfd->init_complete = false;
484 kfd->kfd2kgd = f2g;
485 atomic_set(&kfd->compute_profile, 0);
486
487 mutex_init(&kfd->doorbell_mutex);
488
489 ida_init(&kfd->doorbell_ida);
490
491 return kfd;
492 }
493
kfd_cwsr_init(struct kfd_dev * kfd)494 static void kfd_cwsr_init(struct kfd_dev *kfd)
495 {
496 if (cwsr_enable && kfd->device_info.supports_cwsr) {
497 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
498 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex)
499 > KFD_CWSR_TMA_OFFSET);
500 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
501 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
502 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
503 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex)
504 > KFD_CWSR_TMA_OFFSET);
505 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
506 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
507 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
508 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex)
509 > KFD_CWSR_TMA_OFFSET);
510 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
511 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
512 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
513 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) {
514 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex)
515 > KFD_CWSR_TMA_OFFSET);
516 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
517 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
518 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
519 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex)
520 > KFD_CWSR_TMA_OFFSET);
521 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
522 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
523 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
524 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex)
525 > KFD_CWSR_TMA_OFFSET);
526 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
527 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
528 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
529 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex)
530 > KFD_CWSR_TMA_OFFSET);
531 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
532 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
533 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0)) {
534 /* The gfx11 cwsr trap handler must fit inside a single
535 page. */
536 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
537 kfd->cwsr_isa = cwsr_trap_gfx11_hex;
538 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
539 } else {
540 BUILD_BUG_ON(sizeof(cwsr_trap_gfx12_hex) > PAGE_SIZE);
541 kfd->cwsr_isa = cwsr_trap_gfx12_hex;
542 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx12_hex);
543 }
544
545 kfd->cwsr_enabled = true;
546 }
547 }
548
kfd_gws_init(struct kfd_node * node)549 static int kfd_gws_init(struct kfd_node *node)
550 {
551 int ret = 0;
552 struct kfd_dev *kfd = node->kfd;
553 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
554
555 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
556 return 0;
557
558 if (hws_gws_support || (KFD_IS_SOC15(node) &&
559 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
560 && kfd->mec2_fw_version >= 0x81b3) ||
561 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
562 && kfd->mec2_fw_version >= 0x1b3) ||
563 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
564 && kfd->mec2_fw_version >= 0x30) ||
565 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
566 && kfd->mec2_fw_version >= 0x28) ||
567 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3) ||
568 KFD_GC_VERSION(node) == IP_VERSION(9, 4, 4)) ||
569 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
570 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
571 && kfd->mec2_fw_version >= 0x6b) ||
572 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
573 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
574 && mes_rev >= 68))))
575 ret = amdgpu_amdkfd_alloc_gws(node->adev,
576 node->adev->gds.gws_size, &node->gws);
577
578 return ret;
579 }
580
kfd_smi_init(struct kfd_node * dev)581 static void kfd_smi_init(struct kfd_node *dev)
582 {
583 INIT_LIST_HEAD(&dev->smi_clients);
584 spin_lock_init(&dev->smi_lock);
585 }
586
kfd_init_node(struct kfd_node * node)587 static int kfd_init_node(struct kfd_node *node)
588 {
589 int err = -1;
590
591 if (kfd_interrupt_init(node)) {
592 dev_err(kfd_device, "Error initializing interrupts\n");
593 goto kfd_interrupt_error;
594 }
595
596 node->dqm = device_queue_manager_init(node);
597 if (!node->dqm) {
598 dev_err(kfd_device, "Error initializing queue manager\n");
599 goto device_queue_manager_error;
600 }
601
602 if (kfd_gws_init(node)) {
603 dev_err(kfd_device, "Could not allocate %d gws\n",
604 node->adev->gds.gws_size);
605 goto gws_error;
606 }
607
608 if (kfd_resume(node))
609 goto kfd_resume_error;
610
611 if (kfd_topology_add_device(node)) {
612 dev_err(kfd_device, "Error adding device to topology\n");
613 goto kfd_topology_add_device_error;
614 }
615
616 kfd_smi_init(node);
617
618 return 0;
619
620 kfd_topology_add_device_error:
621 kfd_resume_error:
622 gws_error:
623 device_queue_manager_uninit(node->dqm);
624 device_queue_manager_error:
625 kfd_interrupt_exit(node);
626 kfd_interrupt_error:
627 if (node->gws)
628 amdgpu_amdkfd_free_gws(node->adev, node->gws);
629
630 /* Cleanup the node memory here */
631 kfree(node);
632 return err;
633 }
634
kfd_cleanup_nodes(struct kfd_dev * kfd,unsigned int num_nodes)635 static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
636 {
637 struct kfd_node *knode;
638 unsigned int i;
639
640 for (i = 0; i < num_nodes; i++) {
641 knode = kfd->nodes[i];
642 device_queue_manager_uninit(knode->dqm);
643 kfd_interrupt_exit(knode);
644 kfd_topology_remove_device(knode);
645 if (knode->gws)
646 amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
647 kfree(knode);
648 kfd->nodes[i] = NULL;
649 }
650 }
651
kfd_setup_interrupt_bitmap(struct kfd_node * node,unsigned int kfd_node_idx)652 static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
653 unsigned int kfd_node_idx)
654 {
655 struct amdgpu_device *adev = node->adev;
656 uint32_t xcc_mask = node->xcc_mask;
657 uint32_t xcc, mapped_xcc;
658 /*
659 * Interrupt bitmap is setup for processing interrupts from
660 * different XCDs and AIDs.
661 * Interrupt bitmap is defined as follows:
662 * 1. Bits 0-15 - correspond to the NodeId field.
663 * Each bit corresponds to NodeId number. For example, if
664 * a KFD node has interrupt bitmap set to 0x7, then this
665 * KFD node will process interrupts with NodeId = 0, 1 and 2
666 * in the IH cookie.
667 * 2. Bits 16-31 - unused.
668 *
669 * Please note that the kfd_node_idx argument passed to this
670 * function is not related to NodeId field received in the
671 * IH cookie.
672 *
673 * In CPX mode, a KFD node will process an interrupt if:
674 * - the Node Id matches the corresponding bit set in
675 * Bits 0-15.
676 * - AND VMID reported in the interrupt lies within the
677 * VMID range of the node.
678 */
679 for_each_inst(xcc, xcc_mask) {
680 mapped_xcc = GET_INST(GC, xcc);
681 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
682 }
683 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
684 node->interrupt_bitmap);
685 }
686
kgd2kfd_device_init(struct kfd_dev * kfd,const struct kgd2kfd_shared_resources * gpu_resources)687 bool kgd2kfd_device_init(struct kfd_dev *kfd,
688 const struct kgd2kfd_shared_resources *gpu_resources)
689 {
690 unsigned int size, map_process_packet_size, i;
691 struct kfd_node *node;
692 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
693 unsigned int max_proc_per_quantum;
694 int partition_mode;
695 int xcp_idx;
696
697 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
698 KGD_ENGINE_MEC1);
699 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
700 KGD_ENGINE_MEC2);
701 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
702 KGD_ENGINE_SDMA1);
703 kfd->shared_resources = *gpu_resources;
704
705 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
706
707 if (kfd->num_nodes == 0) {
708 dev_err(kfd_device,
709 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
710 kfd->adev->gfx.num_xcc_per_xcp);
711 goto out;
712 }
713
714 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
715 * 32 and 64-bit requests are possible and must be
716 * supported.
717 */
718 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
719 if (!kfd->pci_atomic_requested &&
720 kfd->device_info.needs_pci_atomics &&
721 (!kfd->device_info.no_atomic_fw_version ||
722 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
723 dev_info(kfd_device,
724 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
725 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
726 kfd->mec_fw_version,
727 kfd->device_info.no_atomic_fw_version);
728 return false;
729 }
730
731 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
732 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
733 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
734
735 /* For GFX9.4.3, we need special handling for VMIDs depending on
736 * partition mode.
737 * In CPX mode, the VMID range needs to be shared between XCDs.
738 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
739 * divide them equally, we change starting VMID to 4 and not use
740 * VMID 3.
741 * If the VMID range changes for GFX9.4.3, then this code MUST be
742 * revisited.
743 */
744 if (kfd->adev->xcp_mgr) {
745 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
746 AMDGPU_XCP_FL_LOCKED);
747 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
748 kfd->num_nodes != 1) {
749 vmid_num_kfd /= 2;
750 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
751 }
752 }
753
754 /* Verify module parameters regarding mapped process number*/
755 if (hws_max_conc_proc >= 0)
756 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
757 else
758 max_proc_per_quantum = vmid_num_kfd;
759
760 /* calculate max size of mqds needed for queues */
761 size = max_num_of_queues_per_device *
762 kfd->device_info.mqd_size_aligned;
763
764 /*
765 * calculate max size of runlist packet.
766 * There can be only 2 packets at once
767 */
768 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
769 sizeof(struct pm4_mes_map_process_aldebaran) :
770 sizeof(struct pm4_mes_map_process);
771 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
772 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
773 + sizeof(struct pm4_mes_runlist)) * 2;
774
775 /* Add size of HIQ & DIQ */
776 size += KFD_KERNEL_QUEUE_SIZE * 2;
777
778 /* add another 512KB for all other allocations on gart (HPD, fences) */
779 size += 512 * 1024;
780
781 if (amdgpu_amdkfd_alloc_gtt_mem(
782 kfd->adev, size, &kfd->gtt_mem,
783 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
784 false)) {
785 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
786 goto alloc_gtt_mem_failure;
787 }
788
789 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
790
791 /* Initialize GTT sa with 512 byte chunk size */
792 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
793 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
794 goto kfd_gtt_sa_init_error;
795 }
796
797 if (kfd_doorbell_init(kfd)) {
798 dev_err(kfd_device,
799 "Error initializing doorbell aperture\n");
800 goto kfd_doorbell_error;
801 }
802
803 if (amdgpu_use_xgmi_p2p)
804 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
805
806 /*
807 * For GFX9.4.3, the KFD abstracts all partitions within a socket as
808 * xGMI connected in the topology so assign a unique hive id per
809 * device based on the pci device location if device is in PCIe mode.
810 */
811 if (!kfd->hive_id &&
812 (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
813 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) &&
814 kfd->num_nodes > 1)
815 kfd->hive_id = pci_dev_id(kfd->adev->pdev);
816
817 kfd->noretry = kfd->adev->gmc.noretry;
818
819 kfd_cwsr_init(kfd);
820
821 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
822 kfd->num_nodes);
823
824 /* Allocate the KFD nodes */
825 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
826 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
827 if (!node)
828 goto node_alloc_error;
829
830 node->node_id = i;
831 node->adev = kfd->adev;
832 node->kfd = kfd;
833 node->kfd2kgd = kfd->kfd2kgd;
834 node->vm_info.vmid_num_kfd = vmid_num_kfd;
835 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
836 /* TODO : Check if error handling is needed */
837 if (node->xcp) {
838 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
839 &node->xcc_mask);
840 ++xcp_idx;
841 } else {
842 node->xcc_mask =
843 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
844 }
845
846 if (node->xcp) {
847 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
848 node->node_id, node->xcp->mem_id,
849 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
850 }
851
852 if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
853 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4)) &&
854 partition_mode == AMDGPU_CPX_PARTITION_MODE &&
855 kfd->num_nodes != 1) {
856 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range
857 * 4-9 and second XCD gets VMID range 10-15.
858 */
859
860 node->vm_info.first_vmid_kfd = (i%2 == 0) ?
861 first_vmid_kfd :
862 first_vmid_kfd+vmid_num_kfd;
863 node->vm_info.last_vmid_kfd = (i%2 == 0) ?
864 last_vmid_kfd-vmid_num_kfd :
865 last_vmid_kfd;
866 node->compute_vmid_bitmap =
867 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
868 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
869 } else {
870 node->vm_info.first_vmid_kfd = first_vmid_kfd;
871 node->vm_info.last_vmid_kfd = last_vmid_kfd;
872 node->compute_vmid_bitmap =
873 gpu_resources->compute_vmid_bitmap;
874 }
875 node->max_proc_per_quantum = max_proc_per_quantum;
876 atomic_set(&node->sram_ecc_flag, 0);
877
878 amdgpu_amdkfd_get_local_mem_info(kfd->adev,
879 &node->local_mem_info, node->xcp);
880
881 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) ||
882 KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 4))
883 kfd_setup_interrupt_bitmap(node, i);
884
885 /* Initialize the KFD node */
886 if (kfd_init_node(node)) {
887 dev_err(kfd_device, "Error initializing KFD node\n");
888 goto node_init_error;
889 }
890
891 spin_lock_init(&node->watch_points_lock);
892
893 kfd->nodes[i] = node;
894 }
895
896 svm_range_set_max_pages(kfd->adev);
897
898 kfd->init_complete = true;
899 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
900 kfd->adev->pdev->device);
901
902 pr_debug("Starting kfd with the following scheduling policy %d\n",
903 node->dqm->sched_policy);
904
905 goto out;
906
907 node_init_error:
908 node_alloc_error:
909 kfd_cleanup_nodes(kfd, i);
910 kfd_doorbell_fini(kfd);
911 kfd_doorbell_error:
912 kfd_gtt_sa_fini(kfd);
913 kfd_gtt_sa_init_error:
914 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
915 alloc_gtt_mem_failure:
916 dev_err(kfd_device,
917 "device %x:%x NOT added due to errors\n",
918 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
919 out:
920 return kfd->init_complete;
921 }
922
kgd2kfd_device_exit(struct kfd_dev * kfd)923 void kgd2kfd_device_exit(struct kfd_dev *kfd)
924 {
925 if (kfd->init_complete) {
926 /* Cleanup KFD nodes */
927 kfd_cleanup_nodes(kfd, kfd->num_nodes);
928 /* Cleanup common/shared resources */
929 kfd_doorbell_fini(kfd);
930 ida_destroy(&kfd->doorbell_ida);
931 kfd_gtt_sa_fini(kfd);
932 amdgpu_amdkfd_free_gtt_mem(kfd->adev, &kfd->gtt_mem);
933 }
934
935 kfree(kfd);
936 }
937
kgd2kfd_pre_reset(struct kfd_dev * kfd,struct amdgpu_reset_context * reset_context)938 int kgd2kfd_pre_reset(struct kfd_dev *kfd,
939 struct amdgpu_reset_context *reset_context)
940 {
941 struct kfd_node *node;
942 int i;
943
944 if (!kfd->init_complete)
945 return 0;
946
947 for (i = 0; i < kfd->num_nodes; i++) {
948 node = kfd->nodes[i];
949 kfd_smi_event_update_gpu_reset(node, false, reset_context);
950 }
951
952 kgd2kfd_suspend(kfd, false);
953
954 for (i = 0; i < kfd->num_nodes; i++)
955 kfd_signal_reset_event(kfd->nodes[i]);
956
957 return 0;
958 }
959
960 /*
961 * Fix me. KFD won't be able to resume existing process for now.
962 * We will keep all existing process in a evicted state and
963 * wait the process to be terminated.
964 */
965
kgd2kfd_post_reset(struct kfd_dev * kfd)966 int kgd2kfd_post_reset(struct kfd_dev *kfd)
967 {
968 int ret;
969 struct kfd_node *node;
970 int i;
971
972 if (!kfd->init_complete)
973 return 0;
974
975 for (i = 0; i < kfd->num_nodes; i++) {
976 ret = kfd_resume(kfd->nodes[i]);
977 if (ret)
978 return ret;
979 }
980
981 mutex_lock(&kfd_processes_mutex);
982 --kfd_locked;
983 mutex_unlock(&kfd_processes_mutex);
984
985 for (i = 0; i < kfd->num_nodes; i++) {
986 node = kfd->nodes[i];
987 atomic_set(&node->sram_ecc_flag, 0);
988 kfd_smi_event_update_gpu_reset(node, true, NULL);
989 }
990
991 return 0;
992 }
993
kfd_is_locked(void)994 bool kfd_is_locked(void)
995 {
996 lockdep_assert_held(&kfd_processes_mutex);
997 return (kfd_locked > 0);
998 }
999
kgd2kfd_suspend(struct kfd_dev * kfd,bool run_pm)1000 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
1001 {
1002 struct kfd_node *node;
1003 int i;
1004
1005 if (!kfd->init_complete)
1006 return;
1007
1008 /* for runtime suspend, skip locking kfd */
1009 if (!run_pm) {
1010 mutex_lock(&kfd_processes_mutex);
1011 /* For first KFD device suspend all the KFD processes */
1012 if (++kfd_locked == 1)
1013 kfd_suspend_all_processes();
1014 mutex_unlock(&kfd_processes_mutex);
1015 }
1016
1017 for (i = 0; i < kfd->num_nodes; i++) {
1018 node = kfd->nodes[i];
1019 node->dqm->ops.stop(node->dqm);
1020 }
1021 }
1022
kgd2kfd_resume(struct kfd_dev * kfd,bool run_pm)1023 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
1024 {
1025 int ret, i;
1026
1027 if (!kfd->init_complete)
1028 return 0;
1029
1030 for (i = 0; i < kfd->num_nodes; i++) {
1031 ret = kfd_resume(kfd->nodes[i]);
1032 if (ret)
1033 return ret;
1034 }
1035
1036 /* for runtime resume, skip unlocking kfd */
1037 if (!run_pm) {
1038 mutex_lock(&kfd_processes_mutex);
1039 if (--kfd_locked == 0)
1040 ret = kfd_resume_all_processes();
1041 WARN_ONCE(kfd_locked < 0, "KFD suspend / resume ref. error");
1042 mutex_unlock(&kfd_processes_mutex);
1043 }
1044
1045 return ret;
1046 }
1047
kfd_resume(struct kfd_node * node)1048 static int kfd_resume(struct kfd_node *node)
1049 {
1050 int err = 0;
1051
1052 err = node->dqm->ops.start(node->dqm);
1053 if (err)
1054 dev_err(kfd_device,
1055 "Error starting queue manager for device %x:%x\n",
1056 node->adev->pdev->vendor, node->adev->pdev->device);
1057
1058 return err;
1059 }
1060
kfd_queue_work(struct workqueue_struct * wq,struct work_struct * work)1061 static inline void kfd_queue_work(struct workqueue_struct *wq,
1062 struct work_struct *work)
1063 {
1064 int cpu, new_cpu;
1065
1066 cpu = new_cpu = smp_processor_id();
1067 do {
1068 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
1069 if (cpu_to_node(new_cpu) == numa_node_id())
1070 break;
1071 } while (cpu != new_cpu);
1072
1073 queue_work_on(new_cpu, wq, work);
1074 }
1075
1076 /* This is called directly from KGD at ISR. */
kgd2kfd_interrupt(struct kfd_dev * kfd,const void * ih_ring_entry)1077 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1078 {
1079 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1080 bool is_patched = false;
1081 unsigned long flags;
1082 struct kfd_node *node;
1083
1084 if (!kfd->init_complete)
1085 return;
1086
1087 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1088 dev_err_once(kfd_device, "Ring entry too small\n");
1089 return;
1090 }
1091
1092 for (i = 0; i < kfd->num_nodes; i++) {
1093 node = kfd->nodes[i];
1094 spin_lock_irqsave(&node->interrupt_lock, flags);
1095
1096 if (node->interrupts_active
1097 && interrupt_is_wanted(node, ih_ring_entry,
1098 patched_ihre, &is_patched)
1099 && enqueue_ih_ring_entry(node,
1100 is_patched ? patched_ihre : ih_ring_entry)) {
1101 kfd_queue_work(node->ih_wq, &node->interrupt_work);
1102 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1103 return;
1104 }
1105 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1106 }
1107
1108 }
1109
kgd2kfd_quiesce_mm(struct mm_struct * mm,uint32_t trigger)1110 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1111 {
1112 struct kfd_process *p;
1113 int r;
1114
1115 /* Because we are called from arbitrary context (workqueue) as opposed
1116 * to process context, kfd_process could attempt to exit while we are
1117 * running so the lookup function increments the process ref count.
1118 */
1119 p = kfd_lookup_process_by_mm(mm);
1120 if (!p)
1121 return -ESRCH;
1122
1123 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1124 r = kfd_process_evict_queues(p, trigger);
1125
1126 kfd_unref_process(p);
1127 return r;
1128 }
1129
kgd2kfd_resume_mm(struct mm_struct * mm)1130 int kgd2kfd_resume_mm(struct mm_struct *mm)
1131 {
1132 struct kfd_process *p;
1133 int r;
1134
1135 /* Because we are called from arbitrary context (workqueue) as opposed
1136 * to process context, kfd_process could attempt to exit while we are
1137 * running so the lookup function increments the process ref count.
1138 */
1139 p = kfd_lookup_process_by_mm(mm);
1140 if (!p)
1141 return -ESRCH;
1142
1143 r = kfd_process_restore_queues(p);
1144
1145 kfd_unref_process(p);
1146 return r;
1147 }
1148
1149 /** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1150 * prepare for safe eviction of KFD BOs that belong to the specified
1151 * process.
1152 *
1153 * @mm: mm_struct that identifies the specified KFD process
1154 * @fence: eviction fence attached to KFD process BOs
1155 *
1156 */
kgd2kfd_schedule_evict_and_restore_process(struct mm_struct * mm,struct dma_fence * fence)1157 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1158 struct dma_fence *fence)
1159 {
1160 struct kfd_process *p;
1161 unsigned long active_time;
1162 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1163
1164 if (!fence)
1165 return -EINVAL;
1166
1167 if (dma_fence_is_signaled(fence))
1168 return 0;
1169
1170 p = kfd_lookup_process_by_mm(mm);
1171 if (!p)
1172 return -ENODEV;
1173
1174 if (fence->seqno == p->last_eviction_seqno)
1175 goto out;
1176
1177 p->last_eviction_seqno = fence->seqno;
1178
1179 /* Avoid KFD process starvation. Wait for at least
1180 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1181 */
1182 active_time = get_jiffies_64() - p->last_restore_timestamp;
1183 if (delay_jiffies > active_time)
1184 delay_jiffies -= active_time;
1185 else
1186 delay_jiffies = 0;
1187
1188 /* During process initialization eviction_work.dwork is initialized
1189 * to kfd_evict_bo_worker
1190 */
1191 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1192 p->lead_thread->pid, delay_jiffies);
1193 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1194 out:
1195 kfd_unref_process(p);
1196 return 0;
1197 }
1198
kfd_gtt_sa_init(struct kfd_dev * kfd,unsigned int buf_size,unsigned int chunk_size)1199 static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1200 unsigned int chunk_size)
1201 {
1202 if (WARN_ON(buf_size < chunk_size))
1203 return -EINVAL;
1204 if (WARN_ON(buf_size == 0))
1205 return -EINVAL;
1206 if (WARN_ON(chunk_size == 0))
1207 return -EINVAL;
1208
1209 kfd->gtt_sa_chunk_size = chunk_size;
1210 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1211
1212 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1213 GFP_KERNEL);
1214 if (!kfd->gtt_sa_bitmap)
1215 return -ENOMEM;
1216
1217 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1218 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1219
1220 mutex_init(&kfd->gtt_sa_lock);
1221
1222 return 0;
1223 }
1224
kfd_gtt_sa_fini(struct kfd_dev * kfd)1225 static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1226 {
1227 mutex_destroy(&kfd->gtt_sa_lock);
1228 bitmap_free(kfd->gtt_sa_bitmap);
1229 }
1230
kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,unsigned int bit_num,unsigned int chunk_size)1231 static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1232 unsigned int bit_num,
1233 unsigned int chunk_size)
1234 {
1235 return start_addr + bit_num * chunk_size;
1236 }
1237
kfd_gtt_sa_calc_cpu_addr(void * start_addr,unsigned int bit_num,unsigned int chunk_size)1238 static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1239 unsigned int bit_num,
1240 unsigned int chunk_size)
1241 {
1242 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1243 }
1244
kfd_gtt_sa_allocate(struct kfd_node * node,unsigned int size,struct kfd_mem_obj ** mem_obj)1245 int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1246 struct kfd_mem_obj **mem_obj)
1247 {
1248 unsigned int found, start_search, cur_size;
1249 struct kfd_dev *kfd = node->kfd;
1250
1251 if (size == 0)
1252 return -EINVAL;
1253
1254 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1255 return -ENOMEM;
1256
1257 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1258 if (!(*mem_obj))
1259 return -ENOMEM;
1260
1261 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1262
1263 start_search = 0;
1264
1265 mutex_lock(&kfd->gtt_sa_lock);
1266
1267 kfd_gtt_restart_search:
1268 /* Find the first chunk that is free */
1269 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1270 kfd->gtt_sa_num_of_chunks,
1271 start_search);
1272
1273 pr_debug("Found = %d\n", found);
1274
1275 /* If there wasn't any free chunk, bail out */
1276 if (found == kfd->gtt_sa_num_of_chunks)
1277 goto kfd_gtt_no_free_chunk;
1278
1279 /* Update fields of mem_obj */
1280 (*mem_obj)->range_start = found;
1281 (*mem_obj)->range_end = found;
1282 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1283 kfd->gtt_start_gpu_addr,
1284 found,
1285 kfd->gtt_sa_chunk_size);
1286 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1287 kfd->gtt_start_cpu_ptr,
1288 found,
1289 kfd->gtt_sa_chunk_size);
1290
1291 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1292 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1293
1294 /* If we need only one chunk, mark it as allocated and get out */
1295 if (size <= kfd->gtt_sa_chunk_size) {
1296 pr_debug("Single bit\n");
1297 __set_bit(found, kfd->gtt_sa_bitmap);
1298 goto kfd_gtt_out;
1299 }
1300
1301 /* Otherwise, try to see if we have enough contiguous chunks */
1302 cur_size = size - kfd->gtt_sa_chunk_size;
1303 do {
1304 (*mem_obj)->range_end =
1305 find_next_zero_bit(kfd->gtt_sa_bitmap,
1306 kfd->gtt_sa_num_of_chunks, ++found);
1307 /*
1308 * If next free chunk is not contiguous than we need to
1309 * restart our search from the last free chunk we found (which
1310 * wasn't contiguous to the previous ones
1311 */
1312 if ((*mem_obj)->range_end != found) {
1313 start_search = found;
1314 goto kfd_gtt_restart_search;
1315 }
1316
1317 /*
1318 * If we reached end of buffer, bail out with error
1319 */
1320 if (found == kfd->gtt_sa_num_of_chunks)
1321 goto kfd_gtt_no_free_chunk;
1322
1323 /* Check if we don't need another chunk */
1324 if (cur_size <= kfd->gtt_sa_chunk_size)
1325 cur_size = 0;
1326 else
1327 cur_size -= kfd->gtt_sa_chunk_size;
1328
1329 } while (cur_size > 0);
1330
1331 pr_debug("range_start = %d, range_end = %d\n",
1332 (*mem_obj)->range_start, (*mem_obj)->range_end);
1333
1334 /* Mark the chunks as allocated */
1335 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1336 (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1337
1338 kfd_gtt_out:
1339 mutex_unlock(&kfd->gtt_sa_lock);
1340 return 0;
1341
1342 kfd_gtt_no_free_chunk:
1343 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1344 mutex_unlock(&kfd->gtt_sa_lock);
1345 kfree(*mem_obj);
1346 return -ENOMEM;
1347 }
1348
kfd_gtt_sa_free(struct kfd_node * node,struct kfd_mem_obj * mem_obj)1349 int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1350 {
1351 struct kfd_dev *kfd = node->kfd;
1352
1353 /* Act like kfree when trying to free a NULL object */
1354 if (!mem_obj)
1355 return 0;
1356
1357 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1358 mem_obj, mem_obj->range_start, mem_obj->range_end);
1359
1360 mutex_lock(&kfd->gtt_sa_lock);
1361
1362 /* Mark the chunks as free */
1363 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1364 mem_obj->range_end - mem_obj->range_start + 1);
1365
1366 mutex_unlock(&kfd->gtt_sa_lock);
1367
1368 kfree(mem_obj);
1369 return 0;
1370 }
1371
kgd2kfd_set_sram_ecc_flag(struct kfd_dev * kfd)1372 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1373 {
1374 /*
1375 * TODO: Currently update SRAM ECC flag for first node.
1376 * This needs to be updated later when we can
1377 * identify SRAM ECC error on other nodes also.
1378 */
1379 if (kfd)
1380 atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1381 }
1382
kfd_inc_compute_active(struct kfd_node * node)1383 void kfd_inc_compute_active(struct kfd_node *node)
1384 {
1385 if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1386 amdgpu_amdkfd_set_compute_idle(node->adev, false);
1387 }
1388
kfd_dec_compute_active(struct kfd_node * node)1389 void kfd_dec_compute_active(struct kfd_node *node)
1390 {
1391 int count = atomic_dec_return(&node->kfd->compute_profile);
1392
1393 if (count == 0)
1394 amdgpu_amdkfd_set_compute_idle(node->adev, true);
1395 WARN_ONCE(count < 0, "Compute profile ref. count error");
1396 }
1397
kgd2kfd_smi_event_throttle(struct kfd_dev * kfd,uint64_t throttle_bitmask)1398 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1399 {
1400 /*
1401 * TODO: For now, raise the throttling event only on first node.
1402 * This will need to change after we are able to determine
1403 * which node raised the throttling event.
1404 */
1405 if (kfd && kfd->init_complete)
1406 kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1407 throttle_bitmask);
1408 }
1409
1410 /* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1411 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1412 * When the device has more than two engines, we reserve two for PCIe to enable
1413 * full-duplex and the rest are used as XGMI.
1414 */
kfd_get_num_sdma_engines(struct kfd_node * node)1415 unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1416 {
1417 /* If XGMI is not supported, all SDMA engines are PCIe */
1418 if (!node->adev->gmc.xgmi.supported)
1419 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1420
1421 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1422 }
1423
kfd_get_num_xgmi_sdma_engines(struct kfd_node * node)1424 unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1425 {
1426 /* After reserved for PCIe, the rest of engines are XGMI */
1427 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1428 kfd_get_num_sdma_engines(node);
1429 }
1430
kgd2kfd_check_and_lock_kfd(void)1431 int kgd2kfd_check_and_lock_kfd(void)
1432 {
1433 mutex_lock(&kfd_processes_mutex);
1434 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {
1435 mutex_unlock(&kfd_processes_mutex);
1436 return -EBUSY;
1437 }
1438
1439 ++kfd_locked;
1440 mutex_unlock(&kfd_processes_mutex);
1441
1442 return 0;
1443 }
1444
kgd2kfd_unlock_kfd(void)1445 void kgd2kfd_unlock_kfd(void)
1446 {
1447 mutex_lock(&kfd_processes_mutex);
1448 --kfd_locked;
1449 mutex_unlock(&kfd_processes_mutex);
1450 }
1451
kgd2kfd_start_sched(struct kfd_dev * kfd,uint32_t node_id)1452 int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)
1453 {
1454 struct kfd_node *node;
1455 int ret;
1456
1457 if (!kfd->init_complete)
1458 return 0;
1459
1460 if (node_id >= kfd->num_nodes) {
1461 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1462 node_id, kfd->num_nodes - 1);
1463 return -EINVAL;
1464 }
1465 node = kfd->nodes[node_id];
1466
1467 ret = node->dqm->ops.unhalt(node->dqm);
1468 if (ret)
1469 dev_err(kfd_device, "Error in starting scheduler\n");
1470
1471 return ret;
1472 }
1473
kgd2kfd_stop_sched(struct kfd_dev * kfd,uint32_t node_id)1474 int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)
1475 {
1476 struct kfd_node *node;
1477
1478 if (!kfd->init_complete)
1479 return 0;
1480
1481 if (node_id >= kfd->num_nodes) {
1482 dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n",
1483 node_id, kfd->num_nodes - 1);
1484 return -EINVAL;
1485 }
1486
1487 node = kfd->nodes[node_id];
1488 return node->dqm->ops.halt(node->dqm);
1489 }
1490
1491 #if defined(CONFIG_DEBUG_FS)
1492
1493 /* This function will send a package to HIQ to hang the HWS
1494 * which will trigger a GPU reset and bring the HWS back to normal state
1495 */
kfd_debugfs_hang_hws(struct kfd_node * dev)1496 int kfd_debugfs_hang_hws(struct kfd_node *dev)
1497 {
1498 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1499 pr_err("HWS is not enabled");
1500 return -EINVAL;
1501 }
1502
1503 return dqm_debugfs_hang_hws(dev->dqm);
1504 }
1505
1506 #endif
1507