1 /* $NetBSD: if_uralreg.h,v 1.5 2019/07/25 11:10:38 msaitoh Exp $ */ 2 /* $OpenBSD: if_ralreg.h,v 1.5 2005/04/01 13:13:43 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2005 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 #define RAL_RX_DESC_SIZE (sizeof(struct ural_rx_desc)) 22 #define RAL_TX_DESC_SIZE (sizeof(struct ural_tx_desc)) 23 24 #define RAL_CONFIG_NO 1 25 #define RAL_IFACE_INDEX 0 26 27 #define RAL_VENDOR_REQUEST 0x01 28 #define RAL_WRITE_MAC 0x02 29 #define RAL_READ_MAC 0x03 30 #define RAL_WRITE_MULTI_MAC 0x06 31 #define RAL_READ_MULTI_MAC 0x07 32 #define RAL_READ_EEPROM 0x09 33 34 /* 35 * MAC registers. 36 */ 37 #define RAL_MAC_CSR0 0x0400 /* ASIC Version */ 38 #define RAL_MAC_CSR1 0x0402 /* System control */ 39 #define RAL_MAC_CSR2 0x0404 /* MAC addr0 */ 40 #define RAL_MAC_CSR3 0x0406 /* MAC addr1 */ 41 #define RAL_MAC_CSR4 0x0408 /* MAC addr2 */ 42 #define RAL_MAC_CSR5 0x040a /* BSSID0 */ 43 #define RAL_MAC_CSR6 0x040c /* BSSID1 */ 44 #define RAL_MAC_CSR7 0x040e /* BSSID2 */ 45 #define RAL_MAC_CSR8 0x0410 /* Max frame length */ 46 #define RAL_MAC_CSR9 0x0412 /* Timer control */ 47 #define RAL_MAC_CSR10 0x0414 /* Slot time */ 48 #define RAL_MAC_CSR11 0x0416 /* IFS */ 49 #define RAL_MAC_CSR12 0x0418 /* EIFS */ 50 #define RAL_MAC_CSR13 0x041a /* Power mode0 */ 51 #define RAL_MAC_CSR14 0x041c /* Power mode1 */ 52 #define RAL_MAC_CSR15 0x041e /* Power saving transition0 */ 53 #define RAL_MAC_CSR16 0x0420 /* Power saving transition1 */ 54 #define RAL_MAC_CSR17 0x0422 /* Power state control */ 55 #define RAL_MAC_CSR18 0x0424 /* Auto wake-up control */ 56 #define RAL_MAC_CSR19 0x0426 /* GPIO control */ 57 #define RAL_MAC_CSR20 0x0428 /* LED control0 */ 58 #define RAL_MAC_CSR22 0x042c /* XXX not documented */ 59 60 /* 61 * Tx/Rx Registers. 62 */ 63 #define RAL_TXRX_CSR0 0x0440 /* Security control */ 64 #define RAL_TXRX_CSR2 0x0444 /* Rx control */ 65 #define RAL_TXRX_CSR5 0x044a /* CCK Tx BBP ID0 */ 66 #define RAL_TXRX_CSR6 0x044c /* CCK Tx BBP ID1 */ 67 #define RAL_TXRX_CSR7 0x044e /* OFDM Tx BBP ID0 */ 68 #define RAL_TXRX_CSR8 0x0450 /* OFDM Tx BBP ID1 */ 69 #define RAL_TXRX_CSR10 0x0454 /* Auto responder control */ 70 #define RAL_TXRX_CSR11 0x0456 /* Auto responder basic rate */ 71 #define RAL_TXRX_CSR18 0x0464 /* Beacon interval */ 72 #define RAL_TXRX_CSR19 0x0466 /* Beacon/sync control */ 73 #define RAL_TXRX_CSR20 0x0468 /* Beacon alignment */ 74 #define RAL_TXRX_CSR21 0x046a /* XXX not documented */ 75 76 /* 77 * Security registers. 78 */ 79 #define RAL_SEC_CSR0 0x0480 /* Shared key 0, word 0 */ 80 81 /* 82 * PHY registers. 83 */ 84 #define RAL_PHY_CSR2 0x04c4 /* Tx MAC configuration */ 85 #define RAL_PHY_CSR4 0x04c8 /* Interface configuration */ 86 #define RAL_PHY_CSR5 0x04ca /* BBP Pre-Tx CCK */ 87 #define RAL_PHY_CSR6 0x04cc /* BBP Pre-Tx OFDM */ 88 #define RAL_PHY_CSR7 0x04ce /* BBP serial control */ 89 #define RAL_PHY_CSR8 0x04d0 /* BBP serial status */ 90 #define RAL_PHY_CSR9 0x04d2 /* RF serial control0 */ 91 #define RAL_PHY_CSR10 0x04d4 /* RF serial control1 */ 92 93 /* 94 * Statistics registers. 95 */ 96 #define RAL_STA_CSR0 0x04e0 /* FCS error */ 97 98 99 #define RAL_DISABLE_RX (1 << 0) 100 #define RAL_DROP_CRC_ERROR (1 << 1) 101 #define RAL_DROP_PHY_ERROR (1 << 2) 102 #define RAL_DROP_CTL (1 << 3) 103 #define RAL_DROP_NOT_TO_ME (1 << 4) 104 #define RAL_DROP_TODS (1 << 5) 105 #define RAL_DROP_VERSION_ERROR (1 << 6) 106 #define RAL_DROP_MULTICAST (1 << 9) 107 #define RAL_DROP_BROADCAST (1 << 10) 108 109 #define RAL_SHORT_PREAMBLE (1 << 2) 110 111 #define RAL_HOST_READY (1 << 2) 112 #define RAL_RESET_ASIC (1 << 0) 113 #define RAL_RESET_BBP (1 << 1) 114 115 #define RAL_ENABLE_TSF (1 << 0) 116 #define RAL_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) 117 #define RAL_ENABLE_TBCN (1 << 3) 118 #define RAL_ENABLE_BEACON_GENERATOR (1 << 4) 119 120 #define RAL_RF_AWAKE (3 << 7) 121 #define RAL_BBP_AWAKE (3 << 5) 122 123 #define RAL_BBP_WRITE (1 << 15) 124 #define RAL_BBP_BUSY (1 << 0) 125 126 #define RAL_RF1_AUTOTUNE 0x08000 127 #define RAL_RF3_AUTOTUNE 0x00040 128 129 #define RAL_RF_2522 0x00 130 #define RAL_RF_2523 0x01 131 #define RAL_RF_2524 0x02 132 #define RAL_RF_2525 0x03 133 #define RAL_RF_2525E 0x04 134 #define RAL_RF_2526 0x05 135 /* dual-band RF */ 136 #define RAL_RF_5222 0x10 137 138 #define RAL_BBP_VERSION 0 139 #define RAL_BBP_TX 2 140 #define RAL_BBP_RX 14 141 142 #define RAL_BBP_ANTA 0x00 143 #define RAL_BBP_DIVERSITY 0x01 144 #define RAL_BBP_ANTB 0x02 145 #define RAL_BBP_ANTMASK 0x03 146 #define RAL_BBP_FLIPIQ 0x04 147 148 #define RAL_JAPAN_FILTER 0x08 149 150 struct ural_tx_desc { 151 uint32_t flags; 152 #define RAL_TX_RETRY(x) ((x) << 4) 153 #define RAL_TX_MORE_FRAG (1 << 8) 154 #define RAL_TX_ACK (1 << 9) 155 #define RAL_TX_TIMESTAMP (1 << 10) 156 #define RAL_TX_OFDM (1 << 11) 157 #define RAL_TX_NEWSEQ (1 << 12) 158 159 #define RAL_TX_IFS_MASK 0x00006000 160 #define RAL_TX_IFS_BACKOFF (0 << 13) 161 #define RAL_TX_IFS_SIFS (1 << 13) 162 #define RAL_TX_IFS_NEWBACKOFF (2 << 13) 163 #define RAL_TX_IFS_NONE (3 << 13) 164 165 uint16_t wme; 166 #define RAL_LOGCWMAX(x) (((x) & 0xf) << 12) 167 #define RAL_LOGCWMIN(x) (((x) & 0xf) << 8) 168 #define RAL_AIFSN(x) (((x) & 0x3) << 6) 169 #define RAL_IVOFFSET(x) (((x) & 0x3f)) 170 171 uint16_t reserved; 172 uint8_t plcp_signal; 173 uint8_t plcp_service; 174 #define RAL_PLCP_LENGEXT 0x80 175 176 uint8_t plcp_length_lo; 177 uint8_t plcp_length_hi; 178 uint32_t iv; 179 uint32_t eiv; 180 } __packed; 181 182 struct ural_rx_desc { 183 uint32_t flags; 184 #define RAL_RX_CRC_ERROR (1 << 5) 185 #define RAL_RX_OFDM (1 << 6) 186 #define RAL_RX_PHY_ERROR (1 << 7) 187 188 uint8_t rate; 189 uint8_t rssi; 190 uint16_t reserved; 191 192 uint32_t iv; 193 uint32_t eiv; 194 } __packed; 195 196 #define RAL_RF_LOBUSY (1 << 15) 197 #define RAL_RF_BUSY (1U << 31) 198 #define RAL_RF_20BIT (20 << 24) 199 200 #define RAL_RF1 0 201 #define RAL_RF2 2 202 #define RAL_RF3 1 203 #define RAL_RF4 3 204 205 #define RAL_EEPROM_ADDRESS 0x0004 206 #define RAL_EEPROM_TXPOWER 0x003c 207 #define RAL_EEPROM_CONFIG0 0x0016 208 #define RAL_EEPROM_BBP_BASE 0x001c 209