1 /* $NetBSD: tcxreg.h,v 1.6 2014/07/16 17:58:35 macallan Exp $ */ 2 /* 3 * Copyright (c) 1996 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Paul Kranenburg. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * differences between S24 and tcx, as far as this driver is concerned: 33 * - S24 has 4MB VRAM, 24bit + 2bit control planes, no expansion possible 34 * - tcx has 1MB VRAM, 8bit, no control planes, may have a VSIMM that bumps 35 * VRAM to 2MB 36 * - tcx can apply ROPs to STIP operations, unlike S24 37 * - tcx has a Bt458 DAC, just like CG6. S24 has an AT&T 20C567 38 * - the chip itself seems to be (almost) the same, just with different DACs 39 * and VRAM configuration 40 */ 41 42 /* 43 * A TCX is composed of numerous groups of control registers, all with TLAs: 44 * DHC - ??? 45 * TEC - transform engine control? 46 * THC - TEC Hardware Configuration 47 * ROM - a 128Kbyte ROM with who knows what in it. 48 * STIP - stipple engine, doesn't write attribute bits 49 * RSTIP - stipple engine, writes attribute bits 50 * BLIT - blit engine, doesn't copy attribute bits 51 * RBLIT - blit engine, does copy attribute bits 52 * ALT - ??? 53 * colormap - see below 54 * frame buffer memory (video RAM) 55 * possible other stuff 56 * 57 * RSTIP and RBLIT are set to size zero on my SS4's tcx, they work anyway 58 * though. No sense using them since tcx has only the lower 8bit planes, 59 * with no control planes, so there is no actual difference to STIP and 60 * BLIT ops, and things like qemu and temlib may not actually implement 61 * them. 62 * The hardware cursor registers in the THC range are cut off by the size 63 * attribute but seem to exist, although the parts that display the cursor 64 * ( the DAC's overlay support ) only exist on the S24. 65 * At this point I wouldn't be surprised if 8bit tcx actually supports 66 * the DFB24 and RDFB32 ranges, with the upper planes returning garbage. 67 */ 68 69 #define TCX_REG_DFB8 0 70 #define TCX_REG_DFB24 1 71 #define TCX_REG_STIP 2 72 #define TCX_REG_BLIT 3 73 #define TCX_REG_RDFB32 4 74 #define TCX_REG_RSTIP 5 75 #define TCX_REG_RBLIT 6 76 #define TCX_REG_TEC 7 77 #define TCX_REG_CMAP 8 78 #define TCX_REG_THC 9 79 #define TCX_REG_ROM 10 80 #define TCX_REG_DHC 11 81 #define TCX_REG_ALT 12 82 83 #define TCX_NREG 13 84 85 /* 86 * The S24 provides the framebuffer RAM mapped in three ways: 87 * 26 bits used per pixel, in 32-bit words; the low-order 24 bits are 88 * blue, green, and red values, and the other two bits select the 89 * display modes, per pixel); 90 * 24 bits per pixel, in 32-bit words; the high-order byte reads as 91 * zero, and is ignored on writes (so the mode bits cannot be altered); 92 * 8 bits per pixel, unpadded; writes to this space do not modify the 93 * other 18 bits. 94 */ 95 #define TCX_CTL_8_MAPPED 0x00000000 /* 8 bits, uses color map */ 96 #define TCX_CTL_24_MAPPED 0x01000000 /* 24 bits, uses color map */ 97 #define TCX_CTL_24_LEVEL 0x03000000 /* 24 bits, ignores color map */ 98 #define TCX_CTL_PIXELMASK 0x00FFFFFF /* mask for index/level */ 99 /* 100 * The DAC actually supports other bits, for example to select between the 101 * red and green plane for 8bit output. Not useful here since we can only 102 * access the red plane as 8bit framebuffer. 103 */ 104 105 /* 106 * The layout of the THC. 107 */ 108 109 #define THC_CONFIG 0x00000000 110 #define THC_SENSEBUS 0x00000080 111 #define THC_DELAY 0x00000090 112 #define THC_STRAPPING 0x00000094 113 #define THC_LINECOUNTER 0x0000009c 114 #define THC_HSYNC_START 0x000000a0 115 #define THC_HSYNC_END 0x000000a4 116 #define THC_HDISP_START 0x000000a8 117 #define THC_HDISP_VSYNC 0x000000ac 118 #define THC_HDISP_END 0x000000b0 119 #define THC_MISC 0x00000818 120 #define THC_CURSOR_POS 0x000008fc 121 #define THC_CURSOR_1 0x00000900 /* bitmap bit 1 */ 122 #define THC_CURSOR_0 0x00000980 /* bitmap bit 0 */ 123 124 /* bits in thc_config ??? */ 125 #define THC_CFG_FBID 0xf0000000 /* id mask */ 126 #define THC_CFG_FBID_SHIFT 28 127 #define THC_CFG_SENSE 0x07000000 /* sense mask */ 128 #define THC_CFG_SENSE_SHIFT 24 129 #define THC_CFG_REV 0x00f00000 /* revision mask */ 130 #define THC_CFG_REV_SHIFT 20 131 #define THC_CFG_RST 0x00008000 /* reset */ 132 133 /* bits in thc_hcmisc */ 134 #define THC_MISC_OPENFLG 0x80000000 /* open flag (what's that?) */ 135 #define THC_MISC_SWERR_EN 0x20000000 /* enable SW error interrupt */ 136 #define THC_MISC_VSYNC_LEVEL 0x08000000 /* vsync level when disabled */ 137 #define THC_MISC_HSYNC_LEVEL 0x04000000 /* hsync level when disabled */ 138 #define THC_MISC_VSYNC_DISABLE 0x02000000 /* vsync disable */ 139 #define THC_MISC_HSYNC_DISABLE 0x01000000 /* hsync disable */ 140 #define THC_MISC_XXX1 0x00ffe000 /* unused */ 141 #define THC_MISC_RESET 0x00001000 /* ??? */ 142 #define THC_MISC_XXX2 0x00000800 /* unused */ 143 #define THC_MISC_VIDEN 0x00000400 /* video enable */ 144 #define THC_MISC_SYNC 0x00000200 /* not sure what ... */ 145 #define THC_MISC_VSYNC 0x00000100 /* ... these really are */ 146 #define THC_MISC_SYNCEN 0x00000080 /* sync enable */ 147 #define THC_MISC_CURSRES 0x00000040 /* cursor resolution */ 148 #define THC_MISC_INTEN 0x00000020 /* v.retrace intr enable */ 149 #define THC_MISC_INTR 0x00000010 /* intr pending / ack bit */ 150 #define THC_MISC_DACWAIT 0x0000000f /* ??? */ 151 152 /* 153 * Partial description of TEC. 154 */ 155 struct tcx_tec { 156 u_int tec_config; /* what's in it? */ 157 u_int tec_xxx0[35]; 158 u_int tec_delay; /* */ 159 #define TEC_DELAY_SYNC 0x00000f00 160 #define TEC_DELAY_WR_F 0x000000c0 161 #define TEC_DELAY_WR_R 0x00000030 162 #define TEC_DELAY_SOE_F 0x0000000c 163 #define TEC_DELAY_SOE_S 0x00000003 164 u_int tec_strapping; /* */ 165 #define TEC_STRAP_FIFO_LIMIT 0x00f00000 166 #define TEC_STRAP_CACHE_EN 0x00010000 167 #define TEC_STRAP_ZERO_OFFSET 0x00008000 168 #define TEC_STRAP_REFRSH_DIS 0x00004000 169 #define TEC_STRAP_REF_LOAD 0x00001000 170 #define TEC_STRAP_REFRSH_PERIOD 0x000003ff 171 u_int tec_hcmisc; /* */ 172 u_int tec_linecount; /* */ 173 u_int tec_hss; /* */ 174 u_int tec_hse; /* */ 175 u_int tec_hds; /* */ 176 u_int tec_hsedvs; /* */ 177 u_int tec_hde; /* */ 178 u_int tec_vss; /* */ 179 u_int tec_vse; /* */ 180 u_int tec_vds; /* */ 181 u_int tec_vde; /* */ 182 }; 183 184 /* DAC registers */ 185 #define DAC_ADDRESS 0x00000000 186 #define DAC_FB_LUT 0x00000004 /* palette / gamma table */ 187 #define DAC_CONTROL_1 0x00000008 188 #define DAC_CURSOR_LUT 0x0000000c /* cursor sprite colours */ 189 #define DAC_CONTROL_2 0x00000018 190 191 #define DAC_C1_ID 0 192 #define DAC_C1_REVISION 1 193 #define DAC_C1_READ_MASK 4 194 #define DAC_C1_BLINK_MASK 5 195 #define DAC_C1_CONTROL_0 6 196