1 /* $NetBSD: if_vtereg.h,v 1.2 2011/04/28 17:32:48 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * FreeBSD: src/sys/dev/vte/if_vtereg.h,v 1.1 2010/12/31 00:21:41 yongari Exp 30 */ 31 32 #ifndef _IF_VTEREG_H 33 #define _IF_VTEREG_H 34 35 /* registers are mapped in i/o or memory space */ 36 #define VTE_PCI_BIO 0x10 37 #define VTE_PCI_BMEM 0x14 38 39 /* MAC control register 0 */ 40 #define VTE_MCR0 0x00 41 #define MCR0_ACCPT_ERR 0x0001 42 #define MCR0_RX_ENB 0x0002 43 #define MCR0_ACCPT_RUNT 0x0004 44 #define MCR0_ACCPT_LONG_PKT 0x0008 45 #define MCR0_ACCPT_DRIBBLE 0x0010 46 #define MCR0_PROMISC 0x0020 47 #define MCR0_BROADCAST_DIS 0x0040 48 #define MCR0_RX_EARLY_INTR 0x0080 49 #define MCR0_MULTICAST 0x0100 50 #define MCR0_FC_ENB 0x0200 51 #define MCR0_TX_ENB 0x1000 52 #define MCR0_TX_EARLY_INTR 0x4000 53 #define MCR0_FULL_DUPLEX 0x8000 54 55 /* MAC control register 1 */ 56 #define VTE_MCR1 0x04 57 #define MCR1_MAC_RESET 0x0001 58 #define MCR1_MAC_LOOPBACK 0x0002 59 #define MCR1_EXCESS_COL_RETRANS_DIS 0x0004 60 #define MCR1_AUTO_CHG_DUPLEX 0x0008 61 #define MCR1_PKT_LENGTH_1518 0x0010 62 #define MCR1_PKT_LENGTH_1522 0x0020 63 #define MCR1_PKT_LENGTH_1534 0x0030 64 #define MCR1_PKT_LENGTH_1537 0x0000 65 #define MCR1_EARLY_INTR_THRESH_1129 0x0000 66 #define MCR1_EARLY_INTR_THRESH_1257 0x0040 67 #define MCR1_EARLY_INTR_THRESH_1385 0x0080 68 #define MCR1_EARLY_INTR_THRESH_1513 0x00C0 69 #define MCR1_EXCESS_COL_RETRY_16 0x0000 70 #define MCR1_EXCESS_COL_RETRY_32 0x0100 71 #define MCR1_FC_ACTIVE 0x0200 72 #define MCR1_RX_DESC_HASH_IDX 0x4000 73 #define MCR1_RX_UNICAST_HASH 0x8000 74 75 #define MCR1_PKT_LENGTH_MASK 0x0030 76 #define MCR1_EARLY_INTR_THRESH_MASK 0x00C0 77 78 /* MAC bus control register */ 79 #define VTE_MBCR 0x08 80 #define MBCR_FIFO_XFER_LENGTH_4 0x0000 81 #define MBCR_FIFO_XFER_LENGTH_8 0x0001 82 #define MBCR_FIFO_XFER_LENGTH_16 0x0002 83 #define MBCR_FIFO_XFER_LENGTH_32 0x0003 84 #define MBCR_TX_FIFO_THRESH_16 0x0000 85 #define MBCR_TX_FIFO_THRESH_32 0x0004 86 #define MBCR_TX_FIFO_THRESH_64 0x0008 87 #define MBCR_TX_FIFO_THRESH_96 0x000C 88 #define MBCR_RX_FIFO_THRESH_8 0x0000 89 #define MBCR_RX_FIFO_THRESH_16 0x0010 90 #define MBCR_RX_FIFO_THRESH_32 0x0020 91 #define MBCR_RX_FIFO_THRESH_64 0x0030 92 #define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00 93 #define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8 94 #define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00 95 96 /* MAC TX interrupt control register */ 97 #define VTE_MTICR 0x0C 98 #define MTICR_TX_TIMER_MASK 0x001F 99 #define MTICR_TX_BUNDLE_MASK 0x0F00 100 #define VTE_IM_TX_TIMER_DEFAULT 0x7F 101 #define VTE_IM_TX_BUNDLE_DEFAULT 15 102 103 #define VTE_IM_TIMER_MIN 0 104 #define VTE_IM_TIMER_MAX 82 105 #define VTE_IM_TIMER_MASK 0x001F 106 #define VTE_IM_TIMER_SHIFT 0 107 #define VTE_IM_BUNDLE_MIN 0 108 #define VTE_IM_BUNDLE_MAX 15 109 #define VTE_IM_BUNDLE_SHIFT 8 110 111 /* MAC RX interrupt control register */ 112 #define VTE_MRICR 0x10 113 #define MRICR_RX_TIMER_MASK 0x001F 114 #define MRICR_RX_BUNDLE_MASK 0x0F00 115 #define VTE_IM_RX_TIMER_DEFAULT 0x7F 116 #define VTE_IM_RX_BUNDLE_DEFAULT 15 117 118 /* MAC TX poll command register */ 119 #define VTE_TX_POLL 0x14 120 #define TX_POLL_START 0x0001 121 122 /* MAC RX buffer size register */ 123 #define VTE_MRBSR 0x18 124 #define VTE_MRBSR_SIZE_MASK 0x03FF 125 126 /* MAC RX descriptor control register */ 127 #define VTE_MRDCR 0x1A 128 #define VTE_MRDCR_RESIDUE_MASK 0x00FF 129 #define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00 130 #define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8 131 132 /* MAC Last status register */ 133 #define VTE_MLSR 0x1C 134 #define MLSR_MULTICAST 0x0001 135 #define MLSR_BROADCAST 0x0002 136 #define MLSR_CRC_ERR 0x0004 137 #define MLSR_RUNT 0x0008 138 #define MLSR_LONG_PKT 0x0010 139 #define MLSR_TRUNC 0x0020 140 #define MLSR_DRIBBLE 0x0040 141 #define MLSR_PHY_ERR 0x0080 142 #define MLSR_TX_FIFO_UNDERRUN 0x0200 143 #define MLSR_RX_DESC_UNAVAIL 0x0400 144 #define MLSR_TX_EXCESS_COL 0x2000 145 #define MLSR_TX_LATE_COL 0x4000 146 #define MLSR_RX_FIFO_OVERRUN 0x8000 147 148 /* MAC MDIO control register */ 149 #define VTE_MMDIO 0x20 150 #define MMDIO_REG_ADDR_MASK 0x001F 151 #define MMDIO_PHY_ADDR_MASK 0x1F00 152 #define MMDIO_READ 0x2000 153 #define MMDIO_WRITE 0x4000 154 #define MMDIO_REG_ADDR_SHIFT 0 155 #define MMDIO_PHY_ADDR_SHIFT 8 156 157 /* MAC MDIO read data register */ 158 #define VTE_MMRD 0x24 159 #define MMRD_DATA_MASK 0xFFFF 160 161 /* MAC MDIO write data register */ 162 #define VTE_MMWD 0x28 163 #define MMWD_DATA_MASK 0xFFFF 164 165 /* MAC TX descriptor start address 0 */ 166 #define VTE_MTDSA0 0x2C 167 168 /* MAC TX descriptor start address 1 */ 169 #define VTE_MTDSA1 0x30 170 171 /* MAC RX descriptor start address 0 */ 172 #define VTE_MRDSA0 0x34 173 174 /* MAC RX descriptor start address 1 */ 175 #define VTE_MRDSA1 0x38 176 177 /* MAC Interrupt status register */ 178 #define VTE_MISR 0x3C 179 #define MISR_RX_DONE 0x0001 180 #define MISR_RX_DESC_UNAVAIL 0x0002 181 #define MISR_RX_FIFO_FULL 0x0004 182 #define MISR_RX_EARLY_INTR 0x0008 183 #define MISR_TX_DONE 0x0010 184 #define MISR_TX_EARLY_INTR 0x0080 185 #define MISR_EVENT_CNT_OFLOW 0x0100 186 #define MISR_PHY_MEDIA_CHG 0x0200 187 188 /* MAC Interrupt enable register */ 189 #define VTE_MIER 0x40 190 191 #define VTE_INTRS \ 192 (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \ 193 MISR_TX_DONE | MISR_EVENT_CNT_OFLOW) 194 195 /* MAC Event counter interrupt status register */ 196 #define VTE_MECISR 0x44 197 #define MECISR_EC_RX_DONE 0x0001 198 #define MECISR_EC_MULTICAST 0x0002 199 #define MECISR_EC_BROADCAST 0x0004 200 #define MECISR_EC_CRC_ERR 0x0008 201 #define MECISR_EC_RUNT 0x0010 202 #define MESCIR_EC_LONG_PKT 0x0020 203 #define MESCIR_EC_RX_DESC_UNAVAIL 0x0080 204 #define MESCIR_EC_RX_FIFO_FULL 0x0100 205 #define MESCIR_EC_TX_DONE 0x0200 206 #define MESCIR_EC_LATE_COL 0x0400 207 #define MESCIR_EC_TX_UNDERRUN 0x0800 208 209 /* MAC Event counter interrupt enable register */ 210 #define VTE_MECIER 0x48 211 #define VTE_MECIER_INTRS \ 212 (MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \ 213 MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \ 214 MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \ 215 MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN) 216 217 #define VTE_CNT_RX_DONE 0x50 218 219 #define VTE_CNT_MECNT0 0x52 220 221 #define VTE_CNT_MECNT1 0x54 222 223 #define VTE_CNT_MECNT2 0x56 224 225 #define VTE_CNT_MECNT3 0x58 226 227 #define VTE_CNT_TX_DONE 0x5A 228 229 #define VTE_CNT_MECNT4 0x5C 230 231 #define VTE_CNT_PAUSE 0x5E 232 233 /* MAC Hash table register */ 234 #define VTE_MAR0 0x60 235 #define VTE_MAR1 0x62 236 #define VTE_MAR2 0x64 237 #define VTE_MAR3 0x66 238 239 /* MAC station address and multicast address register */ 240 #define VTE_MID0L 0x68 241 #define VTE_MID0M 0x6A 242 #define VTE_MID0H 0x6C 243 #define VTE_MID1L 0x70 244 #define VTE_MID1M 0x72 245 #define VTE_MID1H 0x74 246 #define VTE_MID2L 0x78 247 #define VTE_MID2M 0x7A 248 #define VTE_MID2H 0x7C 249 #define VTE_MID3L 0x80 250 #define VTE_MID3M 0x82 251 #define VTE_MID3H 0x84 252 253 #define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L 254 #define VTE_RXFILT_PERFECT_CNT 3 255 256 /* MAC PHY status change configuration register */ 257 #define VTE_MPSCCR 0x88 258 #define MPSCCR_TIMER_DIVIDER_MASK 0x0007 259 #define MPSCCR_PHY_ADDR_MASK 0x1F00 260 #define MPSCCR_PHY_STS_CHG_ENB 0x8000 261 #define MPSCCR_PHY_ADDR_SHIFT 8 262 263 /* MAC PHY status register2 */ 264 #define VTE_MPSR 0x8A 265 #define MPSR_LINK_UP 0x0001 266 #define MPSR_SPEED_100 0x0002 267 #define MPSR_FULL_DUPLEX 0x0004 268 269 /* MAC Status machine(undocumented). */ 270 #define VTE_MACSM 0xAC 271 272 /* MDC Speed control register */ 273 #define VTE_MDCSC 0xB6 274 #define MDCSC_DEFAULT 0x0030 275 276 /* MAC Identifier and revision register */ 277 #define VTE_MACID_REV 0xBC 278 #define VTE_MACID_REV_MASK 0x00FF 279 #define VTE_MACID_MASK 0xFF00 280 #define VTE_MACID_REV_SHIFT 0 281 #define VTE_MACID_SHIFT 8 282 283 /* MAC Identifier register */ 284 #define VTE_MACID 0xBE 285 286 /* 287 * RX descriptor 288 * - Added one more uint16_t member to align it 4 on bytes boundary. 289 * This does not affect operation of controller since it includes 290 * next pointer address. 291 */ 292 struct vte_rx_desc { 293 uint16_t drst; 294 uint16_t drlen; 295 uint32_t drbp; 296 uint32_t drnp; 297 uint16_t hidx; 298 uint16_t rsvd2; 299 uint16_t rsvd3; 300 uint16_t __pad; /* Not actual descriptor member. */ 301 }; 302 303 #define VTE_DRST_MID_MASK 0x0003 304 #define VTE_DRST_MID_HIT 0x0004 305 #define VTE_DRST_MULTICAST_HIT 0x0008 306 #define VTE_DRST_MULTICAST 0x0010 307 #define VTE_DRST_BROADCAST 0x0020 308 #define VTE_DRST_CRC_ERR 0x0040 309 #define VTE_DRST_RUNT 0x0080 310 #define VTE_DRST_LONG 0x0100 311 #define VTE_DRST_TRUNC 0x0200 312 #define VTE_DRST_DRIBBLE 0x0400 313 #define VTE_DRST_PHY_ERR 0x0800 314 #define VTE_DRST_RX_OK 0x4000 315 #define VTE_DRST_RX_OWN 0x8000 316 317 #define VTE_RX_LEN(x) ((x) & 0x7FF) 318 319 #define VTE_RX_HIDX(x) ((x) & 0x3F) 320 321 /* 322 * TX descriptor 323 * - Added one more uint32_t member to align it on 16 bytes boundary. 324 */ 325 struct vte_tx_desc { 326 uint16_t dtst; 327 uint16_t dtlen; 328 uint32_t dtbp; 329 uint32_t dtnp; 330 uint32_t __pad; /* Not actual descriptor member. */ 331 }; 332 333 #define VTE_DTST_EXCESS_COL 0x0010 334 #define VTE_DTST_LATE_COL 0x0020 335 #define VTE_DTST_UNDERRUN 0x0040 336 #define VTE_DTST_NO_CRC 0x2000 337 #define VTE_DTST_TX_OK 0x4000 338 #define VTE_DTST_TX_OWN 0x8000 339 340 #define VTE_TX_LEN(x) ((x) & 0x7FF) 341 342 #endif /* _IF_VTEREG_H */ 343