1 /* $NetBSD: if_sk.c,v 1.113 2024/07/05 04:31:51 rin Exp $ */
2
3 /*-
4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /* $OpenBSD: if_sk.c,v 1.116 2006/06/22 23:06:03 brad Exp $ */
30
31 /*
32 * Copyright (c) 1997, 1998, 1999, 2000
33 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
37 * are met:
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
43 * 3. All advertising materials mentioning features or use of this software
44 * must display the following acknowledgement:
45 * This product includes software developed by Bill Paul.
46 * 4. Neither the name of the author nor the names of any co-contributors
47 * may be used to endorse or promote products derived from this software
48 * without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
60 * THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
63 */
64
65 /*
66 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
67 *
68 * Permission to use, copy, modify, and distribute this software for any
69 * purpose with or without fee is hereby granted, provided that the above
70 * copyright notice and this permission notice appear in all copies.
71 *
72 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
73 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
74 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
75 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
76 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
77 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
78 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
79 */
80
81 /*
82 * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
83 * the SK-984x series adapters, both single port and dual port.
84 * References:
85 * The XaQti XMAC II datasheet,
86 * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
87 * The SysKonnect GEnesis manual, http://www.syskonnect.com
88 *
89 * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
90 * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
91 * convenience to others until Vitesse corrects this problem:
92 *
93 * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
94 *
95 * Written by Bill Paul <wpaul@ee.columbia.edu>
96 * Department of Electrical Engineering
97 * Columbia University, New York City
98 */
99
100 /*
101 * The SysKonnect gigabit ethernet adapters consist of two main
102 * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
103 * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
104 * components and a PHY while the GEnesis controller provides a PCI
105 * interface with DMA support. Each card may have between 512K and
106 * 2MB of SRAM on board depending on the configuration.
107 *
108 * The SysKonnect GEnesis controller can have either one or two XMAC
109 * chips connected to it, allowing single or dual port NIC configurations.
110 * SysKonnect has the distinction of being the only vendor on the market
111 * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
112 * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
113 * XMAC registers. This driver takes advantage of these features to allow
114 * both XMACs to operate as independent interfaces.
115 */
116
117 #include <sys/cdefs.h>
118 __KERNEL_RCSID(0, "$NetBSD: if_sk.c,v 1.113 2024/07/05 04:31:51 rin Exp $");
119
120 #include <sys/param.h>
121 #include <sys/systm.h>
122 #include <sys/sockio.h>
123 #include <sys/mbuf.h>
124 #include <sys/malloc.h>
125 #include <sys/mutex.h>
126 #include <sys/kernel.h>
127 #include <sys/socket.h>
128 #include <sys/device.h>
129 #include <sys/queue.h>
130 #include <sys/callout.h>
131 #include <sys/sysctl.h>
132 #include <sys/endian.h>
133
134 #include <net/if.h>
135 #include <net/if_dl.h>
136 #include <net/if_types.h>
137
138 #include <net/if_media.h>
139
140 #include <net/bpf.h>
141 #include <sys/rndsource.h>
142
143 #include <dev/mii/mii.h>
144 #include <dev/mii/miivar.h>
145 #include <dev/mii/brgphyreg.h>
146
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
149 #include <dev/pci/pcidevs.h>
150
151 /* #define SK_USEIOSPACE */
152
153 #include <dev/pci/if_skreg.h>
154 #include <dev/pci/if_skvar.h>
155
156 static int skc_probe(device_t, cfdata_t, void *);
157 static void skc_attach(device_t, device_t, void *);
158 static int sk_probe(device_t, cfdata_t, void *);
159 static void sk_attach(device_t, device_t, void *);
160 static int skcprint(void *, const char *);
161 static int sk_intr(void *);
162 static void sk_intr_bcom(struct sk_if_softc *);
163 static void sk_intr_xmac(struct sk_if_softc *);
164 static void sk_intr_yukon(struct sk_if_softc *);
165 static void sk_rxeof(struct sk_if_softc *);
166 static void sk_txeof(struct sk_if_softc *);
167 static int sk_encap(struct sk_if_softc *, struct mbuf *, uint32_t *);
168 static void sk_start(struct ifnet *);
169 static int sk_ioctl(struct ifnet *, u_long, void *);
170 static int sk_init(struct ifnet *);
171 static void sk_unreset_xmac(struct sk_if_softc *);
172 static void sk_init_xmac(struct sk_if_softc *);
173 static void sk_unreset_yukon(struct sk_if_softc *);
174 static void sk_init_yukon(struct sk_if_softc *);
175 static void sk_stop(struct ifnet *, int);
176 static void sk_watchdog(struct ifnet *);
177 static int sk_ifmedia_upd(struct ifnet *);
178 static void sk_reset(struct sk_softc *);
179 static int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t);
180 static int sk_alloc_jumbo_mem(struct sk_if_softc *);
181 static void *sk_jalloc(struct sk_if_softc *);
182 static void sk_jfree(struct mbuf *, void *, size_t, void *);
183 static int sk_init_rx_ring(struct sk_if_softc *);
184 static int sk_init_tx_ring(struct sk_if_softc *);
185 static uint8_t sk_vpd_readbyte(struct sk_softc *, int);
186 static void sk_vpd_read_res(struct sk_softc *, struct vpd_res *, int);
187 static void sk_vpd_read(struct sk_softc *);
188
189 static void sk_update_int_mod(struct sk_softc *);
190
191 static int sk_xmac_miibus_readreg(device_t, int, int, uint16_t *);
192 static int sk_xmac_miibus_writereg(device_t, int, int, uint16_t);
193 static void sk_xmac_miibus_statchg(struct ifnet *);
194
195 static int sk_marv_miibus_readreg(device_t, int, int, uint16_t *);
196 static int sk_marv_miibus_writereg(device_t, int, int, uint16_t);
197 static void sk_marv_miibus_statchg(struct ifnet *);
198
199 static uint32_t sk_xmac_hash(void *);
200 static uint32_t sk_yukon_hash(void *);
201 static void sk_setfilt(struct sk_if_softc *, void *, int);
202 static void sk_setmulti(struct sk_if_softc *);
203 static void sk_tick(void *);
204
205 static bool skc_suspend(device_t, const pmf_qual_t *);
206 static bool skc_resume(device_t, const pmf_qual_t *);
207 static bool sk_resume(device_t dv, const pmf_qual_t *);
208
209 /* #define SK_DEBUG 2 */
210 #ifdef SK_DEBUG
211 #define DPRINTF(x) if (skdebug) printf x
212 #define DPRINTFN(n, x) if (skdebug >= (n)) printf x
213 int skdebug = SK_DEBUG;
214
215 static void sk_dump_txdesc(struct sk_tx_desc *, int);
216 static void sk_dump_mbuf(struct mbuf *);
217 static void sk_dump_bytes(const char *, int);
218 #else
219 #define DPRINTF(x)
220 #define DPRINTFN(n, x)
221 #endif
222
223 static int sk_sysctl_handler(SYSCTLFN_PROTO);
224 static int sk_root_num;
225
226 /* supported device vendors */
227 /* PCI_PRODUCT_DLINK_DGE560T_2 might belong in if_msk instead */
228 static const struct device_compatible_entry compat_data[] = {
229 { .id = PCI_ID_CODE(PCI_VENDOR_3COM,
230 PCI_PRODUCT_3COM_3C940) },
231
232 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
233 PCI_PRODUCT_DLINK_DGE530T) },
234
235 { .id = PCI_ID_CODE(PCI_VENDOR_DLINK,
236 PCI_PRODUCT_DLINK_DGE560T_2) },
237
238 { .id = PCI_ID_CODE(PCI_VENDOR_LINKSYS,
239 PCI_PRODUCT_LINKSYS_EG1064) },
240
241 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
242 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE) },
243
244 { .id = PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
245 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2) },
246
247 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
248 PCI_PRODUCT_MARVELL_SKNET) },
249
250 { .id = PCI_ID_CODE(PCI_VENDOR_MARVELL,
251 PCI_PRODUCT_MARVELL_BELKIN) },
252
253 PCI_COMPAT_EOL
254 };
255
256 #define SK_LINKSYS_EG1032_SUBID 0x00151737
257
258 static inline uint32_t
sk_win_read_4(struct sk_softc * sc,uint32_t reg)259 sk_win_read_4(struct sk_softc *sc, uint32_t reg)
260 {
261 #ifdef SK_USEIOSPACE
262 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
263 return CSR_READ_4(sc, SK_WIN_BASE + SK_REG(reg));
264 #else
265 return CSR_READ_4(sc, reg);
266 #endif
267 }
268
269 static inline uint16_t
sk_win_read_2(struct sk_softc * sc,uint32_t reg)270 sk_win_read_2(struct sk_softc *sc, uint32_t reg)
271 {
272 #ifdef SK_USEIOSPACE
273 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
274 return CSR_READ_2(sc, SK_WIN_BASE + SK_REG(reg));
275 #else
276 return CSR_READ_2(sc, reg);
277 #endif
278 }
279
280 static inline uint8_t
sk_win_read_1(struct sk_softc * sc,uint32_t reg)281 sk_win_read_1(struct sk_softc *sc, uint32_t reg)
282 {
283 #ifdef SK_USEIOSPACE
284 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
285 return CSR_READ_1(sc, SK_WIN_BASE + SK_REG(reg));
286 #else
287 return CSR_READ_1(sc, reg);
288 #endif
289 }
290
291 static inline void
sk_win_write_4(struct sk_softc * sc,uint32_t reg,uint32_t x)292 sk_win_write_4(struct sk_softc *sc, uint32_t reg, uint32_t x)
293 {
294 #ifdef SK_USEIOSPACE
295 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
296 CSR_WRITE_4(sc, SK_WIN_BASE + SK_REG(reg), x);
297 #else
298 CSR_WRITE_4(sc, reg, x);
299 #endif
300 }
301
302 static inline void
sk_win_write_2(struct sk_softc * sc,uint32_t reg,uint16_t x)303 sk_win_write_2(struct sk_softc *sc, uint32_t reg, uint16_t x)
304 {
305 #ifdef SK_USEIOSPACE
306 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
307 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), x);
308 #else
309 CSR_WRITE_2(sc, reg, x);
310 #endif
311 }
312
313 static inline void
sk_win_write_1(struct sk_softc * sc,uint32_t reg,uint8_t x)314 sk_win_write_1(struct sk_softc *sc, uint32_t reg, uint8_t x)
315 {
316 #ifdef SK_USEIOSPACE
317 CSR_WRITE_4(sc, SK_RAP, SK_WIN(reg));
318 CSR_WRITE_1(sc, SK_WIN_BASE + SK_REG(reg), x);
319 #else
320 CSR_WRITE_1(sc, reg, x);
321 #endif
322 }
323
324 /*
325 * The VPD EEPROM contains Vital Product Data, as suggested in
326 * the PCI 2.1 specification. The VPD data is separated into areas
327 * denoted by resource IDs. The SysKonnect VPD contains an ID string
328 * resource (the name of the adapter), a read-only area resource
329 * containing various key/data fields and a read/write area which
330 * can be used to store asset management information or log messages.
331 * We read the ID string and read-only into buffers attached to
332 * the controller softc structure for later use. At the moment,
333 * we only use the ID string during sk_attach().
334 */
335 static uint8_t
sk_vpd_readbyte(struct sk_softc * sc,int addr)336 sk_vpd_readbyte(struct sk_softc *sc, int addr)
337 {
338 int i;
339
340 sk_win_write_2(sc, SK_PCI_REG(SK_PCI_VPD_ADDR), addr);
341 for (i = 0; i < SK_TIMEOUT; i++) {
342 DELAY(1);
343 if (sk_win_read_2(sc,
344 SK_PCI_REG(SK_PCI_VPD_ADDR)) & SK_VPD_FLAG)
345 break;
346 }
347
348 if (i == SK_TIMEOUT)
349 return 0;
350
351 return sk_win_read_1(sc, SK_PCI_REG(SK_PCI_VPD_DATA));
352 }
353
354 static void
sk_vpd_read_res(struct sk_softc * sc,struct vpd_res * res,int addr)355 sk_vpd_read_res(struct sk_softc *sc, struct vpd_res *res, int addr)
356 {
357 int i;
358 uint8_t *ptr;
359
360 ptr = (uint8_t *)res;
361 for (i = 0; i < sizeof(struct vpd_res); i++)
362 ptr[i] = sk_vpd_readbyte(sc, i + addr);
363 }
364
365 static void
sk_vpd_read(struct sk_softc * sc)366 sk_vpd_read(struct sk_softc *sc)
367 {
368 int pos = 0, i;
369 struct vpd_res res;
370
371 if (sc->sk_vpd_prodname != NULL)
372 free(sc->sk_vpd_prodname, M_DEVBUF);
373 if (sc->sk_vpd_readonly != NULL)
374 free(sc->sk_vpd_readonly, M_DEVBUF);
375 sc->sk_vpd_prodname = NULL;
376 sc->sk_vpd_readonly = NULL;
377
378 sk_vpd_read_res(sc, &res, pos);
379
380 if (res.vr_id != VPD_RES_ID) {
381 aprint_error_dev(sc->sk_dev,
382 "bad VPD resource id: expected %x got %x\n",
383 VPD_RES_ID, res.vr_id);
384 return;
385 }
386
387 pos += sizeof(res);
388 sc->sk_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_WAITOK);
389 for (i = 0; i < res.vr_len; i++)
390 sc->sk_vpd_prodname[i] = sk_vpd_readbyte(sc, i + pos);
391 sc->sk_vpd_prodname[i] = '\0';
392 pos += i;
393
394 sk_vpd_read_res(sc, &res, pos);
395
396 if (res.vr_id != VPD_RES_READ) {
397 aprint_error_dev(sc->sk_dev,
398 "bad VPD resource id: expected %x got %x\n",
399 VPD_RES_READ, res.vr_id);
400 return;
401 }
402
403 pos += sizeof(res);
404 sc->sk_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_WAITOK);
405 for (i = 0; i < res.vr_len ; i++)
406 sc->sk_vpd_readonly[i] = sk_vpd_readbyte(sc, i + pos);
407 }
408
409 static int
sk_xmac_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)410 sk_xmac_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
411 {
412 struct sk_if_softc *sc_if = device_private(dev);
413 int i;
414
415 DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
416
417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
418 return -1;
419
420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
421 SK_XM_READ_2(sc_if, XM_PHY_DATA);
422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
423 for (i = 0; i < SK_TIMEOUT; i++) {
424 DELAY(1);
425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
426 XM_MMUCMD_PHYDATARDY)
427 break;
428 }
429
430 if (i == SK_TIMEOUT) {
431 aprint_error_dev(sc_if->sk_dev,
432 "phy failed to come ready\n");
433 return ETIMEDOUT;
434 }
435 }
436 DELAY(1);
437 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA);
438 return 0;
439 }
440
441 static int
sk_xmac_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)442 sk_xmac_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
443 {
444 struct sk_if_softc *sc_if = device_private(dev);
445 int i;
446
447 DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
448
449 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
450 for (i = 0; i < SK_TIMEOUT; i++) {
451 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
452 break;
453 }
454
455 if (i == SK_TIMEOUT) {
456 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n");
457 return ETIMEDOUT;
458 }
459
460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
461 for (i = 0; i < SK_TIMEOUT; i++) {
462 DELAY(1);
463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
464 break;
465 }
466
467 if (i == SK_TIMEOUT) {
468 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n");
469 return ETIMEDOUT;
470 }
471
472 return 0;
473 }
474
475 static void
sk_xmac_miibus_statchg(struct ifnet * ifp)476 sk_xmac_miibus_statchg(struct ifnet *ifp)
477 {
478 struct sk_if_softc *sc_if = ifp->if_softc;
479 struct mii_data *mii = &sc_if->sk_mii;
480
481 DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
482
483 /*
484 * If this is a GMII PHY, manually set the XMAC's
485 * duplex mode accordingly.
486 */
487 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
488 if ((mii->mii_media_active & IFM_FDX) != 0)
489 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
490 else
491 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
492 }
493 }
494
495 static int
sk_marv_miibus_readreg(device_t dev,int phy,int reg,uint16_t * val)496 sk_marv_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
497 {
498 struct sk_if_softc *sc_if = device_private(dev);
499 uint16_t data;
500 int i;
501
502 if (phy != 0 ||
503 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
504 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
505 DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
506 phy, reg));
507 return -1;
508 }
509
510 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
511 YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
512
513 for (i = 0; i < SK_TIMEOUT; i++) {
514 DELAY(1);
515 data = SK_YU_READ_2(sc_if, YUKON_SMICR);
516 if (data & YU_SMICR_READ_VALID)
517 break;
518 }
519
520 if (i == SK_TIMEOUT) {
521 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n");
522 return ETIMEDOUT;
523 }
524
525 DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
526 SK_TIMEOUT));
527
528 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
529
530 DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#hx\n",
531 phy, reg, *val));
532
533 return 0;
534 }
535
536 static int
sk_marv_miibus_writereg(device_t dev,int phy,int reg,uint16_t val)537 sk_marv_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
538 {
539 struct sk_if_softc *sc_if = device_private(dev);
540 int i;
541
542 DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#hx\n",
543 phy, reg, val));
544
545 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
546 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
547 YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
548
549 for (i = 0; i < SK_TIMEOUT; i++) {
550 DELAY(1);
551 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
552 break;
553 }
554
555 if (i == SK_TIMEOUT) {
556 printf("%s: phy write timed out\n",
557 device_xname(sc_if->sk_dev));
558 return ETIMEDOUT;
559 }
560
561 return 0;
562 }
563
564 static void
sk_marv_miibus_statchg(struct ifnet * ifp)565 sk_marv_miibus_statchg(struct ifnet *ifp)
566 {
567 DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
568 SK_YU_READ_2(((struct sk_if_softc *)ifp->if_softc),
569 YUKON_GPCR)));
570 }
571
572 static uint32_t
sk_xmac_hash(void * addr)573 sk_xmac_hash(void *addr)
574 {
575 uint32_t crc;
576
577 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
578 crc = ~crc & ((1<< SK_HASH_BITS) - 1);
579 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc));
580 return crc;
581 }
582
583 static uint32_t
sk_yukon_hash(void * addr)584 sk_yukon_hash(void *addr)
585 {
586 uint32_t crc;
587
588 crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
589 crc &= ((1 << SK_HASH_BITS) - 1);
590 DPRINTFN(2,("multicast hash for %s is %x\n", ether_sprintf(addr),crc));
591 return crc;
592 }
593
594 static void
sk_setfilt(struct sk_if_softc * sc_if,void * addrv,int slot)595 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot)
596 {
597 char *addr = addrv;
598 int base = XM_RXFILT_ENTRY(slot);
599
600 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
601 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
602 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
603 }
604
605 static void
sk_setmulti(struct sk_if_softc * sc_if)606 sk_setmulti(struct sk_if_softc *sc_if)
607 {
608 struct sk_softc *sc = sc_if->sk_softc;
609 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if;
610 uint32_t hashes[2] = { 0, 0 };
611 int h = 0, i;
612 struct ethercom *ec = &sc_if->sk_ethercom;
613 struct ether_multi *enm;
614 struct ether_multistep step;
615 uint8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
616
617 /* First, zot all the existing filters. */
618 switch (sc->sk_type) {
619 case SK_GENESIS:
620 for (i = 1; i < XM_RXFILT_MAX; i++)
621 sk_setfilt(sc_if, (void *)&dummy, i);
622
623 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
624 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
625 break;
626 case SK_YUKON:
627 case SK_YUKON_LITE:
628 case SK_YUKON_LP:
629 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
630 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
631 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
632 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
633 break;
634 }
635
636 /* Now program new ones. */
637 allmulti:
638 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
639 hashes[0] = 0xFFFFFFFF;
640 hashes[1] = 0xFFFFFFFF;
641 } else {
642 i = 1;
643 /* First find the tail of the list. */
644 ETHER_LOCK(ec);
645 ETHER_FIRST_MULTI(step, ec, enm);
646 while (enm != NULL) {
647 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
648 ETHER_ADDR_LEN)) {
649 ifp->if_flags |= IFF_ALLMULTI;
650 ETHER_UNLOCK(ec);
651 goto allmulti;
652 }
653 DPRINTFN(2,("multicast address %s\n",
654 ether_sprintf(enm->enm_addrlo)));
655 /*
656 * Program the first XM_RXFILT_MAX multicast groups
657 * into the perfect filter. For all others,
658 * use the hash table.
659 */
660 if (sc->sk_type == SK_GENESIS && i < XM_RXFILT_MAX) {
661 sk_setfilt(sc_if, enm->enm_addrlo, i);
662 i++;
663 }
664 else {
665 switch (sc->sk_type) {
666 case SK_GENESIS:
667 h = sk_xmac_hash(enm->enm_addrlo);
668 break;
669 case SK_YUKON:
670 case SK_YUKON_LITE:
671 case SK_YUKON_LP:
672 h = sk_yukon_hash(enm->enm_addrlo);
673 break;
674 }
675 if (h < 32)
676 hashes[0] |= (1 << h);
677 else
678 hashes[1] |= (1 << (h - 32));
679 }
680
681 ETHER_NEXT_MULTI(step, enm);
682 }
683 ETHER_UNLOCK(ec);
684 }
685
686 switch (sc->sk_type) {
687 case SK_GENESIS:
688 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH |
689 XM_MODE_RX_USE_PERFECT);
690 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
691 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
692 break;
693 case SK_YUKON:
694 case SK_YUKON_LITE:
695 case SK_YUKON_LP:
696 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
697 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
698 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
699 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
700 break;
701 }
702 }
703
704 static int
sk_init_rx_ring(struct sk_if_softc * sc_if)705 sk_init_rx_ring(struct sk_if_softc *sc_if)
706 {
707 struct sk_chain_data *cd = &sc_if->sk_cdata;
708 struct sk_ring_data *rd = sc_if->sk_rdata;
709 int i;
710
711 memset((char *)rd->sk_rx_ring, 0,
712 sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
713
714 for (i = 0; i < SK_RX_RING_CNT; i++) {
715 cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
716 if (i == (SK_RX_RING_CNT - 1)) {
717 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[0];
718 rd->sk_rx_ring[i].sk_next =
719 htole32(SK_RX_RING_ADDR(sc_if, 0));
720 } else {
721 cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[i + 1];
722 rd->sk_rx_ring[i].sk_next =
723 htole32(SK_RX_RING_ADDR(sc_if, i+1));
724 }
725 }
726
727 for (i = 0; i < SK_RX_RING_CNT; i++) {
728 if (sk_newbuf(sc_if, i, NULL,
729 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
730 aprint_error_dev(sc_if->sk_dev,
731 "failed alloc of %dth mbuf\n", i);
732 return ENOBUFS;
733 }
734 }
735 sc_if->sk_cdata.sk_rx_prod = 0;
736 sc_if->sk_cdata.sk_rx_cons = 0;
737
738 return 0;
739 }
740
741 static int
sk_init_tx_ring(struct sk_if_softc * sc_if)742 sk_init_tx_ring(struct sk_if_softc *sc_if)
743 {
744 struct sk_chain_data *cd = &sc_if->sk_cdata;
745 struct sk_ring_data *rd = sc_if->sk_rdata;
746 int i;
747
748 memset(sc_if->sk_rdata->sk_tx_ring, 0,
749 sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
750
751 for (i = 0; i < SK_TX_RING_CNT; i++) {
752 cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
753 if (i == (SK_TX_RING_CNT - 1)) {
754 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[0];
755 rd->sk_tx_ring[i].sk_next =
756 htole32(SK_TX_RING_ADDR(sc_if, 0));
757 } else {
758 cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[i + 1];
759 rd->sk_tx_ring[i].sk_next =
760 htole32(SK_TX_RING_ADDR(sc_if, i+1));
761 }
762 }
763
764 sc_if->sk_cdata.sk_tx_prod = 0;
765 sc_if->sk_cdata.sk_tx_cons = 0;
766 sc_if->sk_cdata.sk_tx_cnt = 0;
767
768 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT,
769 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
770
771 return 0;
772 }
773
774 static int
sk_newbuf(struct sk_if_softc * sc_if,int i,struct mbuf * m,bus_dmamap_t dmamap)775 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
776 bus_dmamap_t dmamap)
777 {
778 struct mbuf *m_new = NULL;
779 struct sk_chain *c;
780 struct sk_rx_desc *r;
781
782 if (m == NULL) {
783 void *buf = NULL;
784
785 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
786 if (m_new == NULL) {
787 aprint_error_dev(sc_if->sk_dev,
788 "no memory for rx list -- packet dropped!\n");
789 return ENOBUFS;
790 }
791
792 /* Allocate the jumbo buffer */
793 buf = sk_jalloc(sc_if);
794 if (buf == NULL) {
795 m_freem(m_new);
796 DPRINTFN(1, ("%s jumbo allocation failed -- packet "
797 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname));
798 return ENOBUFS;
799 }
800
801 /* Attach the buffer to the mbuf */
802 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
803 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if);
804
805 } else {
806 /*
807 * We're re-using a previously allocated mbuf;
808 * be sure to re-init pointers and lengths to
809 * default values.
810 */
811 m_new = m;
812 m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
813 m_new->m_data = m_new->m_ext.ext_buf;
814 }
815 m_adj(m_new, ETHER_ALIGN);
816
817 c = &sc_if->sk_cdata.sk_rx_chain[i];
818 r = c->sk_desc;
819 c->sk_mbuf = m_new;
820 r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr +
821 (((vaddr_t)m_new->m_data
822 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
823 r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT);
824
825 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
826
827 return 0;
828 }
829
830 /*
831 * Memory management for jumbo frames.
832 */
833
834 static int
sk_alloc_jumbo_mem(struct sk_if_softc * sc_if)835 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
836 {
837 struct sk_softc *sc = sc_if->sk_softc;
838 char *ptr, *kva;
839 bus_dma_segment_t seg;
840 int i, rseg, state, error;
841 struct sk_jpool_entry *entry;
842
843 state = error = 0;
844
845 /* Grab a big chunk o' storage. */
846 if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0,
847 &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
848 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n");
849 return ENOBUFS;
850 }
851
852 state = 1;
853 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, (void **)&kva,
854 BUS_DMA_NOWAIT)) {
855 aprint_error_dev(sc->sk_dev,
856 "can't map dma buffers (%d bytes)\n",
857 SK_JMEM);
858 error = ENOBUFS;
859 goto out;
860 }
861
862 state = 2;
863 if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0,
864 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
865 aprint_error_dev(sc->sk_dev, "can't create dma map\n");
866 error = ENOBUFS;
867 goto out;
868 }
869
870 state = 3;
871 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
872 kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) {
873 aprint_error_dev(sc->sk_dev, "can't load dma map\n");
874 error = ENOBUFS;
875 goto out;
876 }
877
878 state = 4;
879 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva;
880 DPRINTFN(1,("sk_jumbo_buf = %p\n", sc_if->sk_cdata.sk_jumbo_buf));
881
882 LIST_INIT(&sc_if->sk_jfree_listhead);
883 LIST_INIT(&sc_if->sk_jinuse_listhead);
884 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET);
885
886 /*
887 * Now divide it up into 9K pieces and save the addresses
888 * in an array.
889 */
890 ptr = sc_if->sk_cdata.sk_jumbo_buf;
891 for (i = 0; i < SK_JSLOTS; i++) {
892 sc_if->sk_cdata.sk_jslots[i] = ptr;
893 ptr += SK_JLEN;
894 entry = malloc(sizeof(struct sk_jpool_entry),
895 M_DEVBUF, M_WAITOK);
896 entry->slot = i;
897 if (i)
898 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
899 entry, jpool_entries);
900 else
901 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead,
902 entry, jpool_entries);
903 }
904 out:
905 if (error != 0) {
906 switch (state) {
907 case 4:
908 bus_dmamap_unload(sc->sc_dmatag,
909 sc_if->sk_cdata.sk_rx_jumbo_map);
910 /* FALLTHROUGH */
911 case 3:
912 bus_dmamap_destroy(sc->sc_dmatag,
913 sc_if->sk_cdata.sk_rx_jumbo_map);
914 /* FALLTHROUGH */
915 case 2:
916 bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM);
917 /* FALLTHROUGH */
918 case 1:
919 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
920 break;
921 default:
922 break;
923 }
924 }
925
926 return error;
927 }
928
929 /*
930 * Allocate a jumbo buffer.
931 */
932 static void *
sk_jalloc(struct sk_if_softc * sc_if)933 sk_jalloc(struct sk_if_softc *sc_if)
934 {
935 struct sk_jpool_entry *entry;
936
937 mutex_enter(&sc_if->sk_jpool_mtx);
938 entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
939
940 if (entry == NULL) {
941 mutex_exit(&sc_if->sk_jpool_mtx);
942 return NULL;
943 }
944
945 LIST_REMOVE(entry, jpool_entries);
946 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
947 mutex_exit(&sc_if->sk_jpool_mtx);
948 return sc_if->sk_cdata.sk_jslots[entry->slot];
949 }
950
951 /*
952 * Release a jumbo buffer.
953 */
954 static void
sk_jfree(struct mbuf * m,void * buf,size_t size,void * arg)955 sk_jfree(struct mbuf *m, void *buf, size_t size, void *arg)
956 {
957 struct sk_jpool_entry *entry;
958 struct sk_if_softc *sc;
959 int i;
960
961 /* Extract the softc struct pointer. */
962 sc = (struct sk_if_softc *)arg;
963
964 if (sc == NULL)
965 panic("sk_jfree: can't find softc pointer!");
966
967 /* calculate the slot this buffer belongs to */
968
969 i = ((vaddr_t)buf
970 - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
971
972 if ((i < 0) || (i >= SK_JSLOTS))
973 panic("sk_jfree: asked to free buffer that we don't manage!");
974
975 mutex_enter(&sc->sk_jpool_mtx);
976 entry = LIST_FIRST(&sc->sk_jinuse_listhead);
977 if (entry == NULL)
978 panic("sk_jfree: buffer not in use!");
979 entry->slot = i;
980 LIST_REMOVE(entry, jpool_entries);
981 LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
982 mutex_exit(&sc->sk_jpool_mtx);
983
984 if (__predict_true(m != NULL))
985 pool_cache_put(mb_cache, m);
986 }
987
988 /*
989 * Set media options.
990 */
991 static int
sk_ifmedia_upd(struct ifnet * ifp)992 sk_ifmedia_upd(struct ifnet *ifp)
993 {
994 struct sk_if_softc *sc_if = ifp->if_softc;
995 int rc;
996
997 (void) sk_init(ifp);
998 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO)
999 return 0;
1000 return rc;
1001 }
1002
1003 static void
sk_promisc(struct sk_if_softc * sc_if,int on)1004 sk_promisc(struct sk_if_softc *sc_if, int on)
1005 {
1006 struct sk_softc *sc = sc_if->sk_softc;
1007 switch (sc->sk_type) {
1008 case SK_GENESIS:
1009 if (on)
1010 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1011 else
1012 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1013 break;
1014 case SK_YUKON:
1015 case SK_YUKON_LITE:
1016 case SK_YUKON_LP:
1017 if (on)
1018 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
1019 YU_RCR_UFLEN | YU_RCR_MUFLEN);
1020 else
1021 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
1022 YU_RCR_UFLEN | YU_RCR_MUFLEN);
1023 break;
1024 default:
1025 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n",
1026 sc->sk_type);
1027 break;
1028 }
1029 }
1030
1031 static int
sk_ioctl(struct ifnet * ifp,u_long command,void * data)1032 sk_ioctl(struct ifnet *ifp, u_long command, void *data)
1033 {
1034 struct sk_if_softc *sc_if = ifp->if_softc;
1035 int s, error = 0;
1036
1037 /* DPRINTFN(2, ("sk_ioctl\n")); */
1038
1039 s = splnet();
1040
1041 switch (command) {
1042
1043 case SIOCSIFFLAGS:
1044 DPRINTFN(2, ("sk_ioctl IFFLAGS\n"));
1045 if ((error = ifioctl_common(ifp, command, data)) != 0)
1046 break;
1047 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
1048 case IFF_RUNNING:
1049 sk_stop(ifp, 1);
1050 break;
1051 case IFF_UP:
1052 sk_init(ifp);
1053 break;
1054 case IFF_UP | IFF_RUNNING:
1055 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) {
1056 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC);
1057 sk_setmulti(sc_if);
1058 } else
1059 sk_init(ifp);
1060 break;
1061 }
1062 sc_if->sk_if_flags = ifp->if_flags;
1063 error = 0;
1064 break;
1065
1066 default:
1067 DPRINTFN(2, ("sk_ioctl ETHER\n"));
1068 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
1069 break;
1070
1071 error = 0;
1072
1073 if (command != SIOCADDMULTI && command != SIOCDELMULTI)
1074 ;
1075 else if (ifp->if_flags & IFF_RUNNING) {
1076 sk_setmulti(sc_if);
1077 DPRINTFN(2, ("sk_ioctl setmulti called\n"));
1078 }
1079 break;
1080 }
1081
1082 splx(s);
1083 return error;
1084 }
1085
1086 static void
sk_update_int_mod(struct sk_softc * sc)1087 sk_update_int_mod(struct sk_softc *sc)
1088 {
1089 uint32_t imtimer_ticks;
1090
1091 /*
1092 * Configure interrupt moderation. The moderation timer
1093 * defers interrupts specified in the interrupt moderation
1094 * timer mask based on the timeout specified in the interrupt
1095 * moderation timer init register. Each bit in the timer
1096 * register represents one tick, so to specify a timeout in
1097 * microseconds, we have to multiply by the correct number of
1098 * ticks-per-microsecond.
1099 */
1100 switch (sc->sk_type) {
1101 case SK_GENESIS:
1102 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
1103 break;
1104 case SK_YUKON_EC:
1105 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
1106 break;
1107 default:
1108 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
1109 }
1110 aprint_verbose_dev(sc->sk_dev, "interrupt moderation is %d us\n",
1111 sc->sk_int_mod);
1112 sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(sc->sk_int_mod));
1113 sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF | SK_ISR_TX2_S_EOF |
1114 SK_ISR_RX1_EOF | SK_ISR_RX2_EOF);
1115 sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
1116 sc->sk_int_mod_pending = 0;
1117 }
1118
1119 /*
1120 * Lookup: Check the PCI vendor and device, and return a pointer to
1121 * The structure if the IDs match against our list.
1122 */
1123
1124 /*
1125 * Probe for a SysKonnect GEnesis chip.
1126 */
1127
1128 static int
skc_probe(device_t parent,cfdata_t match,void * aux)1129 skc_probe(device_t parent, cfdata_t match, void *aux)
1130 {
1131 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
1132 pcireg_t subid;
1133
1134 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
1135
1136 /* special-case Linksys EG1032, since rev 3 uses re(4) */
1137 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS &&
1138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 &&
1139 subid == SK_LINKSYS_EG1032_SUBID)
1140 return 1;
1141
1142 return pci_compatible_match(pa, compat_data);
1143 }
1144
1145 /*
1146 * Force the GEnesis into reset, then bring it out of reset.
1147 */
1148 static void
sk_reset(struct sk_softc * sc)1149 sk_reset(struct sk_softc *sc)
1150 {
1151 DPRINTFN(2, ("sk_reset\n"));
1152
1153 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
1154 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
1155 if (SK_YUKON_FAMILY(sc->sk_type))
1156 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
1157
1158 DELAY(1000);
1159 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
1160 DELAY(2);
1161 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
1162 if (SK_YUKON_FAMILY(sc->sk_type))
1163 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
1164
1165 DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
1166 DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
1167 CSR_READ_2(sc, SK_LINK_CTRL)));
1168
1169 if (sc->sk_type == SK_GENESIS) {
1170 /* Configure packet arbiter */
1171 sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
1172 sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
1173 sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
1174 sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
1175 sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
1176 }
1177
1178 /* Enable RAM interface */
1179 sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
1180
1181 sk_update_int_mod(sc);
1182 }
1183
1184 static int
sk_probe(device_t parent,cfdata_t match,void * aux)1185 sk_probe(device_t parent, cfdata_t match, void *aux)
1186 {
1187 struct skc_attach_args *sa = aux;
1188
1189 if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
1190 return 0;
1191
1192 return 1;
1193 }
1194
1195 /*
1196 * Each XMAC chip is attached as a separate logical IP interface.
1197 * Single port cards will have only one logical interface of course.
1198 */
1199 static void
sk_attach(device_t parent,device_t self,void * aux)1200 sk_attach(device_t parent, device_t self, void *aux)
1201 {
1202 struct sk_if_softc *sc_if = device_private(self);
1203 struct mii_data *mii = &sc_if->sk_mii;
1204 struct sk_softc *sc = device_private(parent);
1205 struct skc_attach_args *sa = aux;
1206 struct sk_txmap_entry *entry;
1207 struct ifnet *ifp;
1208 bus_dma_segment_t seg;
1209 bus_dmamap_t dmamap;
1210 prop_data_t data;
1211 void *kva;
1212 int i, rseg;
1213 int mii_flags = 0;
1214
1215 aprint_naive("\n");
1216
1217 sc_if->sk_dev = self;
1218 sc_if->sk_port = sa->skc_port;
1219 sc_if->sk_softc = sc;
1220 sc->sk_if[sa->skc_port] = sc_if;
1221
1222 if (sa->skc_port == SK_PORT_A)
1223 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1224 if (sa->skc_port == SK_PORT_B)
1225 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1226
1227 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1228
1229 /*
1230 * Get station address for this interface. Note that
1231 * dual port cards actually come with three station
1232 * addresses: one for each port, plus an extra. The
1233 * extra one is used by the SysKonnect driver software
1234 * as a 'virtual' station address for when both ports
1235 * are operating in failover mode. Currently we don't
1236 * use this extra address.
1237 */
1238 data = prop_dictionary_get(device_properties(self), "mac-address");
1239 if (data != NULL) {
1240 /*
1241 * Try to get the station address from device properties
1242 * first, in case the ROM is missing.
1243 */
1244 KASSERT(prop_object_type(data) == PROP_TYPE_DATA);
1245 KASSERT(prop_data_size(data) == ETHER_ADDR_LEN);
1246 memcpy(sc_if->sk_enaddr, prop_data_value(data),
1247 ETHER_ADDR_LEN);
1248 } else
1249 for (i = 0; i < ETHER_ADDR_LEN; i++)
1250 sc_if->sk_enaddr[i] = sk_win_read_1(sc,
1251 SK_MAC0_0 + (sa->skc_port * 8) + i);
1252
1253 aprint_normal(": Ethernet address %s\n",
1254 ether_sprintf(sc_if->sk_enaddr));
1255
1256 /*
1257 * Set up RAM buffer addresses. The NIC will have a certain
1258 * amount of SRAM on it, somewhere between 512K and 2MB. We
1259 * need to divide this up a) between the transmitter and
1260 * receiver and b) between the two XMACs, if this is a
1261 * dual port NIC. Our algorithm is to divide up the memory
1262 * evenly so that everyone gets a fair share.
1263 */
1264 if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
1265 uint32_t chunk, val;
1266
1267 chunk = sc->sk_ramsize / 2;
1268 val = sc->sk_rboff / sizeof(uint64_t);
1269 sc_if->sk_rx_ramstart = val;
1270 val += (chunk / sizeof(uint64_t));
1271 sc_if->sk_rx_ramend = val - 1;
1272 sc_if->sk_tx_ramstart = val;
1273 val += (chunk / sizeof(uint64_t));
1274 sc_if->sk_tx_ramend = val - 1;
1275 } else {
1276 uint32_t chunk, val;
1277
1278 chunk = sc->sk_ramsize / 4;
1279 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1280 sizeof(uint64_t);
1281 sc_if->sk_rx_ramstart = val;
1282 val += (chunk / sizeof(uint64_t));
1283 sc_if->sk_rx_ramend = val - 1;
1284 sc_if->sk_tx_ramstart = val;
1285 val += (chunk / sizeof(uint64_t));
1286 sc_if->sk_tx_ramend = val - 1;
1287 }
1288
1289 DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
1290 " tx_ramstart=%#x tx_ramend=%#x\n",
1291 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1292 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1293
1294 /* Read and save PHY type and set PHY address */
1295 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1296 switch (sc_if->sk_phytype) {
1297 case SK_PHYTYPE_XMAC:
1298 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1299 break;
1300 case SK_PHYTYPE_BCOM:
1301 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1302 break;
1303 case SK_PHYTYPE_MARV_COPPER:
1304 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1305 break;
1306 default:
1307 aprint_error_dev(sc->sk_dev, "unsupported PHY type: %d\n",
1308 sc_if->sk_phytype);
1309 return;
1310 }
1311
1312 /* Allocate the descriptor queues. */
1313 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data),
1314 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
1315 aprint_error_dev(sc->sk_dev, "can't alloc rx buffers\n");
1316 goto fail;
1317 }
1318 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1319 sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) {
1320 aprint_error_dev(sc_if->sk_dev,
1321 "can't map dma buffers (%lu bytes)\n",
1322 (u_long) sizeof(struct sk_ring_data));
1323 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1324 goto fail;
1325 }
1326 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1,
1327 sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT,
1328 &sc_if->sk_ring_map)) {
1329 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n");
1330 bus_dmamem_unmap(sc->sc_dmatag, kva,
1331 sizeof(struct sk_ring_data));
1332 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1333 goto fail;
1334 }
1335 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
1336 sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) {
1337 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n");
1338 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1339 bus_dmamem_unmap(sc->sc_dmatag, kva,
1340 sizeof(struct sk_ring_data));
1341 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1342 goto fail;
1343 }
1344
1345 for (i = 0; i < SK_RX_RING_CNT; i++)
1346 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
1347
1348 SIMPLEQ_INIT(&sc_if->sk_txmap_head);
1349 for (i = 0; i < SK_TX_RING_CNT; i++) {
1350 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
1351
1352 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
1353 SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap)) {
1354 aprint_error_dev(sc_if->sk_dev,
1355 "Can't create TX dmamap\n");
1356 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map);
1357 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1358 bus_dmamem_unmap(sc->sc_dmatag, kva,
1359 sizeof(struct sk_ring_data));
1360 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1361 goto fail;
1362 }
1363
1364 entry = malloc(sizeof(*entry), M_DEVBUF, M_WAITOK);
1365 entry->dmamap = dmamap;
1366 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
1367 }
1368
1369 sc_if->sk_rdata = (struct sk_ring_data *)kva;
1370 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data));
1371
1372 ifp = &sc_if->sk_ethercom.ec_if;
1373 /* Try to allocate memory for jumbo buffers. */
1374 if (sk_alloc_jumbo_mem(sc_if)) {
1375 aprint_error("%s: jumbo buffer allocation failed\n",
1376 ifp->if_xname);
1377 goto fail;
1378 }
1379 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU
1380 | ETHERCAP_JUMBO_MTU;
1381
1382 ifp->if_softc = sc_if;
1383 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1384 ifp->if_ioctl = sk_ioctl;
1385 ifp->if_start = sk_start;
1386 ifp->if_stop = sk_stop;
1387 ifp->if_init = sk_init;
1388 ifp->if_watchdog = sk_watchdog;
1389 ifp->if_capabilities = 0;
1390 IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
1391 IFQ_SET_READY(&ifp->if_snd);
1392 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ);
1393
1394 /*
1395 * Do miibus setup.
1396 */
1397 switch (sc->sk_type) {
1398 case SK_GENESIS:
1399 sk_unreset_xmac(sc_if);
1400 break;
1401 case SK_YUKON:
1402 case SK_YUKON_LITE:
1403 case SK_YUKON_LP:
1404 sk_unreset_yukon(sc_if);
1405 break;
1406 default:
1407 aprint_error_dev(sc->sk_dev, "unknown device type %d\n",
1408 sc->sk_type);
1409 goto fail;
1410 }
1411
1412 DPRINTFN(2, ("sk_attach: 1\n"));
1413
1414 mii->mii_ifp = ifp;
1415 switch (sc->sk_type) {
1416 case SK_GENESIS:
1417 mii->mii_readreg = sk_xmac_miibus_readreg;
1418 mii->mii_writereg = sk_xmac_miibus_writereg;
1419 mii->mii_statchg = sk_xmac_miibus_statchg;
1420 break;
1421 case SK_YUKON:
1422 case SK_YUKON_LITE:
1423 case SK_YUKON_LP:
1424 mii->mii_readreg = sk_marv_miibus_readreg;
1425 mii->mii_writereg = sk_marv_miibus_writereg;
1426 mii->mii_statchg = sk_marv_miibus_statchg;
1427 mii_flags = MIIF_DOPAUSE;
1428 break;
1429 }
1430
1431 sc_if->sk_ethercom.ec_mii = mii;
1432 ifmedia_init(&mii->mii_media, 0, sk_ifmedia_upd, ether_mediastatus);
1433 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY,
1434 MII_OFFSET_ANY, mii_flags);
1435 if (LIST_EMPTY(&mii->mii_phys)) {
1436 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n");
1437 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_MANUAL, 0, NULL);
1438 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_MANUAL);
1439 } else
1440 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
1441
1442 callout_init(&sc_if->sk_tick_ch, 0);
1443 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
1444
1445 DPRINTFN(2, ("sk_attach: 1\n"));
1446
1447 /*
1448 * Call MI attach routines.
1449 */
1450 if_attach(ifp);
1451 if_deferred_start_init(ifp, NULL);
1452
1453 ether_ifattach(ifp, sc_if->sk_enaddr);
1454
1455 if (sc->rnd_attached++ == 0) {
1456 rnd_attach_source(&sc->rnd_source, device_xname(sc->sk_dev),
1457 RND_TYPE_NET, RND_FLAG_DEFAULT);
1458 }
1459
1460 if (pmf_device_register(self, NULL, sk_resume))
1461 pmf_class_network_register(self, ifp);
1462 else
1463 aprint_error_dev(self, "couldn't establish power handler\n");
1464
1465 DPRINTFN(2, ("sk_attach: end\n"));
1466
1467 return;
1468
1469 fail:
1470 sc->sk_if[sa->skc_port] = NULL;
1471 }
1472
1473 static int
skcprint(void * aux,const char * pnp)1474 skcprint(void *aux, const char *pnp)
1475 {
1476 struct skc_attach_args *sa = aux;
1477
1478 if (pnp)
1479 aprint_normal("sk port %c at %s",
1480 (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
1481 else
1482 aprint_normal(" port %c",
1483 (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
1484 return UNCONF;
1485 }
1486
1487 /*
1488 * Attach the interface. Allocate softc structures, do ifmedia
1489 * setup and ethernet/BPF attach.
1490 */
1491 static void
skc_attach(device_t parent,device_t self,void * aux)1492 skc_attach(device_t parent, device_t self, void *aux)
1493 {
1494 struct sk_softc *sc = device_private(self);
1495 struct pci_attach_args *pa = aux;
1496 struct skc_attach_args skca;
1497 pci_chipset_tag_t pc = pa->pa_pc;
1498 #ifndef SK_USEIOSPACE
1499 pcireg_t memtype;
1500 #endif
1501 pci_intr_handle_t ih;
1502 const char *intrstr = NULL;
1503 bus_addr_t iobase;
1504 bus_size_t iosize;
1505 int rc, sk_nodenum;
1506 uint32_t command;
1507 const char *revstr;
1508 const struct sysctlnode *node;
1509 char intrbuf[PCI_INTRSTR_LEN];
1510
1511 sc->sk_dev = self;
1512 aprint_naive("\n");
1513
1514 DPRINTFN(2, ("begin skc_attach\n"));
1515
1516 /*
1517 * Handle power management nonsense.
1518 */
1519 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
1520
1521 if (command == 0x01) {
1522 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
1523 if (command & SK_PSTATE_MASK) {
1524 uint32_t xiobase, membase, irq;
1525
1526 /* Save important PCI config data. */
1527 xiobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
1528 membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
1529 irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
1530
1531 /* Reset the power state. */
1532 aprint_normal_dev(sc->sk_dev,
1533 "chip is in D%d power mode -- setting to D0\n",
1534 command & SK_PSTATE_MASK);
1535 command &= 0xFFFFFFFC;
1536 pci_conf_write(pc, pa->pa_tag,
1537 SK_PCI_PWRMGMTCTRL, command);
1538
1539 /* Restore PCI config data. */
1540 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, xiobase);
1541 pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
1542 pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
1543 }
1544 }
1545
1546 /*
1547 * The firmware might have configured the interface to revert the
1548 * byte order in all descriptors. Make that undone.
1549 */
1550 command = pci_conf_read(pc, pa->pa_tag, SK_PCI_OURREG2);
1551 if (command & SK_REG2_REV_DESC)
1552 pci_conf_write(pc, pa->pa_tag, SK_PCI_OURREG2,
1553 command & ~SK_REG2_REV_DESC);
1554
1555 /*
1556 * Map control/status registers.
1557 */
1558 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1559 command |= PCI_COMMAND_IO_ENABLE |
1560 PCI_COMMAND_MEM_ENABLE |
1561 PCI_COMMAND_MASTER_ENABLE;
1562 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
1563 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1564
1565 #ifdef SK_USEIOSPACE
1566 if (!(command & PCI_COMMAND_IO_ENABLE)) {
1567 aprint_error(": failed to enable I/O ports!\n");
1568 return;
1569 }
1570 /*
1571 * Map control/status registers.
1572 */
1573 if (pci_mapreg_map(pa, SK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
1574 &sc->sk_btag, &sc->sk_bhandle,
1575 &iobase, &iosize)) {
1576 aprint_error(": can't find i/o space\n");
1577 return;
1578 }
1579 #else
1580 if (!(command & PCI_COMMAND_MEM_ENABLE)) {
1581 aprint_error(": failed to enable memory mapping!\n");
1582 return;
1583 }
1584 memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
1585 switch (memtype) {
1586 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
1587 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
1588 if (pci_mapreg_map(pa, SK_PCI_LOMEM,
1589 memtype, 0, &sc->sk_btag, &sc->sk_bhandle,
1590 &iobase, &iosize) == 0)
1591 break;
1592 /* FALLTHROUGH */
1593 default:
1594 aprint_error_dev(sc->sk_dev, "can't find mem space\n");
1595 return;
1596 }
1597
1598 DPRINTFN(2, ("skc_attach: iobase=%#" PRIxPADDR ", iosize=%zx\n",
1599 iobase, iosize));
1600 #endif
1601 sc->sc_dmatag = pa->pa_dmat;
1602
1603 sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
1604 sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
1605
1606 /* bail out here if chip is not recognized */
1607 if ( sc->sk_type != SK_GENESIS && ! SK_YUKON_FAMILY(sc->sk_type)) {
1608 aprint_error_dev(sc->sk_dev, "unknown chip type\n");
1609 goto fail;
1610 }
1611 if (SK_IS_YUKON2(sc)) {
1612 aprint_error_dev(sc->sk_dev,
1613 "Does not support Yukon2--try msk(4).\n");
1614 goto fail;
1615 }
1616 DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
1617
1618 /* Allocate interrupt */
1619 if (pci_intr_map(pa, &ih)) {
1620 aprint_error(": couldn't map interrupt\n");
1621 goto fail;
1622 }
1623
1624 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
1625 sc->sk_intrhand = pci_intr_establish_xname(pc, ih, IPL_NET, sk_intr,
1626 sc, device_xname(sc->sk_dev));
1627 if (sc->sk_intrhand == NULL) {
1628 aprint_error(": couldn't establish interrupt");
1629 if (intrstr != NULL)
1630 aprint_error(" at %s", intrstr);
1631 aprint_error("\n");
1632 goto fail;
1633 }
1634 aprint_normal(": %s\n", intrstr);
1635
1636 /* Reset the adapter. */
1637 sk_reset(sc);
1638
1639 /* Read and save vital product data from EEPROM. */
1640 sk_vpd_read(sc);
1641
1642 if (sc->sk_type == SK_GENESIS) {
1643 uint8_t val = sk_win_read_1(sc, SK_EPROM0);
1644 /* Read and save RAM size and RAMbuffer offset */
1645 switch (val) {
1646 case SK_RAMSIZE_512K_64:
1647 sc->sk_ramsize = 0x80000;
1648 sc->sk_rboff = SK_RBOFF_0;
1649 break;
1650 case SK_RAMSIZE_1024K_64:
1651 sc->sk_ramsize = 0x100000;
1652 sc->sk_rboff = SK_RBOFF_80000;
1653 break;
1654 case SK_RAMSIZE_1024K_128:
1655 sc->sk_ramsize = 0x100000;
1656 sc->sk_rboff = SK_RBOFF_0;
1657 break;
1658 case SK_RAMSIZE_2048K_128:
1659 sc->sk_ramsize = 0x200000;
1660 sc->sk_rboff = SK_RBOFF_0;
1661 break;
1662 default:
1663 aprint_error_dev(sc->sk_dev, "unknown ram size: %d\n",
1664 val);
1665 goto fail_1;
1666 break;
1667 }
1668
1669 DPRINTFN(2, ("skc_attach: ramsize=%d(%dk), rboff=%d\n",
1670 sc->sk_ramsize, sc->sk_ramsize / 1024,
1671 sc->sk_rboff));
1672 } else {
1673 uint8_t val = sk_win_read_1(sc, SK_EPROM0);
1674 sc->sk_ramsize = ( val == 0 ) ? 0x20000 : (( val * 4 )*1024);
1675 sc->sk_rboff = SK_RBOFF_0;
1676
1677 DPRINTFN(2, ("skc_attach: ramsize=%dk (%d), rboff=%d\n",
1678 sc->sk_ramsize / 1024, sc->sk_ramsize,
1679 sc->sk_rboff));
1680 }
1681
1682 /* Read and save physical media type */
1683 switch (sk_win_read_1(sc, SK_PMDTYPE)) {
1684 case SK_PMD_1000BASESX:
1685 sc->sk_pmd = IFM_1000_SX;
1686 break;
1687 case SK_PMD_1000BASELX:
1688 sc->sk_pmd = IFM_1000_LX;
1689 break;
1690 case SK_PMD_1000BASECX:
1691 sc->sk_pmd = IFM_1000_CX;
1692 break;
1693 case SK_PMD_1000BASETX:
1694 case SK_PMD_1000BASETX_ALT:
1695 sc->sk_pmd = IFM_1000_T;
1696 break;
1697 default:
1698 aprint_error_dev(sc->sk_dev, "unknown media type: 0x%x\n",
1699 sk_win_read_1(sc, SK_PMDTYPE));
1700 goto fail_1;
1701 }
1702
1703 /* determine whether to name it with vpd or just make it up */
1704 /* Marvell Yukon VPD's can freqently be bogus */
1705
1706 switch (pa->pa_id) {
1707 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
1708 PCI_PRODUCT_SCHNEIDERKOCH_SKNET_GE):
1709 case PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2:
1710 case PCI_PRODUCT_3COM_3C940:
1711 case PCI_PRODUCT_DLINK_DGE530T:
1712 case PCI_PRODUCT_DLINK_DGE560T:
1713 case PCI_PRODUCT_DLINK_DGE560T_2:
1714 case PCI_PRODUCT_LINKSYS_EG1032:
1715 case PCI_PRODUCT_LINKSYS_EG1064:
1716 case PCI_ID_CODE(PCI_VENDOR_SCHNEIDERKOCH,
1717 PCI_PRODUCT_SCHNEIDERKOCH_SK9821v2):
1718 case PCI_ID_CODE(PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C940):
1719 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T):
1720 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T):
1721 case PCI_ID_CODE(PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE560T_2):
1722 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032):
1723 case PCI_ID_CODE(PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1064):
1724 sc->sk_name = sc->sk_vpd_prodname;
1725 break;
1726 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_SKNET):
1727 /* whoops yukon vpd prodname bears no resemblance to reality */
1728 switch (sc->sk_type) {
1729 case SK_GENESIS:
1730 sc->sk_name = sc->sk_vpd_prodname;
1731 break;
1732 case SK_YUKON:
1733 sc->sk_name = "Marvell Yukon Gigabit Ethernet";
1734 break;
1735 case SK_YUKON_LITE:
1736 sc->sk_name = "Marvell Yukon Lite Gigabit Ethernet";
1737 break;
1738 case SK_YUKON_LP:
1739 sc->sk_name = "Marvell Yukon LP Gigabit Ethernet";
1740 break;
1741 default:
1742 sc->sk_name = "Marvell Yukon (Unknown) Gigabit Ethernet";
1743 }
1744
1745 /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
1746
1747 if ( sc->sk_type == SK_YUKON ) {
1748 uint32_t flashaddr;
1749 uint8_t testbyte;
1750
1751 flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
1752
1753 /* test Flash-Address Register */
1754 sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
1755 testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
1756
1757 if (testbyte != 0) {
1758 /* this is yukon lite Rev. A0 */
1759 sc->sk_type = SK_YUKON_LITE;
1760 sc->sk_rev = SK_YUKON_LITE_REV_A0;
1761 /* restore Flash-Address Register */
1762 sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
1763 }
1764 }
1765 break;
1766 case PCI_ID_CODE(PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_BELKIN):
1767 sc->sk_name = sc->sk_vpd_prodname;
1768 break;
1769 default:
1770 sc->sk_name = "Unknown Marvell";
1771 }
1772
1773
1774 if ( sc->sk_type == SK_YUKON_LITE ) {
1775 switch (sc->sk_rev) {
1776 case SK_YUKON_LITE_REV_A0:
1777 revstr = "A0";
1778 break;
1779 case SK_YUKON_LITE_REV_A1:
1780 revstr = "A1";
1781 break;
1782 case SK_YUKON_LITE_REV_A3:
1783 revstr = "A3";
1784 break;
1785 default:
1786 revstr = "";
1787 }
1788 } else {
1789 revstr = "";
1790 }
1791
1792 /* Announce the product name. */
1793 aprint_normal_dev(sc->sk_dev, "%s rev. %s(0x%x)\n",
1794 sc->sk_name, revstr, sc->sk_rev);
1795
1796 skca.skc_port = SK_PORT_A;
1797 (void)config_found(sc->sk_dev, &skca, skcprint, CFARGS_NONE);
1798
1799 if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC)) {
1800 skca.skc_port = SK_PORT_B;
1801 (void)config_found(sc->sk_dev, &skca, skcprint, CFARGS_NONE);
1802 }
1803
1804 /* Turn on the 'driver is loaded' LED. */
1805 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
1806
1807 /* skc sysctl setup */
1808
1809 sc->sk_int_mod = SK_IM_DEFAULT;
1810 sc->sk_int_mod_pending = 0;
1811
1812 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1813 0, CTLTYPE_NODE, device_xname(sc->sk_dev),
1814 SYSCTL_DESCR("skc per-controller controls"),
1815 NULL, 0, NULL, 0, CTL_HW, sk_root_num, CTL_CREATE,
1816 CTL_EOL)) != 0) {
1817 aprint_normal_dev(sc->sk_dev, "couldn't create sysctl node\n");
1818 goto fail_1;
1819 }
1820
1821 sk_nodenum = node->sysctl_num;
1822
1823 /* interrupt moderation time in usecs */
1824 if ((rc = sysctl_createv(&sc->sk_clog, 0, NULL, &node,
1825 CTLFLAG_READWRITE,
1826 CTLTYPE_INT, "int_mod",
1827 SYSCTL_DESCR("sk interrupt moderation timer"),
1828 sk_sysctl_handler, 0, (void *)sc,
1829 0, CTL_HW, sk_root_num, sk_nodenum, CTL_CREATE,
1830 CTL_EOL)) != 0) {
1831 aprint_normal_dev(sc->sk_dev,
1832 "couldn't create int_mod sysctl node\n");
1833 goto fail_1;
1834 }
1835
1836 if (!pmf_device_register(self, skc_suspend, skc_resume))
1837 aprint_error_dev(self, "couldn't establish power handler\n");
1838
1839 return;
1840
1841 fail_1:
1842 pci_intr_disestablish(pc, sc->sk_intrhand);
1843 fail:
1844 bus_space_unmap(sc->sk_btag, sc->sk_bhandle, iosize);
1845 }
1846
1847 static int
sk_encap(struct sk_if_softc * sc_if,struct mbuf * m_head,uint32_t * txidx)1848 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1849 {
1850 struct sk_softc *sc = sc_if->sk_softc;
1851 struct sk_tx_desc *f = NULL;
1852 uint32_t frag, cur, cnt = 0, sk_ctl;
1853 int i;
1854 struct sk_txmap_entry *entry;
1855 bus_dmamap_t txmap;
1856
1857 DPRINTFN(3, ("sk_encap\n"));
1858
1859 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
1860 if (entry == NULL) {
1861 DPRINTFN(3, ("sk_encap: no txmap available\n"));
1862 return ENOBUFS;
1863 }
1864 txmap = entry->dmamap;
1865
1866 cur = frag = *txidx;
1867
1868 #ifdef SK_DEBUG
1869 if (skdebug >= 3)
1870 sk_dump_mbuf(m_head);
1871 #endif
1872
1873 /*
1874 * Start packing the mbufs in this chain into
1875 * the fragment pointers. Stop when we run out
1876 * of fragments or hit the end of the mbuf chain.
1877 */
1878 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1879 BUS_DMA_NOWAIT)) {
1880 DPRINTFN(1, ("sk_encap: dmamap failed\n"));
1881 return ENOBUFS;
1882 }
1883
1884 DPRINTFN(3, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
1885
1886 /* Sync the DMA map. */
1887 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1888 BUS_DMASYNC_PREWRITE);
1889
1890 for (i = 0; i < txmap->dm_nsegs; i++) {
1891 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) {
1892 DPRINTFN(1, ("sk_encap: too few descriptors free\n"));
1893 return ENOBUFS;
1894 }
1895 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1896 f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr);
1897 sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT;
1898 if (cnt == 0)
1899 sk_ctl |= SK_TXCTL_FIRSTFRAG;
1900 else
1901 sk_ctl |= SK_TXCTL_OWN;
1902 f->sk_ctl = htole32(sk_ctl);
1903 cur = frag;
1904 SK_INC(frag, SK_TX_RING_CNT);
1905 cnt++;
1906 }
1907
1908 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1909 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
1910
1911 sc_if->sk_cdata.sk_tx_map[cur] = entry;
1912 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1913 htole32(SK_TXCTL_LASTFRAG | SK_TXCTL_EOF_INTR);
1914
1915 /* Sync descriptors before handing to chip */
1916 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
1917 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1918
1919 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |=
1920 htole32(SK_TXCTL_OWN);
1921
1922 /* Sync first descriptor to hand it off */
1923 SK_CDTXSYNC(sc_if, *txidx, 1,
1924 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1925
1926 sc_if->sk_cdata.sk_tx_cnt += cnt;
1927
1928 #ifdef SK_DEBUG
1929 if (skdebug >= 3) {
1930 struct sk_tx_desc *desc;
1931 uint32_t idx;
1932 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
1933 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1934 sk_dump_txdesc(desc, idx);
1935 }
1936 }
1937 #endif
1938
1939 *txidx = frag;
1940
1941 DPRINTFN(3, ("sk_encap: completed successfully\n"));
1942
1943 return 0;
1944 }
1945
1946 static void
sk_start(struct ifnet * ifp)1947 sk_start(struct ifnet *ifp)
1948 {
1949 struct sk_if_softc *sc_if = ifp->if_softc;
1950 struct sk_softc *sc = sc_if->sk_softc;
1951 struct mbuf *m_head = NULL;
1952 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1953 int pkts = 0;
1954
1955 DPRINTFN(3, ("sk_start (idx %d, tx_chain[idx] %p)\n", idx,
1956 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf));
1957
1958 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1959 IFQ_POLL(&ifp->if_snd, m_head);
1960 if (m_head == NULL)
1961 break;
1962
1963 /*
1964 * Pack the data into the transmit ring. If we
1965 * don't have room, set the OACTIVE flag and wait
1966 * for the NIC to drain the ring.
1967 */
1968 if (sk_encap(sc_if, m_head, &idx)) {
1969 ifp->if_flags |= IFF_OACTIVE;
1970 break;
1971 }
1972
1973 /* now we are committed to transmit the packet */
1974 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1975 pkts++;
1976
1977 /*
1978 * If there's a BPF listener, bounce a copy of this frame
1979 * to him.
1980 */
1981 bpf_mtap(ifp, m_head, BPF_D_OUT);
1982 }
1983 if (pkts == 0)
1984 return;
1985
1986 /* Transmit */
1987 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1988 sc_if->sk_cdata.sk_tx_prod = idx;
1989 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1990
1991 /* Set a timeout in case the chip goes out to lunch. */
1992 ifp->if_timer = 5;
1993 }
1994 }
1995
1996
1997 static void
sk_watchdog(struct ifnet * ifp)1998 sk_watchdog(struct ifnet *ifp)
1999 {
2000 struct sk_if_softc *sc_if = ifp->if_softc;
2001
2002 /*
2003 * Reclaim first as there is a possibility of losing Tx completion
2004 * interrupts.
2005 */
2006 sk_txeof(sc_if);
2007 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
2008 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n");
2009
2010 if_statinc(ifp, if_oerrors);
2011
2012 sk_init(ifp);
2013 }
2014 }
2015
2016 #if 0 /* XXX XXX XXX UNUSED */
2017 static void
2018 sk_shutdown(void *v)
2019 {
2020 struct sk_if_softc *sc_if = (struct sk_if_softc *)v;
2021 struct sk_softc *sc = sc_if->sk_softc;
2022 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2023
2024 DPRINTFN(2, ("sk_shutdown\n"));
2025 sk_stop(ifp, 1);
2026
2027 /* Turn off the 'driver is loaded' LED. */
2028 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2029
2030 /*
2031 * Reset the GEnesis controller. Doing this should also
2032 * assert the resets on the attached XMAC(s).
2033 */
2034 sk_reset(sc);
2035 }
2036 #endif
2037
2038 static void
sk_rxeof(struct sk_if_softc * sc_if)2039 sk_rxeof(struct sk_if_softc *sc_if)
2040 {
2041 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2042 struct mbuf *m;
2043 struct sk_chain *cur_rx;
2044 struct sk_rx_desc *cur_desc;
2045 int i, cur, total_len = 0;
2046 uint32_t rxstat, sk_ctl;
2047 bus_dmamap_t dmamap;
2048
2049 i = sc_if->sk_cdata.sk_rx_prod;
2050
2051 DPRINTFN(3, ("sk_rxeof %d\n", i));
2052
2053 for (;;) {
2054 cur = i;
2055
2056 /* Sync the descriptor */
2057 SK_CDRXSYNC(sc_if, cur,
2058 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2059
2060 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl);
2061 if (sk_ctl & SK_RXCTL_OWN) {
2062 /* Invalidate the descriptor -- it's not ready yet */
2063 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD);
2064 sc_if->sk_cdata.sk_rx_prod = i;
2065 break;
2066 }
2067
2068 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
2069 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur];
2070 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
2071
2072 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
2073 dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
2074
2075 rxstat = le32toh(cur_desc->sk_xmac_rxstat);
2076 m = cur_rx->sk_mbuf;
2077 cur_rx->sk_mbuf = NULL;
2078 total_len = SK_RXBYTES(le32toh(cur_desc->sk_ctl));
2079
2080 sc_if->sk_cdata.sk_rx_map[cur] = 0;
2081
2082 SK_INC(i, SK_RX_RING_CNT);
2083
2084 if (rxstat & XM_RXSTAT_ERRFRAME) {
2085 if_statinc(ifp, if_ierrors);
2086 sk_newbuf(sc_if, cur, m, dmamap);
2087 continue;
2088 }
2089
2090 /*
2091 * Try to allocate a new jumbo buffer. If that
2092 * fails, copy the packet to mbufs and put the
2093 * jumbo buffer back in the ring so it can be
2094 * re-used. If allocating mbufs fails, then we
2095 * have to drop the packet.
2096 */
2097 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
2098 struct mbuf *m0;
2099 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
2100 total_len + ETHER_ALIGN, 0, ifp);
2101 sk_newbuf(sc_if, cur, m, dmamap);
2102 if (m0 == NULL) {
2103 aprint_error_dev(sc_if->sk_dev, "no receive "
2104 "buffers available -- packet dropped!\n");
2105 if_statinc(ifp, if_ierrors);
2106 continue;
2107 }
2108 m_adj(m0, ETHER_ALIGN);
2109 m = m0;
2110 } else {
2111 m_set_rcvif(m, ifp);
2112 m->m_pkthdr.len = m->m_len = total_len;
2113 }
2114
2115 /* pass it on. */
2116 if_percpuq_enqueue(ifp->if_percpuq, m);
2117 }
2118 }
2119
2120 static void
sk_txeof(struct sk_if_softc * sc_if)2121 sk_txeof(struct sk_if_softc *sc_if)
2122 {
2123 struct sk_softc *sc = sc_if->sk_softc;
2124 struct sk_tx_desc *cur_tx;
2125 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2126 uint32_t idx, sk_ctl;
2127 struct sk_txmap_entry *entry;
2128
2129 DPRINTFN(3, ("sk_txeof\n"));
2130
2131 /*
2132 * Go through our tx ring and free mbufs for those
2133 * frames that have been sent.
2134 */
2135 idx = sc_if->sk_cdata.sk_tx_cons;
2136 while (idx != sc_if->sk_cdata.sk_tx_prod) {
2137 SK_CDTXSYNC(sc_if, idx, 1,
2138 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2139
2140 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2141 sk_ctl = le32toh(cur_tx->sk_ctl);
2142 #ifdef SK_DEBUG
2143 if (skdebug >= 3)
2144 sk_dump_txdesc(cur_tx, idx);
2145 #endif
2146 if (sk_ctl & SK_TXCTL_OWN) {
2147 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD);
2148 break;
2149 }
2150 if (sk_ctl & SK_TXCTL_LASTFRAG)
2151 if_statinc(ifp, if_opackets);
2152 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2153 entry = sc_if->sk_cdata.sk_tx_map[idx];
2154
2155 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
2156 entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
2157
2158 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
2159 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
2160 link);
2161 sc_if->sk_cdata.sk_tx_map[idx] = NULL;
2162
2163 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2164 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2165 }
2166 sc_if->sk_cdata.sk_tx_cnt--;
2167 SK_INC(idx, SK_TX_RING_CNT);
2168 }
2169 if (sc_if->sk_cdata.sk_tx_cnt == 0)
2170 ifp->if_timer = 0;
2171 else /* nudge chip to keep tx ring moving */
2172 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2173
2174 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
2175 ifp->if_flags &= ~IFF_OACTIVE;
2176
2177 sc_if->sk_cdata.sk_tx_cons = idx;
2178 }
2179
2180 static void
sk_tick(void * xsc_if)2181 sk_tick(void *xsc_if)
2182 {
2183 struct sk_if_softc *sc_if = xsc_if;
2184 struct mii_data *mii = &sc_if->sk_mii;
2185 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2186 int i;
2187
2188 DPRINTFN(3, ("sk_tick\n"));
2189
2190 if (!(ifp->if_flags & IFF_UP))
2191 return;
2192
2193 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2194 sk_intr_bcom(sc_if);
2195 return;
2196 }
2197
2198 /*
2199 * According to SysKonnect, the correct way to verify that
2200 * the link has come back up is to poll bit 0 of the GPIO
2201 * register three times. This pin has the signal from the
2202 * link sync pin connected to it; if we read the same link
2203 * state 3 times in a row, we know the link is up.
2204 */
2205 for (i = 0; i < 3; i++) {
2206 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2207 break;
2208 }
2209
2210 if (i != 3) {
2211 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2212 return;
2213 }
2214
2215 /* Turn the GP0 interrupt back on. */
2216 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2217 SK_XM_READ_2(sc_if, XM_ISR);
2218 mii_tick(mii);
2219 if (ifp->if_link_state != LINK_STATE_UP)
2220 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2221 else
2222 callout_stop(&sc_if->sk_tick_ch);
2223 }
2224
2225 static void
sk_intr_bcom(struct sk_if_softc * sc_if)2226 sk_intr_bcom(struct sk_if_softc *sc_if)
2227 {
2228 struct mii_data *mii = &sc_if->sk_mii;
2229 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2230 uint16_t status;
2231
2232
2233 DPRINTFN(3, ("sk_intr_bcom\n"));
2234
2235 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2236
2237 /*
2238 * Read the PHY interrupt register to make sure
2239 * we clear any pending interrupts.
2240 */
2241 sk_xmac_miibus_readreg(sc_if->sk_dev,
2242 SK_PHYADDR_BCOM, BRGPHY_MII_ISR, &status);
2243
2244 if (!(ifp->if_flags & IFF_RUNNING)) {
2245 sk_init_xmac(sc_if);
2246 return;
2247 }
2248
2249 if (status & (BRGPHY_ISR_LNK_CHG | BRGPHY_ISR_AN_PR)) {
2250 uint16_t lstat;
2251 sk_xmac_miibus_readreg(sc_if->sk_dev,
2252 SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS, &lstat);
2253
2254 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2255 (void)mii_mediachg(mii);
2256 /* Turn off the link LED. */
2257 SK_IF_WRITE_1(sc_if, 0,
2258 SK_LINKLED1_CTL, SK_LINKLED_OFF);
2259 sc_if->sk_link = 0;
2260 } else if (status & BRGPHY_ISR_LNK_CHG) {
2261 sk_xmac_miibus_writereg(sc_if->sk_dev,
2262 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00);
2263 mii_tick(mii);
2264 sc_if->sk_link = 1;
2265 /* Turn on the link LED. */
2266 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2267 SK_LINKLED_ON | SK_LINKLED_LINKSYNC_OFF |
2268 SK_LINKLED_BLINK_OFF);
2269 mii_pollstat(mii);
2270 } else {
2271 mii_tick(mii);
2272 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2273 }
2274 }
2275
2276 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2277 }
2278
2279 static void
sk_intr_xmac(struct sk_if_softc * sc_if)2280 sk_intr_xmac(struct sk_if_softc *sc_if)
2281 {
2282 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR);
2283
2284 DPRINTFN(3, ("sk_intr_xmac\n"));
2285
2286 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2287 if (status & XM_ISR_GP0_SET) {
2288 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2289 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2290 }
2291
2292 if (status & XM_ISR_AUTONEG_DONE) {
2293 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2294 }
2295 }
2296
2297 if (status & XM_IMR_TX_UNDERRUN)
2298 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2299
2300 if (status & XM_IMR_RX_OVERRUN)
2301 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2302 }
2303
2304 static void
sk_intr_yukon(struct sk_if_softc * sc_if)2305 sk_intr_yukon(struct sk_if_softc *sc_if)
2306 {
2307 #ifdef SK_DEBUG
2308 int status;
2309
2310 status =
2311 #endif
2312 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2313
2314 DPRINTFN(3, ("sk_intr_yukon status=%#x\n", status));
2315 }
2316
2317 static int
sk_intr(void * xsc)2318 sk_intr(void *xsc)
2319 {
2320 struct sk_softc *sc = xsc;
2321 struct sk_if_softc *sc_if0 = sc->sk_if[SK_PORT_A];
2322 struct sk_if_softc *sc_if1 = sc->sk_if[SK_PORT_B];
2323 struct ifnet *ifp0 = NULL, *ifp1 = NULL;
2324 uint32_t status;
2325 int claimed = 0;
2326
2327 if (sc_if0 != NULL)
2328 ifp0 = &sc_if0->sk_ethercom.ec_if;
2329 if (sc_if1 != NULL)
2330 ifp1 = &sc_if1->sk_ethercom.ec_if;
2331
2332 for (;;) {
2333 status = CSR_READ_4(sc, SK_ISSR);
2334 DPRINTFN(3, ("sk_intr: status=%#x\n", status));
2335
2336 if (!(status & sc->sk_intrmask))
2337 break;
2338
2339 claimed = 1;
2340
2341 /* Handle receive interrupts first. */
2342 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
2343 sk_rxeof(sc_if0);
2344 CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
2345 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START);
2346 }
2347 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
2348 sk_rxeof(sc_if1);
2349 CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
2350 SK_RXBMU_CLR_IRQ_EOF | SK_RXBMU_RX_START);
2351 }
2352
2353 /* Then transmit interrupts. */
2354 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
2355 sk_txeof(sc_if0);
2356 CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
2357 SK_TXBMU_CLR_IRQ_EOF);
2358 }
2359 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
2360 sk_txeof(sc_if1);
2361 CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
2362 SK_TXBMU_CLR_IRQ_EOF);
2363 }
2364
2365 /* Then MAC interrupts. */
2366 if (sc_if0 && (status & SK_ISR_MAC1) &&
2367 (ifp0->if_flags & IFF_RUNNING)) {
2368 if (sc->sk_type == SK_GENESIS)
2369 sk_intr_xmac(sc_if0);
2370 else
2371 sk_intr_yukon(sc_if0);
2372 }
2373
2374 if (sc_if1 && (status & SK_ISR_MAC2) &&
2375 (ifp1->if_flags & IFF_RUNNING)) {
2376 if (sc->sk_type == SK_GENESIS)
2377 sk_intr_xmac(sc_if1);
2378 else
2379 sk_intr_yukon(sc_if1);
2380
2381 }
2382
2383 if (status & SK_ISR_EXTERNAL_REG) {
2384 if (sc_if0 != NULL &&
2385 sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
2386 sk_intr_bcom(sc_if0);
2387
2388 if (sc_if1 != NULL &&
2389 sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
2390 sk_intr_bcom(sc_if1);
2391 }
2392 }
2393
2394 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2395
2396 if (ifp0 != NULL)
2397 if_schedule_deferred_start(ifp0);
2398 if (ifp1 != NULL)
2399 if_schedule_deferred_start(ifp1);
2400
2401 KASSERT(sc->rnd_attached > 0);
2402 rnd_add_uint32(&sc->rnd_source, status);
2403
2404 if (sc->sk_int_mod_pending)
2405 sk_update_int_mod(sc);
2406
2407 return claimed;
2408 }
2409
2410 static void
sk_unreset_xmac(struct sk_if_softc * sc_if)2411 sk_unreset_xmac(struct sk_if_softc *sc_if)
2412 {
2413 struct sk_softc *sc = sc_if->sk_softc;
2414 static const struct sk_bcom_hack bhack[] = {
2415 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
2416 { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
2417 { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
2418 { 0, 0 } };
2419
2420 DPRINTFN(1, ("sk_unreset_xmac\n"));
2421
2422 /* Unreset the XMAC. */
2423 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2424 DELAY(1000);
2425
2426 /* Reset the XMAC's internal state. */
2427 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2428
2429 /* Save the XMAC II revision */
2430 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2431
2432 /*
2433 * Perform additional initialization for external PHYs,
2434 * namely for the 1000baseTX cards that use the XMAC's
2435 * GMII mode.
2436 */
2437 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2438 int i = 0;
2439 uint32_t val;
2440 uint16_t phyval;
2441
2442 /* Take PHY out of reset. */
2443 val = sk_win_read_4(sc, SK_GPIO);
2444 if (sc_if->sk_port == SK_PORT_A)
2445 val |= SK_GPIO_DIR0 | SK_GPIO_DAT0;
2446 else
2447 val |= SK_GPIO_DIR2 | SK_GPIO_DAT2;
2448 sk_win_write_4(sc, SK_GPIO, val);
2449
2450 /* Enable GMII mode on the XMAC. */
2451 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2452
2453 sk_xmac_miibus_writereg(sc_if->sk_dev,
2454 SK_PHYADDR_BCOM, MII_BMCR, BMCR_RESET);
2455 DELAY(10000);
2456 sk_xmac_miibus_writereg(sc_if->sk_dev,
2457 SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0);
2458
2459 /*
2460 * Early versions of the BCM5400 apparently have
2461 * a bug that requires them to have their reserved
2462 * registers initialized to some magic values. I don't
2463 * know what the numbers do, I'm just the messenger.
2464 */
2465 sk_xmac_miibus_readreg(sc_if->sk_dev,
2466 SK_PHYADDR_BCOM, 0x03, &phyval);
2467 if (phyval == 0x6041) {
2468 while (bhack[i].reg) {
2469 sk_xmac_miibus_writereg(sc_if->sk_dev,
2470 SK_PHYADDR_BCOM, bhack[i].reg,
2471 bhack[i].val);
2472 i++;
2473 }
2474 }
2475 }
2476 }
2477
2478 static void
sk_init_xmac(struct sk_if_softc * sc_if)2479 sk_init_xmac(struct sk_if_softc *sc_if)
2480 {
2481 struct sk_softc *sc = sc_if->sk_softc;
2482 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2483
2484 sk_unreset_xmac(sc_if);
2485
2486 /* Set station address */
2487 SK_XM_WRITE_2(sc_if, XM_PAR0,
2488 *(uint16_t *)(&sc_if->sk_enaddr[0]));
2489 SK_XM_WRITE_2(sc_if, XM_PAR1,
2490 *(uint16_t *)(&sc_if->sk_enaddr[2]));
2491 SK_XM_WRITE_2(sc_if, XM_PAR2,
2492 *(uint16_t *)(&sc_if->sk_enaddr[4]));
2493 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2494
2495 if (ifp->if_flags & IFF_PROMISC)
2496 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
2497 else
2498 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
2499
2500 if (ifp->if_flags & IFF_BROADCAST)
2501 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2502 else
2503 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2504
2505 /* We don't need the FCS appended to the packet. */
2506 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2507
2508 /* We want short frames padded to 60 bytes. */
2509 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2510
2511 /*
2512 * Enable the reception of all error frames. This is
2513 * a necessary evil due to the design of the XMAC. The
2514 * XMAC's receive FIFO is only 8K in size, however jumbo
2515 * frames can be up to 9000 bytes in length. When bad
2516 * frame filtering is enabled, the XMAC's RX FIFO operates
2517 * in 'store and forward' mode. For this to work, the
2518 * entire frame has to fit into the FIFO, but that means
2519 * that jumbo frames larger than 8192 bytes will be
2520 * truncated. Disabling all bad frame filtering causes
2521 * the RX FIFO to operate in streaming mode, in which
2522 * case the XMAC will start transferring frames out of the
2523 * RX FIFO as soon as the FIFO threshold is reached.
2524 */
2525 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES |
2526 XM_MODE_RX_GIANTS | XM_MODE_RX_RUNTS | XM_MODE_RX_CRCERRS |
2527 XM_MODE_RX_INRANGELEN);
2528
2529 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2530 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2531 else
2532 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2533
2534 /*
2535 * Bump up the transmit threshold. This helps hold off transmit
2536 * underruns when we're blasting traffic from both ports at once.
2537 */
2538 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2539
2540 /* Set multicast filter */
2541 sk_setmulti(sc_if);
2542
2543 /* Clear and enable interrupts */
2544 SK_XM_READ_2(sc_if, XM_ISR);
2545 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2546 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2547 else
2548 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2549
2550 /* Configure MAC arbiter */
2551 switch (sc_if->sk_xmac_rev) {
2552 case XM_XMAC_REV_B2:
2553 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
2554 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
2555 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
2556 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
2557 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
2558 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
2559 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
2560 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
2561 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2562 break;
2563 case XM_XMAC_REV_C1:
2564 sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
2565 sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
2566 sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
2567 sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
2568 sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
2569 sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
2570 sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
2571 sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
2572 sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
2573 break;
2574 default:
2575 break;
2576 }
2577 sk_win_write_2(sc, SK_MACARB_CTL,
2578 SK_MACARBCTL_UNRESET | SK_MACARBCTL_FASTOE_OFF);
2579
2580 sc_if->sk_link = 1;
2581 }
2582
2583 static void
sk_unreset_yukon(struct sk_if_softc * sc_if)2584 sk_unreset_yukon(struct sk_if_softc *sc_if)
2585 {
2586 uint32_t /*mac, */phy;
2587 struct sk_softc *sc;
2588
2589 DPRINTFN(1, ("sk_unreset_yukon: start: sk_csr=%#x\n",
2590 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2591
2592 sc = sc_if->sk_softc;
2593 if (sc->sk_type == SK_YUKON_LITE &&
2594 sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
2595 /* Take PHY out of reset. */
2596 sk_win_write_4(sc, SK_GPIO,
2597 (sk_win_read_4(sc, SK_GPIO) | SK_GPIO_DIR9)
2598 & ~SK_GPIO_DAT9);
2599 }
2600
2601 /* GMAC and GPHY Reset */
2602 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2603
2604 DPRINTFN(6, ("sk_init_yukon: 1\n"));
2605
2606 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2607 DELAY(1000);
2608 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2609 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2610 DELAY(1000);
2611
2612
2613 DPRINTFN(6, ("sk_init_yukon: 2\n"));
2614
2615 phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
2616 SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
2617
2618 switch (sc_if->sk_softc->sk_pmd) {
2619 case IFM_1000_SX:
2620 case IFM_1000_LX:
2621 phy |= SK_GPHY_FIBER;
2622 break;
2623
2624 case IFM_1000_CX:
2625 case IFM_1000_T:
2626 phy |= SK_GPHY_COPPER;
2627 break;
2628 }
2629
2630 DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
2631
2632 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2633 DELAY(1000);
2634 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2635 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2636 SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
2637
2638 DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
2639 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2640 }
2641
2642 static void
sk_init_yukon(struct sk_if_softc * sc_if)2643 sk_init_yukon(struct sk_if_softc *sc_if)
2644 {
2645 uint16_t reg;
2646 int i;
2647
2648 DPRINTFN(1, ("sk_init_yukon: start\n"));
2649 sk_unreset_yukon(sc_if);
2650
2651 /* unused read of the interrupt source register */
2652 DPRINTFN(6, ("sk_init_yukon: 4\n"));
2653 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2654
2655 DPRINTFN(6, ("sk_init_yukon: 4a\n"));
2656 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2657 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2658
2659 /* MIB Counter Clear Mode set */
2660 reg |= YU_PAR_MIB_CLR;
2661 DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
2662 DPRINTFN(6, ("sk_init_yukon: 4b\n"));
2663 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2664
2665 /* MIB Counter Clear Mode clear */
2666 DPRINTFN(6, ("sk_init_yukon: 5\n"));
2667 reg &= ~YU_PAR_MIB_CLR;
2668 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2669
2670 /* receive control reg */
2671 DPRINTFN(6, ("sk_init_yukon: 7\n"));
2672 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN |
2673 YU_RCR_CRCR);
2674
2675 /* transmit parameter register */
2676 DPRINTFN(6, ("sk_init_yukon: 8\n"));
2677 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2678 YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a));
2679
2680 /* serial mode register */
2681 DPRINTFN(6, ("sk_init_yukon: 9\n"));
2682 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2683 YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO |
2684 YU_SMR_IPG_DATA(0x1e));
2685
2686 DPRINTFN(6, ("sk_init_yukon: 10\n"));
2687 /* Setup Yukon's address */
2688 for (i = 0; i < 3; i++) {
2689 /* Write Source Address 1 (unicast filter) */
2690 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2691 sc_if->sk_enaddr[i * 2] |
2692 sc_if->sk_enaddr[i * 2 + 1] << 8);
2693 }
2694
2695 for (i = 0; i < 3; i++) {
2696 reg = sk_win_read_2(sc_if->sk_softc,
2697 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2698 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2699 }
2700
2701 /* Set multicast filter */
2702 DPRINTFN(6, ("sk_init_yukon: 11\n"));
2703 sk_setmulti(sc_if);
2704
2705 /* enable interrupt mask for counter overflows */
2706 DPRINTFN(6, ("sk_init_yukon: 12\n"));
2707 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2708 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2709 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2710
2711 /* Configure RX MAC FIFO */
2712 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2713 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2714
2715 /* Configure TX MAC FIFO */
2716 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2717 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2718
2719 DPRINTFN(6, ("sk_init_yukon: end\n"));
2720 }
2721
2722 /*
2723 * Note that to properly initialize any part of the GEnesis chip,
2724 * you first have to take it out of reset mode.
2725 */
2726 static int
sk_init(struct ifnet * ifp)2727 sk_init(struct ifnet *ifp)
2728 {
2729 struct sk_if_softc *sc_if = ifp->if_softc;
2730 struct sk_softc *sc = sc_if->sk_softc;
2731 struct mii_data *mii = &sc_if->sk_mii;
2732 int rc = 0, s;
2733 uint32_t imr, imtimer_ticks;
2734
2735 DPRINTFN(1, ("sk_init\n"));
2736
2737 s = splnet();
2738
2739 if (ifp->if_flags & IFF_RUNNING) {
2740 splx(s);
2741 return 0;
2742 }
2743
2744 /* Cancel pending I/O and free all RX/TX buffers. */
2745 sk_stop(ifp, 0);
2746
2747 if (sc->sk_type == SK_GENESIS) {
2748 /* Configure LINK_SYNC LED */
2749 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2750 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2751 SK_LINKLED_LINKSYNC_ON);
2752
2753 /* Configure RX LED */
2754 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2755 SK_RXLEDCTL_COUNTER_START);
2756
2757 /* Configure TX LED */
2758 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2759 SK_TXLEDCTL_COUNTER_START);
2760 }
2761
2762 /* Configure I2C registers */
2763
2764 /* Configure XMAC(s) */
2765 switch (sc->sk_type) {
2766 case SK_GENESIS:
2767 sk_init_xmac(sc_if);
2768 break;
2769 case SK_YUKON:
2770 case SK_YUKON_LITE:
2771 case SK_YUKON_LP:
2772 sk_init_yukon(sc_if);
2773 break;
2774 }
2775 if ((rc = mii_mediachg(mii)) == ENXIO)
2776 rc = 0;
2777 else if (rc != 0)
2778 goto out;
2779
2780 if (sc->sk_type == SK_GENESIS) {
2781 /* Configure MAC FIFOs */
2782 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2783 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2784 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2785
2786 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2787 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2788 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2789 }
2790
2791 /* Configure transmit arbiter(s) */
2792 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2793 SK_TXARCTL_ON | SK_TXARCTL_FSYNC_ON);
2794
2795 /* Configure RAMbuffers */
2796 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2797 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2798 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2799 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2800 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2801 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2802
2803 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2804 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2805 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2806 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2807 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2808 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2809 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2810
2811 /* Configure BMUs */
2812 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2813 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2814 SK_RX_RING_ADDR(sc_if, 0));
2815 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2816
2817 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2818 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2819 SK_TX_RING_ADDR(sc_if, 0));
2820 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2821
2822 /* Init descriptors */
2823 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2824 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2825 "memory for rx buffers\n");
2826 sk_stop(ifp, 0);
2827 splx(s);
2828 return ENOBUFS;
2829 }
2830
2831 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2832 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2833 "memory for tx buffers\n");
2834 sk_stop(ifp, 0);
2835 splx(s);
2836 return ENOBUFS;
2837 }
2838
2839 /* Set interrupt moderation if changed via sysctl. */
2840 switch (sc->sk_type) {
2841 case SK_GENESIS:
2842 imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
2843 break;
2844 case SK_YUKON_EC:
2845 imtimer_ticks = SK_IMTIMER_TICKS_YUKON_EC;
2846 break;
2847 default:
2848 imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
2849 }
2850 imr = sk_win_read_4(sc, SK_IMTIMERINIT);
2851 if (imr != SK_IM_USECS(sc->sk_int_mod)) {
2852 sk_win_write_4(sc, SK_IMTIMERINIT,
2853 SK_IM_USECS(sc->sk_int_mod));
2854 aprint_verbose_dev(sc->sk_dev,
2855 "interrupt moderation is %d us\n", sc->sk_int_mod);
2856 }
2857
2858 /* Configure interrupt handling */
2859 CSR_READ_4(sc, SK_ISSR);
2860 if (sc_if->sk_port == SK_PORT_A)
2861 sc->sk_intrmask |= SK_INTRS1;
2862 else
2863 sc->sk_intrmask |= SK_INTRS2;
2864
2865 sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
2866
2867 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2868
2869 /* Start BMUs. */
2870 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2871
2872 if (sc->sk_type == SK_GENESIS) {
2873 /* Enable XMACs TX and RX state machines */
2874 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2875 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2876 XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2877 }
2878
2879 if (SK_YUKON_FAMILY(sc->sk_type)) {
2880 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2881 reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
2882 #if 0
2883 /* XXX disable 100Mbps and full duplex mode? */
2884 reg &= ~(YU_GPCR_SPEED | YU_GPCR_DPLX_EN);
2885 #endif
2886 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2887 }
2888
2889
2890 ifp->if_flags |= IFF_RUNNING;
2891 ifp->if_flags &= ~IFF_OACTIVE;
2892 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2893
2894 out:
2895 splx(s);
2896 return rc;
2897 }
2898
2899 static void
sk_stop(struct ifnet * ifp,int disable)2900 sk_stop(struct ifnet *ifp, int disable)
2901 {
2902 struct sk_if_softc *sc_if = ifp->if_softc;
2903 struct sk_softc *sc = sc_if->sk_softc;
2904 int i;
2905
2906 DPRINTFN(1, ("sk_stop\n"));
2907
2908 callout_stop(&sc_if->sk_tick_ch);
2909
2910 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2911 uint32_t val;
2912
2913 /* Put PHY back into reset. */
2914 val = sk_win_read_4(sc, SK_GPIO);
2915 if (sc_if->sk_port == SK_PORT_A) {
2916 val |= SK_GPIO_DIR0;
2917 val &= ~SK_GPIO_DAT0;
2918 } else {
2919 val |= SK_GPIO_DIR2;
2920 val &= ~SK_GPIO_DAT2;
2921 }
2922 sk_win_write_4(sc, SK_GPIO, val);
2923 }
2924
2925 /* Turn off various components of this interface. */
2926 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2927 switch (sc->sk_type) {
2928 case SK_GENESIS:
2929 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL,
2930 SK_TXMACCTL_XMAC_RESET);
2931 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2932 break;
2933 case SK_YUKON:
2934 case SK_YUKON_LITE:
2935 case SK_YUKON_LP:
2936 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2937 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2938 break;
2939 }
2940 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2941 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF);
2942 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2943 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2944 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2945 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2946 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2947 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2948 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2949
2950 /* Disable interrupts */
2951 if (sc_if->sk_port == SK_PORT_A)
2952 sc->sk_intrmask &= ~SK_INTRS1;
2953 else
2954 sc->sk_intrmask &= ~SK_INTRS2;
2955 CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
2956
2957 SK_XM_READ_2(sc_if, XM_ISR);
2958 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2959
2960 /* Free RX and TX mbufs still in the queues. */
2961 for (i = 0; i < SK_RX_RING_CNT; i++) {
2962 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2963 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2964 }
2965
2966 for (i = 0; i < SK_TX_RING_CNT; i++) {
2967 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2968 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2969 }
2970
2971 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2972 }
2973
2974 /* Power Management Framework */
2975
2976 static bool
skc_suspend(device_t dv,const pmf_qual_t * qual)2977 skc_suspend(device_t dv, const pmf_qual_t *qual)
2978 {
2979 struct sk_softc *sc = device_private(dv);
2980
2981 DPRINTFN(2, ("skc_suspend\n"));
2982
2983 /* Turn off the driver is loaded LED */
2984 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
2985
2986 return true;
2987 }
2988
2989 static bool
skc_resume(device_t dv,const pmf_qual_t * qual)2990 skc_resume(device_t dv, const pmf_qual_t *qual)
2991 {
2992 struct sk_softc *sc = device_private(dv);
2993
2994 DPRINTFN(2, ("skc_resume\n"));
2995
2996 sk_reset(sc);
2997 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
2998
2999 return true;
3000 }
3001
3002 static bool
sk_resume(device_t dv,const pmf_qual_t * qual)3003 sk_resume(device_t dv, const pmf_qual_t *qual)
3004 {
3005 struct sk_if_softc *sc_if = device_private(dv);
3006
3007 sk_init_yukon(sc_if);
3008 return true;
3009 }
3010
3011 CFATTACH_DECL_NEW(skc, sizeof(struct sk_softc),
3012 skc_probe, skc_attach, NULL, NULL);
3013
3014 CFATTACH_DECL_NEW(sk, sizeof(struct sk_if_softc),
3015 sk_probe, sk_attach, NULL, NULL);
3016
3017 #ifdef SK_DEBUG
3018 static void
sk_dump_txdesc(struct sk_tx_desc * desc,int idx)3019 sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
3020 {
3021 #define DESC_PRINT(X) \
3022 if (X) \
3023 printf("txdesc[%d]." #X "=%#x\n", \
3024 idx, X);
3025
3026 DESC_PRINT(le32toh(desc->sk_ctl));
3027 DESC_PRINT(le32toh(desc->sk_next));
3028 DESC_PRINT(le32toh(desc->sk_data_lo));
3029 DESC_PRINT(le32toh(desc->sk_data_hi));
3030 DESC_PRINT(le32toh(desc->sk_xmac_txstat));
3031 DESC_PRINT(le16toh(desc->sk_rsvd0));
3032 DESC_PRINT(le16toh(desc->sk_csum_startval));
3033 DESC_PRINT(le16toh(desc->sk_csum_startpos));
3034 DESC_PRINT(le16toh(desc->sk_csum_writepos));
3035 DESC_PRINT(le16toh(desc->sk_rsvd1));
3036 #undef PRINT
3037 }
3038
3039 static void
sk_dump_bytes(const char * data,int len)3040 sk_dump_bytes(const char *data, int len)
3041 {
3042 int c, i, j;
3043
3044 for (i = 0; i < len; i += 16) {
3045 printf("%08x ", i);
3046 c = len - i;
3047 if (c > 16) c = 16;
3048
3049 for (j = 0; j < c; j++) {
3050 printf("%02x ", data[i + j] & 0xff);
3051 if ((j & 0xf) == 7 && j > 0)
3052 printf(" ");
3053 }
3054
3055 for (; j < 16; j++)
3056 printf(" ");
3057 printf(" ");
3058
3059 for (j = 0; j < c; j++) {
3060 int ch = data[i + j] & 0xff;
3061 printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
3062 }
3063
3064 printf("\n");
3065
3066 if (c < 16)
3067 break;
3068 }
3069 }
3070
3071 static void
sk_dump_mbuf(struct mbuf * m)3072 sk_dump_mbuf(struct mbuf *m)
3073 {
3074 int count = m->m_pkthdr.len;
3075
3076 printf("m=%p, m->m_pkthdr.len=%d\n", m, m->m_pkthdr.len);
3077
3078 while (count > 0 && m) {
3079 printf("m=%p, m->m_data=%p, m->m_len=%d\n",
3080 m, m->m_data, m->m_len);
3081 sk_dump_bytes(mtod(m, char *), m->m_len);
3082
3083 count -= m->m_len;
3084 m = m->m_next;
3085 }
3086 }
3087 #endif
3088
3089 static int
sk_sysctl_handler(SYSCTLFN_ARGS)3090 sk_sysctl_handler(SYSCTLFN_ARGS)
3091 {
3092 int error, t;
3093 struct sysctlnode node;
3094 struct sk_softc *sc;
3095
3096 node = *rnode;
3097 sc = node.sysctl_data;
3098 t = sc->sk_int_mod;
3099 node.sysctl_data = &t;
3100 error = sysctl_lookup(SYSCTLFN_CALL(&node));
3101 if (error || newp == NULL)
3102 return error;
3103
3104 if (t < SK_IM_MIN || t > SK_IM_MAX)
3105 return EINVAL;
3106
3107 /* update the softc with sysctl-changed value, and mark
3108 for hardware update */
3109 sc->sk_int_mod = t;
3110 sc->sk_int_mod_pending = 1;
3111 return 0;
3112 }
3113
3114 /*
3115 * Set up sysctl(3) MIB, hw.sk.* - Individual controllers will be
3116 * set up in skc_attach()
3117 */
3118 SYSCTL_SETUP(sysctl_sk, "sysctl sk subtree setup")
3119 {
3120 int rc;
3121 const struct sysctlnode *node;
3122
3123 if ((rc = sysctl_createv(clog, 0, NULL, &node,
3124 0, CTLTYPE_NODE, "sk",
3125 SYSCTL_DESCR("sk interface controls"),
3126 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
3127 goto err;
3128 }
3129
3130 sk_root_num = node->sysctl_num;
3131 return;
3132
3133 err:
3134 aprint_error("%s: syctl_createv failed (rc = %d)\n", __func__, rc);
3135 }
3136