1 /* $NetBSD: ahcisata_pci.c,v 1.72 2025/04/20 09:44:40 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2006 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: ahcisata_pci.c,v 1.72 2025/04/20 09:44:40 andvar Exp $");
30
31 #ifdef _KERNEL_OPT
32 #include "opt_ahcisata_pci.h"
33 #endif
34
35 #include <sys/types.h>
36 #include <sys/kmem.h>
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/disklabel.h>
41 #include <sys/pmf.h>
42
43 #include <dev/pci/pcivar.h>
44 #include <dev/pci/pcidevs.h>
45 #include <dev/pci/pciidereg.h>
46 #include <dev/pci/pciidevar.h>
47 #include <dev/ic/ahcisatavar.h>
48
49 struct ahci_pci_quirk {
50 pci_vendor_id_t vendor; /* Vendor ID */
51 pci_product_id_t product; /* Product ID */
52 int quirks; /* quirks; same as sc_ahci_quirks */
53 };
54
55 static const struct ahci_pci_quirk ahci_pci_quirks[] = {
56 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA,
57 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
58 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA2,
59 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
60 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA3,
61 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
62 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SATA4,
63 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
64 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_1,
65 AHCI_QUIRK_BADPMP },
66 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_2,
67 AHCI_QUIRK_BADPMP },
68 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_3,
69 AHCI_QUIRK_BADPMP },
70 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_AHCI_4,
71 AHCI_QUIRK_BADPMP },
72 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA,
73 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
74 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA2,
75 AHCI_QUIRK_BADPMP },
76 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA3,
77 AHCI_QUIRK_BADPMP },
78 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SATA4,
79 AHCI_QUIRK_BADPMP },
80 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_1,
81 AHCI_QUIRK_BADPMP },
82 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_2,
83 AHCI_QUIRK_BADPMP },
84 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_3,
85 AHCI_QUIRK_BADPMP },
86 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_4,
87 AHCI_QUIRK_BADPMP },
88 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_5,
89 AHCI_QUIRK_BADPMP },
90 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_6,
91 AHCI_QUIRK_BADPMP },
92 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_7,
93 AHCI_QUIRK_BADPMP },
94 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_AHCI_8,
95 AHCI_QUIRK_BADPMP },
96 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_1,
97 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
98 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_2,
99 AHCI_QUIRK_BADPMP },
100 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_3,
101 AHCI_QUIRK_BADPMP },
102 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_4,
103 AHCI_QUIRK_BADPMP },
104 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_5,
105 AHCI_QUIRK_BADPMP },
106 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_6,
107 AHCI_QUIRK_BADPMP },
108 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_7,
109 AHCI_QUIRK_BADPMP },
110 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_8,
111 AHCI_QUIRK_BADPMP },
112 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_9,
113 AHCI_QUIRK_BADPMP },
114 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_10,
115 AHCI_QUIRK_BADPMP },
116 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_11,
117 AHCI_QUIRK_BADPMP },
118 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_AHCI_12,
119 AHCI_QUIRK_BADPMP },
120 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_1,
121 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
122 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_2,
123 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
124 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_3,
125 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
126 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_4,
127 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
128 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_5,
129 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
130 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_6,
131 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
132 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_7,
133 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
134 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_8,
135 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
136 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_9,
137 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
138 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_10,
139 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
140 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_11,
141 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
142 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_AHCI_12,
143 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
144 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_1,
145 AHCI_QUIRK_BADPMP },
146 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_2,
147 AHCI_QUIRK_BADPMP },
148 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_3,
149 AHCI_QUIRK_BADPMP },
150 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_4,
151 AHCI_QUIRK_BADPMP },
152 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_5,
153 AHCI_QUIRK_BADPMP },
154 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_6,
155 AHCI_QUIRK_BADPMP },
156 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_7,
157 AHCI_QUIRK_BADPMP },
158 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_8,
159 AHCI_QUIRK_BADPMP },
160 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_9,
161 AHCI_QUIRK_BADPMP },
162 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_10,
163 AHCI_QUIRK_BADPMP },
164 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_11,
165 AHCI_QUIRK_BADPMP },
166 { PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_AHCI_12,
167 AHCI_QUIRK_BADPMP },
168 { PCI_VENDOR_ALI, PCI_PRODUCT_ALI_M5288,
169 AHCI_PCI_QUIRK_FORCE },
170 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6121,
171 AHCI_PCI_QUIRK_FORCE | AHCI_QUIRK_BADPMP },
172 { PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SE6145,
173 AHCI_QUIRK_BADPMP },
174 { PCI_VENDOR_MARVELL2, PCI_PRODUCT_MARVELL2_88SE91XX,
175 AHCI_PCI_QUIRK_FORCE },
176 /* ATI SB600 AHCI 64-bit DMA only works on some boards/BIOSes */
177 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB600_SATA_1,
178 AHCI_PCI_QUIRK_BAD64 | AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
179 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI,
180 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
181 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID,
182 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
183 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_RAID5,
184 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
185 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_AHCI2,
186 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
187 { PCI_VENDOR_ATI, PCI_PRODUCT_ATI_SB700_SATA_STORAGE,
188 AHCI_QUIRK_BADPMP | AHCI_QUIRK_BADNCQ },
189 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_SATA,
190 AHCI_QUIRK_BADPMP },
191 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT8251_AHCI,
192 AHCI_QUIRK_BADPMP },
193 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_01,
194 AHCI_PCI_QUIRK_FORCE },
195 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_02,
196 AHCI_PCI_QUIRK_FORCE },
197 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_11,
198 AHCI_PCI_QUIRK_FORCE },
199 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1061_12,
200 AHCI_PCI_QUIRK_FORCE },
201 { PCI_VENDOR_ASMEDIA, PCI_PRODUCT_ASMEDIA_ASM1062_JMB575,
202 AHCI_PCI_QUIRK_FORCE },
203 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA,
204 AHCI_PCI_QUIRK_FORCE },
205 { PCI_VENDOR_AMD, PCI_PRODUCT_AMD_HUDSON_SATA_AHCI,
206 AHCI_QUIRK_BADPMP },
207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801JI_SATA_AHCI,
208 AHCI_QUIRK_BADPMP },
209 };
210
211 struct ahci_pci_softc {
212 struct ahci_softc ah_sc;
213 pci_chipset_tag_t sc_pc;
214 pcitag_t sc_pcitag;
215 pci_intr_handle_t *sc_pihp;
216 int sc_nintr;
217 void **sc_ih;
218 };
219
220 static int ahci_pci_has_quirk(pci_vendor_id_t, pci_product_id_t);
221 static int ahci_pci_match(device_t, cfdata_t, void *);
222 static void ahci_pci_attach(device_t, device_t, void *);
223 static int ahci_pci_detach(device_t, int);
224 static void ahci_pci_childdetached(device_t, device_t);
225 static bool ahci_pci_resume(device_t, const pmf_qual_t *);
226
227
228 CFATTACH_DECL3_NEW(ahcisata_pci, sizeof(struct ahci_pci_softc),
229 ahci_pci_match, ahci_pci_attach, ahci_pci_detach, NULL,
230 NULL, ahci_pci_childdetached, DVF_DETACH_SHUTDOWN);
231
232 #define AHCI_PCI_ABAR_CAVIUM 0x10
233
234 static int
ahci_pci_has_quirk(pci_vendor_id_t vendor,pci_product_id_t product)235 ahci_pci_has_quirk(pci_vendor_id_t vendor, pci_product_id_t product)
236 {
237 int i;
238
239 for (i = 0; i < __arraycount(ahci_pci_quirks); i++)
240 if (vendor == ahci_pci_quirks[i].vendor &&
241 product == ahci_pci_quirks[i].product)
242 return ahci_pci_quirks[i].quirks;
243 return 0;
244 }
245
246 static int
ahci_pci_abar(struct pci_attach_args * pa)247 ahci_pci_abar(struct pci_attach_args *pa)
248 {
249 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CAVIUM) {
250 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_AHCI ||
251 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CAVIUM_THUNDERX_RAID) {
252 return AHCI_PCI_ABAR_CAVIUM;
253 }
254 }
255
256 return AHCI_PCI_ABAR;
257 }
258
259
260 static int
ahci_pci_match(device_t parent,cfdata_t match,void * aux)261 ahci_pci_match(device_t parent, cfdata_t match, void *aux)
262 {
263 struct pci_attach_args *pa = aux;
264 bus_space_tag_t regt;
265 bus_space_handle_t regh;
266 bus_size_t size;
267 int ret = 0;
268 bool force;
269
270 force = ((ahci_pci_has_quirk( PCI_VENDOR(pa->pa_id),
271 PCI_PRODUCT(pa->pa_id)) & AHCI_PCI_QUIRK_FORCE) != 0);
272
273 /* if wrong class and not forced by quirks, don't match */
274 if ((PCI_CLASS(pa->pa_class) != PCI_CLASS_MASS_STORAGE ||
275 ((PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_SATA ||
276 PCI_INTERFACE(pa->pa_class) != PCI_INTERFACE_SATA_AHCI) &&
277 PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_RAID)) &&
278 (force == false))
279 return 0;
280
281 int bar = ahci_pci_abar(pa);
282 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
283 if (pci_mapreg_map(pa, bar, memtype, 0, ®t, ®h, NULL, &size) != 0)
284 return 0;
285
286 if ((PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_SATA &&
287 PCI_INTERFACE(pa->pa_class) == PCI_INTERFACE_SATA_AHCI) ||
288 (bus_space_read_4(regt, regh, AHCI_GHC) & AHCI_GHC_AE) ||
289 (force == true))
290 ret = 3;
291
292 bus_space_unmap(regt, regh, size);
293 return ret;
294 }
295
296 static int
ahci_pci_intr_establish(struct ahci_softc * sc,int port)297 ahci_pci_intr_establish(struct ahci_softc *sc, int port)
298 {
299 struct ahci_pci_softc *psc = (struct ahci_pci_softc *)sc;
300 device_t self = sc->sc_atac.atac_dev;
301 char intrbuf[PCI_INTRSTR_LEN];
302 char intr_xname[INTRDEVNAMEBUF];
303 const char *intrstr;
304 int vec;
305 int (*intr_handler)(void *);
306 void *intr_arg;
307
308 KASSERT(psc->sc_pihp != NULL);
309 KASSERT(psc->sc_nintr > 0);
310
311 snprintf(intr_xname, sizeof(intr_xname), "%s", device_xname(self));
312
313 if (psc->sc_nintr == 1 || sc->sc_ghc_mrsm) {
314 /* Only one interrupt, established on vector 0 */
315 intr_handler = ahci_intr;
316 intr_arg = sc;
317 vec = 0;
318
319 if (psc->sc_ih[vec] != NULL) {
320 /* Already established, nothing more to do */
321 goto out;
322 }
323
324 } else {
325 /*
326 * Theoretically AHCI device can have less MSI/MSI-X vectors
327 * than supported ports. Hardware is allowed to revert
328 * to single message MSI, but not required to do so.
329 * So handle the case when it did not revert to single MSI.
330 * In this case last available interrupt vector is used
331 * for port == max vector, and all further ports.
332 * This last vector must use the general interrupt handler,
333 * since it needs to be able to handle several ports.
334 * NOTE: such case was never actually observed yet
335 */
336 if (sc->sc_atac.atac_nchannels > psc->sc_nintr
337 && port >= (psc->sc_nintr - 1)) {
338 intr_handler = ahci_intr;
339 intr_arg = sc;
340 vec = psc->sc_nintr - 1;
341
342 if (psc->sc_ih[vec] != NULL) {
343 /* Already established, nothing more to do */
344 goto out;
345 }
346
347 if (port == vec) {
348 /* Print error once */
349 aprint_error_dev(self,
350 "port %d independent interrupt vector not "
351 "available, sharing with further ports",
352 port);
353 }
354 } else {
355 /* Vector according to port */
356 KASSERT(port < psc->sc_nintr);
357 KASSERT(psc->sc_ih[port] == NULL);
358 intr_handler = ahci_intr_port;
359 intr_arg = &sc->sc_channels[port];
360 vec = port;
361
362 snprintf(intr_xname, sizeof(intr_xname), "%s port%d",
363 device_xname(self), port);
364 }
365 }
366
367 intrstr = pci_intr_string(psc->sc_pc, psc->sc_pihp[vec], intrbuf,
368 sizeof(intrbuf));
369 psc->sc_ih[vec] = pci_intr_establish_xname(psc->sc_pc,
370 psc->sc_pihp[vec], IPL_BIO, intr_handler, intr_arg, intr_xname);
371 if (psc->sc_ih[vec] == NULL) {
372 aprint_error_dev(self, "couldn't establish interrupt");
373 if (intrstr != NULL)
374 aprint_error(" at %s", intrstr);
375 aprint_error("\n");
376 goto fail;
377 }
378 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
379
380 out:
381 return 0;
382
383 fail:
384 return EAGAIN;
385 }
386
387 static void
ahci_pci_attach(device_t parent,device_t self,void * aux)388 ahci_pci_attach(device_t parent, device_t self, void *aux)
389 {
390 struct pci_attach_args *pa = aux;
391 struct ahci_pci_softc *psc = device_private(self);
392 struct ahci_softc *sc = &psc->ah_sc;
393 bool ahci_cap_64bit;
394 bool ahci_bad_64bit;
395 pcireg_t reg;
396
397 sc->sc_atac.atac_dev = self;
398
399 int bar = ahci_pci_abar(pa);
400 pcireg_t memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, bar);
401 if (pci_mapreg_map(pa, bar, memtype, 0, &sc->sc_ahcit, &sc->sc_ahcih,
402 NULL, &sc->sc_ahcis) != 0) {
403 aprint_error_dev(self, "can't map ahci registers\n");
404 return;
405 }
406 psc->sc_pc = pa->pa_pc;
407 psc->sc_pcitag = pa->pa_tag;
408
409 pci_aprint_devinfo(pa, "AHCI disk controller");
410
411 int counts[PCI_INTR_TYPE_SIZE] = {
412 [PCI_INTR_TYPE_INTX] = 1,
413 [PCI_INTR_TYPE_MSI] = 1,
414 [PCI_INTR_TYPE_MSIX] = -1,
415 };
416
417 /* Allocate and establish the interrupt. */
418 if (pci_intr_alloc(pa, &psc->sc_pihp, counts, PCI_INTR_TYPE_MSIX)) {
419 aprint_error_dev(self, "can't allocate handler\n");
420 goto fail;
421 }
422
423 psc->sc_nintr = counts[pci_intr_type(pa->pa_pc, psc->sc_pihp[0])];
424 psc->sc_ih = kmem_zalloc(sizeof(void *) * psc->sc_nintr, KM_SLEEP);
425 sc->sc_intr_establish = ahci_pci_intr_establish;
426
427 sc->sc_dmat = pa->pa_dmat;
428
429 sc->sc_ahci_quirks = ahci_pci_has_quirk(PCI_VENDOR(pa->pa_id),
430 PCI_PRODUCT(pa->pa_id));
431
432 ahci_cap_64bit = (AHCI_READ(sc, AHCI_CAP) & AHCI_CAP_64BIT) != 0;
433 ahci_bad_64bit = ((sc->sc_ahci_quirks & AHCI_PCI_QUIRK_BAD64) != 0);
434
435 if (pci_dma64_available(pa) && ahci_cap_64bit) {
436 if (!ahci_bad_64bit)
437 sc->sc_dmat = pa->pa_dmat64;
438 aprint_verbose_dev(self, "64-bit DMA%s\n",
439 (sc->sc_dmat == pa->pa_dmat) ? " unavailable" : "");
440 }
441
442 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) {
443 AHCIDEBUG_PRINT(("%s: RAID mode\n", AHCINAME(sc)), DEBUG_PROBE);
444 sc->sc_atac_capflags = ATAC_CAP_RAID;
445 } else {
446 AHCIDEBUG_PRINT(("%s: SATA mode\n", AHCINAME(sc)), DEBUG_PROBE);
447 }
448
449 reg = pci_conf_read(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG);
450 reg |= (PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE);
451 pci_conf_write(psc->sc_pc, psc->sc_pcitag, PCI_COMMAND_STATUS_REG, reg);
452
453 ahci_attach(sc);
454
455 if (!pmf_device_register(self, NULL, ahci_pci_resume))
456 aprint_error_dev(self, "couldn't establish power handler\n");
457
458 return;
459 fail:
460 if (psc->sc_pihp != NULL) {
461 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
462 psc->sc_pihp = NULL;
463 }
464 if (sc->sc_ahcis) {
465 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
466 sc->sc_ahcis = 0;
467 }
468
469 return;
470
471 }
472
473 static void
ahci_pci_childdetached(device_t dv,device_t child)474 ahci_pci_childdetached(device_t dv, device_t child)
475 {
476 struct ahci_pci_softc *psc = device_private(dv);
477 struct ahci_softc *sc = &psc->ah_sc;
478
479 ahci_childdetached(sc, child);
480 }
481
482 static int
ahci_pci_detach(device_t dv,int flags)483 ahci_pci_detach(device_t dv, int flags)
484 {
485 struct ahci_pci_softc *psc;
486 struct ahci_softc *sc;
487 int rv;
488
489 psc = device_private(dv);
490 sc = &psc->ah_sc;
491
492 if ((rv = ahci_detach(sc, flags)))
493 return rv;
494
495 pmf_device_deregister(dv);
496
497 if (psc->sc_ih != NULL) {
498 for (int intr = 0; intr < psc->sc_nintr; intr++) {
499 if (psc->sc_ih[intr] != NULL) {
500 pci_intr_disestablish(psc->sc_pc,
501 psc->sc_ih[intr]);
502 psc->sc_ih[intr] = NULL;
503 }
504 }
505
506 kmem_free(psc->sc_ih, sizeof(void *) * psc->sc_nintr);
507 psc->sc_ih = NULL;
508 }
509
510 if (psc->sc_pihp != NULL) {
511 pci_intr_release(psc->sc_pc, psc->sc_pihp, psc->sc_nintr);
512 psc->sc_pihp = NULL;
513 }
514
515 bus_space_unmap(sc->sc_ahcit, sc->sc_ahcih, sc->sc_ahcis);
516
517 return 0;
518 }
519
520 static bool
ahci_pci_resume(device_t dv,const pmf_qual_t * qual)521 ahci_pci_resume(device_t dv, const pmf_qual_t *qual)
522 {
523 struct ahci_pci_softc *psc = device_private(dv);
524 struct ahci_softc *sc = &psc->ah_sc;
525 int s;
526
527 s = splbio();
528 ahci_resume(sc);
529 splx(s);
530
531 return true;
532 }
533