1 /* $NetBSD: mvxpsecreg.h,v 1.1 2015/06/03 04:20:02 hsuenaga Exp $ */ 2 /* 3 * Copyright (c) 2015 Internet Initiative Japan Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 /* 28 * Cryptographic Engine and Security Accelerator(CESA) 29 */ 30 31 #ifndef __MVXPSECREG_H__ 32 #define __MVXPSECREG_H__ 33 34 /* Security Accelerator */ 35 #define MV_ACC_COMMAND 0xDE00 36 #define MV_ACC_COMMAND_ACT (0x01 << 0) 37 #define MV_ACC_COMMAND_STOP (0x01 << 2) 38 39 #define MV_ACC_DESC 0xDE04 40 #define MV_ACC_DESC_MASK 0x0000ffff 41 42 #define MV_ACC_CONFIG 0xDE08 43 #define MV_ACC_CONFIG_STOP_ON_ERR (0x01 << 0) 44 #define MV_ACC_CONFIG_WAIT_TDMA (0x01 << 7) 45 #define MV_ACC_CONFIG_ACT_TDMA (0x01 << 9) 46 #define MV_ACC_CONFIG_MULT_PKT (0x01 << 11) 47 48 #define MV_ACC_STATUS 0xDE0C 49 #define MV_ACC_STATUS_ACC_ACT (0x01 << 1) 50 #define MV_ACC_STATUS_MAC_ERR (0x01 << 8) 51 #define MV_ACC_STATUS_ACT_STATUS_MASK 0x0007ffff 52 #define MV_ACC_STATUS_ACT_STATUS_SHIFT 13 53 54 /* Security Accelerator Algorithms */ 55 /* XXX: simplify shift operation.... */ 56 #define MV_ACC_CRYPTO_OP_MASK 0x03 57 #define MV_ACC_CRYPTO_OP_SHIFT 0 58 #define MV_ACC_CRYPTO_OP_MAC (0x00 << MV_ACC_CRYPTO_OP_SHIFT) 59 #define MV_ACC_CRYPTO_OP_ENC (0x01 << MV_ACC_CRYPTO_OP_SHIFT) 60 #define MV_ACC_CRYPTO_OP_MACENC (0x02 << MV_ACC_CRYPTO_OP_SHIFT) 61 #define MV_ACC_CRYPTO_OP_ENCMAC (0x03 << MV_ACC_CRYPTO_OP_SHIFT) 62 #define MV_ACC_CRYPTO_OP(x) \ 63 (((x) & (MV_ACC_CRYPTO_OP_MASK << MV_ACC_CRYPTO_OP_SHIFT)) \ 64 >> MV_ACC_CRYPTO_OP_SHIFT) 65 66 #define MV_ACC_CRYPTO_MAC_MASK 0x07 67 #define MV_ACC_CRYPTO_MAC_SHIFT 4 68 #define MV_ACC_CRYPTO_MAC_NONE 0 69 #define MV_ACC_CRYPTO_MAC_SHA2 (0x01 << MV_ACC_CRYPTO_MAC_SHIFT) 70 #define MV_ACC_CRYPTO_MAC_HMAC_SHA2 (0x03 << MV_ACC_CRYPTO_MAC_SHIFT) 71 #define MV_ACC_CRYPTO_MAC_MD5 (0x04 << MV_ACC_CRYPTO_MAC_SHIFT) 72 #define MV_ACC_CRYPTO_MAC_SHA1 (0x05 << MV_ACC_CRYPTO_MAC_SHIFT) 73 #define MV_ACC_CRYPTO_MAC_HMAC_MD5 (0x06 << MV_ACC_CRYPTO_MAC_SHIFT) 74 #define MV_ACC_CRYPTO_MAC_HMAC_SHA1 (0x07 << MV_ACC_CRYPTO_MAC_SHIFT) 75 #define MV_ACC_CRYPTO_MAC(x) \ 76 (((x) & (MV_ACC_CRYPTO_MAC_MASK << MV_ACC_CRYPTO_MAC_SHIFT)) \ 77 >> MV_ACC_CRYPTO_MAC_SHIFT) 78 #define MV_ACC_CRYPTO_MAC_SET(dst, x) \ 79 do { \ 80 (dst) &= ~(MV_ACC_CRYPTO_MAC_MASK << MV_ACC_CRYPTO_MAC_SHIFT);\ 81 (dst) |= \ 82 ((x) & (MV_ACC_CRYPTO_MAC_MASK << MV_ACC_CRYPTO_MAC_SHIFT)); \ 83 } while(0); 84 85 #define MV_ACC_CRYPTO_ENC_MASK 0x03 86 #define MV_ACC_CRYPTO_ENC_SHIFT 8 87 #define MV_ACC_CRYPTO_ENC_NOP (0x00 << MV_ACC_CRYPTO_ENC_SHIFT) 88 #define MV_ACC_CRYPTO_ENC_DES (0x01 << MV_ACC_CRYPTO_ENC_SHIFT) 89 #define MV_ACC_CRYPTO_ENC_3DES (0x02 << MV_ACC_CRYPTO_ENC_SHIFT) 90 #define MV_ACC_CRYPTO_ENC_AES (0x03 << MV_ACC_CRYPTO_ENC_SHIFT) 91 #define MV_ACC_CRYPTO_ENC(x) \ 92 (((x) & (MV_ACC_CRYPTO_ENC_MASK << MV_ACC_CRYPTO_ENC_SHIFT)) \ 93 >> MV_ACC_CRYPTO_ENC_SHIFT) 94 #define MV_ACC_CRYPTO_ENC_SET(dst, x) \ 95 do { \ 96 (dst) &= ~(MV_ACC_CRYPTO_ENC_MASK << MV_ACC_CRYPTO_ENC_SHIFT);\ 97 (dst) |= \ 98 ((x) & (MV_ACC_CRYPTO_ENC_MASK << MV_ACC_CRYPTO_ENC_SHIFT));\ 99 } while(0); 100 101 /* this is not described in the document.... FUUUUUUUUUUUUCK! */ 102 #define MV_ACC_CRYPTO_AES_KLEN_MASK 0x03 103 #define MV_ACC_CRYPTO_AES_KLEN_SHIFT 24 104 #define MV_ACC_CRYPTO_AES_KLEN_128 \ 105 (0x00 << MV_ACC_CRYPTO_AES_KLEN_SHIFT) 106 #define MV_ACC_CRYPTO_AES_KLEN_192 \ 107 (0x01 << MV_ACC_CRYPTO_AES_KLEN_SHIFT) 108 #define MV_ACC_CRYPTO_AES_KLEN_256 \ 109 (0x02 << MV_ACC_CRYPTO_AES_KLEN_SHIFT) 110 #define MV_ACC_CRYPTO_AES_KLEN(x) \ 111 (((x) & (MV_ACC_CRYPTO_AES_KLEN_MASK << MV_ACC_CRYPTO_AES_KLEN_SHIFT)) \ 112 >> MV_ACC_CRYPTO_AES_KLEN_SHIFT) 113 #define MV_ACC_CRYPTO_AES_KLEN_SET(dst, x) \ 114 do { \ 115 (dst) &= \ 116 ~(MV_ACC_CRYPTO_AES_KLEN_MASK << MV_ACC_CRYPTO_AES_KLEN_SHIFT); \ 117 (dst) |= \ 118 ((x) & \ 119 (MV_ACC_CRYPTO_AES_KLEN_MASK << MV_ACC_CRYPTO_AES_KLEN_SHIFT)); \ 120 } while(0); 121 122 #define MV_ACC_CRYPTO_MAC_96 __BIT(7) 123 #define MV_ACC_CRYPTO_DECRYPT __BIT(12) 124 #define MV_ACC_CRYPTO_CBC __BIT(16) 125 #define MV_ACC_CRYPTO_3DES_EDE __BIT(20) 126 127 /* Security Accelerator Descriptors */ 128 /* Algorithm names are defined in mviicesa.h */ 129 #define MV_ACC_CRYPTO_FRAG_MASK 0x03 130 #define MV_ACC_CRYPTO_FRAG_SHIFT 30 131 #define MV_ACC_CRYPTO_NOFRAG (0x00 << MV_ACC_CRYPTO_FRAG_SHIFT) 132 #define MV_ACC_CRYPTO_FRAG_FIRST (0x01 << MV_ACC_CRYPTO_FRAG_SHIFT) 133 #define MV_ACC_CRYPTO_FRAG_LAST (0x02 << MV_ACC_CRYPTO_FRAG_SHIFT) 134 #define MV_ACC_CRYPTO_FRAG_MID (0x03 << MV_ACC_CRYPTO_FRAG_SHIFT) 135 #define MV_ACC_CRYPTO_FRAG(x) \ 136 (((x) & (MV_ACC_CRYPTO_FRAG_MASK << MV_ACC_CRYPTO_FRAG_SHIFT)) \ 137 >> MV_ACC_CRYPTO_FRAG_SHIFT) 138 139 #define MV_ACC_DESC_VAL_1(x) ((x) & 0x7ff) 140 #define MV_ACC_DESC_VAL_2(x) (((x) & 0x7ff) << 16) 141 #define MV_ACC_DESC_VAL_3(x) (((x) & 0xffff) << 16) 142 #define MV_ACC_DESC_GET_VAL_1(x) ((x) & 0x7ff) 143 #define MV_ACC_DESC_GET_VAL_2(x) (((x) & (0x7ff << 16)) >> 16) 144 #define MV_ACC_DESC_GET_VAL_3(x) (((x) & (0xffff << 16)) >> 16) 145 146 #define MV_ACC_DESC_ENC_DATA(src, dst) \ 147 (MV_ACC_DESC_VAL_1(src) | MV_ACC_DESC_VAL_2(dst)) 148 #define MV_ACC_DESC_ENC_LEN(len) \ 149 (MV_ACC_DESC_VAL_1(len)) 150 #define MV_ACC_DESC_ENC_KEY(key) \ 151 (MV_ACC_DESC_VAL_1(key)) 152 #define MV_ACC_DESC_ENC_IV(iv_e, iv_d) \ 153 (MV_ACC_DESC_VAL_1(iv_e) | MV_ACC_DESC_VAL_2(iv_d)) 154 155 #define MV_ACC_DESC_MAC_SRC(src, len) \ 156 (MV_ACC_DESC_VAL_1(src) | MV_ACC_DESC_VAL_3(len)) 157 #define MV_ACC_DESC_MAC_DST(dst, len) \ 158 (MV_ACC_DESC_VAL_1(dst) | MV_ACC_DESC_VAL_2(len)) 159 #define MV_ACC_DESC_MAC_IV(iv_in, iv_out) \ 160 (MV_ACC_DESC_VAL_1(iv_in) | MV_ACC_DESC_VAL_2(iv_out)) 161 162 #define MV_ACC_SRAM_SIZE 2048 163 164 /* Interrupt Cause */ 165 #define MVXPSEC_INT_CAUSE 0xDE20 166 #define MVXPSEC_INT_MASK 0xDE24 167 168 /* ENGINE interrupts */ 169 #define MVXPSEC_INT_AUTH __BIT(0) 170 #define MVXPSEC_INT_DES __BIT(1) 171 #define MVXPSEC_INT_AES_ENC __BIT(2) 172 #define MVXPSEC_INT_AES_DEC __BIT(3) 173 #define MVXPSEC_INT_ENC __BIT(4) 174 #define MVXPSEC_INT_ENGINE \ 175 (MVXPSEC_INT_AUTH | MVXPSEC_INT_ENC | \ 176 MVXPSEC_INT_DES | MVXPSEC_INT_AES_ENC | MVXPSEC_INT_AES_DEC) 177 178 /* Security Accelerator interrupts */ 179 #define MVXPSEC_INT_SA __BIT(5) 180 #define MVXPSEC_INT_ACCTDMA __BIT(7) 181 #define MVXPSEC_INT_ACCTDMA_CONT __BIT(11) 182 #define MVXPSEC_INT_COAL __BIT(14) 183 184 /* TDMA interrupts */ 185 #define MVXPSEC_INT_TDMA_COMP __BIT(9) 186 #define MVXPSEC_INT_TDMA_OWN __BIT(10) 187 188 #define MVXPSEC_INT_ACC \ 189 (MVXPSEC_INT_SA | MVXPSEC_INT_ACCTDMA | MVXPSEC_INT_ACCTDMA_CONT) 190 191 #define MVXPSEC_INT_TDMA \ 192 (MVXPSEC_INT_TDMA_COMP | MVXPSEC_INT_TDMA_OWN) 193 194 #define MVXPSEC_INT_ALL \ 195 (MVXPSEC_INT_ENGINE | MVXPSEC_INT_ACC | MVXPSEC_INT_TDMA) 196 197 /* 198 * TDMA Controllers 199 */ 200 /* TDMA Address */ 201 #define MV_TDMA_NWINDOW 4 202 #define MV_TDMA_BAR(window) (0x0A00 + (window) * 8) 203 #define MV_TDMA_BAR_BASE_MASK __BITS(31,16) 204 #define MV_TDMA_BAR_BASE(base) ((base) & MV_TDMA_BAR_BASE_MASK) 205 #define MV_TDMA_ATTR(window) (0x0A04 + (window) * 8) 206 #define MV_TDMA_ATTR_SIZE_MASK __BITS(31,16) 207 #define MV_TDMA_ATTR_ATTR_MASK __BITS(31,16) 208 #define MV_TDMA_ATTR_ENABLE __BIT(0) 209 #define MV_TDMA_ATTR_SIZE(size) ((((size - 1) >> 16) & 0xffff) << 16) 210 #define MV_TDMA_ATTR_ATTR(attr) (((attr) & 0xff) << 8) 211 #define MV_TDMA_ATTR_TARGET(target) (((target) & 0xf) << 4) 212 #define MV_TDMA_ATTR_GET_SIZE(reg) (((reg) >> 16) & 0xffff) 213 #define MV_TDMA_ATTR_GET_ATTR(reg) (((reg) >> 8) & 0xff) 214 #define MV_TDMA_ATTR_GET_TARGET(reg) (((reg) >> 4) & 0xf) 215 216 /* TDMA Control */ 217 #define MV_TDMA_CONTROL 0x0840 218 219 #define MV_TDMA_CONTROL_DST_BURST_MASK __BITS(2,0) 220 #define MV_TDMA_CONTROL_DST_BURST_32 0x3 221 #define MV_TDMA_CONTROL_DST_BURST_128 0x4 222 #define MV_TDMA_CONTROL_GET_DST_BURST(reg) \ 223 ((uint32_t)(((reg) & MV_TDMA_CONTROL_DST_BURST_MASK) >> 0)) 224 #define MV_TDMA_CONTROL_OUTS_EN __BIT(4) 225 #define MV_TDMA_CONTROL_SRC_BURST_MASK __BITS(8,6) 226 #define MV_TDMA_CONTROL_SRC_BURST_32 (0x3 << 6) 227 #define MV_TDMA_CONTROL_SRC_BURST_128 (0x4 << 6) 228 #define MV_TDMA_CONTROL_GET_SRC_BURST(reg) \ 229 ((uint32_t)(((reg) & MV_TDMA_CONTROL_SRC_BURST_MASK) >> 6)) 230 #define MV_TDMA_CONTROL_CHAIN_DIS __BIT(9) 231 #define MV_TDMA_CONTROL_BSWAP_DIS __BIT(11) 232 #define MV_TDMA_CONTROL_ENABLE __BIT(12) 233 #define MV_TDMA_CONTROL_FETCH __BIT(13) 234 #define MV_TDMA_CONTROL_ACT __BIT(14) 235 #define MV_TDMA_CONTROL_OUTS_MODE_MASK __BITS(17,16) 236 #define MV_TDMA_CONTROL_OUTS_MODE_4OUTS (3 << 16) 237 238 /* TDMA Descriptor Registers */ 239 #define MV_TDMA_CNT 0x0800 240 #define MV_TDMA_SRC 0x0810 241 #define MV_TDMA_DST 0x0820 242 #define MV_TDMA_NXT 0x0830 243 #define MV_TDMA_CUR 0x0870 244 245 #define MV_TDMA_CNT_OWN (1 << 31) 246 247 /* TDMA Interrupt */ 248 #define MV_TDMA_ERR_CAUSE 0x08C8 249 #define MV_TDMA_ERR_MASK 0x08CC 250 251 #define MV_TDMA_ERRC_MISS 0x01 252 #define MV_TDMA_ERRC_DHIT 0x02 253 #define MV_TDMA_ERRC_BHIT 0x04 254 #define MV_TDMA_ERRC_DERR 0x08 255 #define MV_TDMA_ERRC_ALL \ 256 (MV_TDMA_ERRC_MISS | MV_TDMA_ERRC_DHIT | MV_TDMA_ERRC_BHIT | \ 257 MV_TDMA_ERRC_DERR) 258 259 /* Crypto Engine Registers (just for debug) */ 260 #define MV_CE_DES_KEY0L 0xdd48 261 #define MV_CE_DES_KEY0H 0xdd4c 262 #define MV_CE_DES_KEY1L 0xdd50 263 #define MV_CE_DES_KEY1H 0xdd54 264 #define MV_CE_DES_KEY2L 0xdd60 265 #define MV_CE_DES_KEY2H 0xdd64 266 267 #define MV_CE_AES_EKEY(n) (0xdd80 + (4 * (7 - (n)))) 268 #define MV_CE_AES_DKEY(n) (0xddc0 + (4 * (7 - (n)))) 269 270 #endif /* __MVXPSECREG_H__ */ 271