1 /* $NetBSD: if_ixreg.h,v 1.3 2001/01/22 22:28:47 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1993, 1994, 1995 5 * Rodney W. Grimes, Milwaukie, Oregon 97222. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer as 12 * the first lines of this file unmodified. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Rodney W. Grimes. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY RODNEY W. GRIMES ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL RODNEY W. GRIMES BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 /* 36 * Definitions for EtherExpress 16 37 */ 38 39 #define IX_IOSIZE 16 /* card has 16 registers in IO space */ 40 41 #define IX_DATAPORT 0x00 /* shared memory data port */ 42 #define IX_WRITEPTR 0x02 /* shared memory write pointer */ 43 #define IX_READPTR 0x04 /* shared memory read pointer */ 44 45 #define IX_ATTN 0x06 /* channel attention control */ 46 #define IX_IRQ 0x07 /* IRQ configuration */ 47 #define IX_IRQ_ENABLE 0x08 /* enable board interrupts */ 48 49 #define IX_SHADOWPTR 0x08 /* shadow memory pointer */ 50 51 #define IX_MEMDEC 0x0a /* memory decode */ 52 #define IX_MCTRL 0x0b /* memory control */ 53 #define IX_MCTRL_FMCS16 0x10 /* MEMCS16- for F000 */ 54 55 #define IX_MPCTRL 0x0c /* memory page control */ 56 #define IX_CONFIG 0x0d /* config register */ 57 #define IX_BART_LOOPBACK 0x02 /* loopback, 0=none, 1=loopback */ 58 #define IX_BART_IOCHRDY_LATE 0x10 /* iochrdy late control bit */ 59 #define IX_BART_IO_TEST_EN 0x20 /* enable iochrdy timing test */ 60 #define IX_BART_IO_RESULT 0x40 /* result of the iochrdy test */ 61 #define IX_BART_MCS16_TEST 0x80 /* enable memcs16 select test */ 62 63 #define IX_ECTRL 0x0e /* eeprom control */ 64 #define IX_ECTRL_EESK 0x01 /* EEPROM clock bit */ 65 #define IX_ECTRL_EECS 0x02 /* EEPROM chip select */ 66 #define IX_ECTRL_EEDI 0x04 /* EEPROM data in bit */ 67 #define IX_ECTRL_EEDO 0x08 /* EEPROM data out bit */ 68 #define IX_RESET_ASIC 0x40 /* reset ASIC (bart) pin */ 69 #define IX_RESET_586 0x80 /* reset 82586 pin */ 70 #define IX_ECTRL_MASK 0xb2 /* and'ed with ECTRL to enable read */ 71 72 #define IX_MECTRL 0x0f /* memory control, 0xe000 seg 'W' */ 73 #define IX_ID_PORT 0x0f /* auto-id port 'R' */ 74 75 #define IX_ID 0xbaba /* known id of EE16 */ 76 77 #define IX_EEPROM_READ 0x06 /* EEPROM read opcode */ 78 #define IX_EEPROM_OPSIZE1 0x03 /* size of EEPROM opcodes */ 79 #define IX_EEPROM_ADDR_SIZE 0x06 /* size of EEPROM address */ 80 81 /* Locations in the EEPROM */ 82 #define IX_EEPROM_CONFIG1 0x00 /* Configuration register 1 */ 83 #define IX_EEPROM_MEDIA_EXT 0x1000 /* Using external transceiver */ 84 85 #define IX_EEPROM_IRQ 0xE000 /* Encoded IRQ */ 86 #define IX_EEPROM_IRQ_SHIFT 13 /* To shift IRQ to lower bits */ 87 #define IX_EEPROM_LOCK_ADDR 0x01 /* contains the lock bit */ 88 #define IX_EEPROM_LOCKED 0x01 /* means that it is locked */ 89 90 #define IX_EEPROM_ENET_LOW 0x02 /* Ethernet address, low word */ 91 #define IX_EEPROM_ENET_MID 0x03 /* Ethernet address, middle word */ 92 #define IX_EEPROM_ENET_HIGH 0x04 /* Ethernet address, high word */ 93 94 #define IX_EEPROM_MEDIA 0x05 /* Selects between TP/BNC */ 95 #define IX_EEPROM_MEDIA_TP 0x01 /* if ON, using TP, else BNC */ 96 97