1 /* $NetBSD: addcom_isa.c,v 1.23 2021/08/07 16:19:12 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2000 Michael Graff. All rights reserved.
5 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
6 * Copyright (c) 1995 Charles M. Hannum. All rights reserved.
7 *
8 * This code is derived from public-domain software written by
9 * Roland McGrath, and information provided by David Muir Sharnoff.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Charles M. Hannum.
22 * 4. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 /*
38 * This code was written and tested with the Addonics FlexPort 8S.
39 * It has 8 ports, using 16650-compatible chips, sharing a single
40 * interrupt.
41 *
42 * An interrupt status register exists at 0x240, according to the
43 * skimpy documentation supplied. It doesn't change depending on
44 * io base address, so only one of these cards can ever be used at
45 * a time.
46 *
47 * This card is different from the boca or other cards in that ports
48 * 0..5 are from addresses 0x108..0x137, and 6..7 are from 0x200..0x20f,
49 * making a gap that the other cards do not have.
50 *
51 * The addresses which are documented are 0x108, 0x1108, 0x1d08, and
52 * 0x8508, for the base (port 0) address.
53 *
54 * --Michael <explorer@NetBSD.org> -- April 21, 2000
55 */
56
57 #include <sys/cdefs.h>
58 __KERNEL_RCSID(0, "$NetBSD: addcom_isa.c,v 1.23 2021/08/07 16:19:12 thorpej Exp $");
59
60 #include <sys/param.h>
61 #include <sys/systm.h>
62 #include <sys/device.h>
63 #include <sys/termios.h>
64
65 #include <sys/bus.h>
66 #include <sys/intr.h>
67
68 #include <dev/ic/comreg.h>
69 #include <dev/ic/comvar.h>
70
71 #include <dev/isa/isavar.h>
72 #include <dev/isa/com_multi.h>
73
74 #define NSLAVES 8
75
76 /*
77 * Grr. This card always uses 0x420 for the status register, regardless
78 * of io base address.
79 */
80 #define STATUS_IOADDR 0x420
81 #define STATUS_SIZE 8 /* May be bogus... */
82
83 struct addcom_softc {
84 void *sc_ih;
85
86 bus_space_tag_t sc_iot;
87 int sc_iobase;
88
89 int sc_alive; /* mask of slave units attached */
90 void *sc_slaves[NSLAVES]; /* com device unit numbers */
91 bus_space_handle_t sc_slaveioh[NSLAVES];
92 bus_space_handle_t sc_statusioh;
93 };
94
95 #define SLAVE_IOBASE_OFFSET 0x108
96 static int slave_iobases[8] = {
97 0x108, /* port 0, base port */
98 0x110,
99 0x118,
100 0x120,
101 0x128,
102 0x130,
103 0x200, /* port 7, note address skip... */
104 0x208
105 };
106
107 int addcomprobe(device_t, cfdata_t, void *);
108 void addcomattach(device_t, device_t, void *);
109 int addcomintr(void *);
110
111 CFATTACH_DECL_NEW(addcom_isa, sizeof(struct addcom_softc),
112 addcomprobe, addcomattach, NULL, NULL);
113
114 int
addcomprobe(device_t parent,cfdata_t self,void * aux)115 addcomprobe(device_t parent, cfdata_t self, void *aux)
116 {
117 struct isa_attach_args *ia = aux;
118 bus_space_tag_t iot = ia->ia_iot;
119 bus_space_handle_t ioh;
120 int i, iobase, rv = 1;
121
122 /*
123 * Do the normal com probe for the first UART and assume
124 * its presence, and the ability to map the other UARTS,
125 * means there is a multiport board there.
126 * XXX Needs more robustness.
127 */
128
129 if (ia->ia_nio < 1)
130 return (0);
131 if (ia->ia_nirq < 1)
132 return (0);
133
134 if (ISA_DIRECT_CONFIG(ia))
135 return (0);
136
137 /* Disallow wildcarded i/o address. */
138 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT)
139 return (0);
140 if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ)
141 return (0);
142
143 iobase = ia->ia_io[0].ir_addr;
144
145 /* if the first port is in use as console, then it. */
146 if (com_is_console(iot, iobase, 0))
147 goto checkmappings;
148
149 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
150 rv = 0;
151 goto out;
152 }
153 rv = comprobe1(iot, ioh);
154 bus_space_unmap(iot, ioh, COM_NPORTS);
155 if (rv == 0)
156 goto out;
157
158 checkmappings:
159 for (i = 1; i < NSLAVES; i++) {
160 iobase += slave_iobases[i] - slave_iobases[i - 1];
161
162 if (com_is_console(iot, iobase, 0))
163 continue;
164
165 if (bus_space_map(iot, iobase, COM_NPORTS, 0, &ioh)) {
166 rv = 0;
167 goto out;
168 }
169 bus_space_unmap(iot, ioh, COM_NPORTS);
170 }
171
172 out:
173 if (rv) {
174 ia->ia_nio = 1;
175 ia->ia_io[0].ir_size = NSLAVES * COM_NPORTS;
176
177 ia->ia_nirq = 1;
178
179 ia->ia_niomem = 0;
180 ia->ia_ndrq = 0;
181 }
182 return (rv);
183 }
184
185 void
addcomattach(device_t parent,device_t self,void * aux)186 addcomattach(device_t parent, device_t self, void *aux)
187 {
188 struct addcom_softc *sc = device_private(self);
189 struct isa_attach_args *ia = aux;
190 struct commulti_attach_args ca;
191 bus_space_tag_t iot = ia->ia_iot;
192 int i, iobase;
193
194 printf("\n");
195
196 sc->sc_iot = ia->ia_iot;
197 sc->sc_iobase = ia->ia_io[0].ir_addr;
198
199 if (bus_space_map(iot, STATUS_IOADDR, STATUS_SIZE,
200 0, &sc->sc_statusioh)) {
201 aprint_error_dev(self, "can't map status space\n");
202 return;
203 }
204
205 for (i = 0; i < NSLAVES; i++) {
206 iobase = sc->sc_iobase
207 + slave_iobases[i]
208 - SLAVE_IOBASE_OFFSET;
209 if (!com_is_console(iot, iobase, &sc->sc_slaveioh[i]) &&
210 bus_space_map(iot, iobase, COM_NPORTS, 0,
211 &sc->sc_slaveioh[i])) {
212 aprint_error_dev(self,
213 "can't map i/o space for slave %d\n", i);
214 return;
215 }
216 }
217
218 for (i = 0; i < NSLAVES; i++) {
219 ca.ca_slave = i;
220 ca.ca_iot = sc->sc_iot;
221 ca.ca_ioh = sc->sc_slaveioh[i];
222 ca.ca_iobase = sc->sc_iobase
223 + slave_iobases[i]
224 - SLAVE_IOBASE_OFFSET;
225 ca.ca_noien = 0;
226
227 sc->sc_slaves[i] = config_found(self, &ca, commultiprint,
228 CFARGS_NONE);
229 if (sc->sc_slaves[i] != NULL)
230 sc->sc_alive |= 1 << i;
231 }
232
233 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq,
234 IST_EDGE, IPL_SERIAL, addcomintr, sc);
235 }
236
237 int
addcomintr(void * arg)238 addcomintr(void *arg)
239 {
240 struct addcom_softc *sc = arg;
241 bus_space_tag_t iot = sc->sc_iot;
242 int alive = sc->sc_alive;
243 int bits;
244
245 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive;
246 if (bits == 0)
247 return (0);
248
249 for (;;) {
250 #define TRY(n) \
251 if (bits & (1 << (n))) \
252 comintr(sc->sc_slaves[n]);
253 TRY(0);
254 TRY(1);
255 TRY(2);
256 TRY(3);
257 TRY(4);
258 TRY(5);
259 TRY(6);
260 TRY(7);
261 #undef TRY
262 bits = bus_space_read_1(iot, sc->sc_statusioh, 0) & alive;
263 if (bits == 0)
264 return (1);
265 }
266 }
267