1 /* $NetBSD: pca9564reg.h,v 1.1 2010/04/09 10:09:50 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 2010 NONAKA Kimihiro <nonaka@netbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _DEV_IC_PCA9564REG_H_ 29 #define _DEV_IC_PCA9564REG_H_ 30 31 #define PCA9564_I2CSTA 0x00 /* R: Status */ 32 #define PCA9564_I2CCTO 0x00 /* W: Time-out */ 33 #define PCA9564_I2CDAT 0x01 /* R/W: Data */ 34 #define PCA9564_I2CADR 0x02 /* R/W: Own address */ 35 #define PCA9564_I2CCON 0x03 /* R/W: Control */ 36 37 /* Control */ 38 #define I2CCON_CR0 (1 << 0) /* Clock Rate Bit0 */ 39 #define I2CCON_CR1 (1 << 1) /* Clock Rate Bit1 */ 40 #define I2CCON_CR2 (1 << 2) /* Clock Rate Bit2 */ 41 #define I2CCON_CR_330KHZ (0x0) 42 #define I2CCON_CR_288KHZ (0x1) 43 #define I2CCON_CR_217KHZ (0x2) 44 #define I2CCON_CR_146KHZ (0x3) 45 #define I2CCON_CR_88KHZ (0x4) 46 #define I2CCON_CR_59KHZ (0x5) 47 #define I2CCON_CR_44KHZ (0x6) 48 #define I2CCON_CR_36KHZ (0x7) 49 #define I2CCON_CR_MASK (0x7) 50 #define I2CCON_SI (1 << 3) /* Serial Interrupt Flag */ 51 #define I2CCON_STO (1 << 4) /* Stop Flag */ 52 #define I2CCON_STA (1 << 5) /* Start Flag */ 53 #define I2CCON_ENSIO (1 << 6) /* SIO Enable Bit */ 54 #define I2CCON_AA (1 << 7) /* Assert Acknowledge Flag */ 55 56 #endif /* _DEV_IC_PCA9564REG_H_ */ 57