1 /* $NetBSD: mtd803var.h,v 1.10 2015/04/13 16:33:24 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Peter Bex <Peter.Bex@student.kun.nl>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/device.h> 33 #include <sys/socket.h> 34 #include <sys/rndsource.h> 35 #include <net/if.h> 36 #include <net/if_ether.h> 37 #include <net/if_media.h> 38 #include <dev/mii/miivar.h> 39 40 41 /* Number of Tx and Rx descriptors */ 42 #define MTD_NUM_TXD 64 43 #define MTD_NUM_RXD 64 44 /* Tx and Rx buffer size */ 45 #define MTD_RXBUF_SIZE 1536 46 #define MTD_TXBUF_SIZE 1536 47 48 /* DMA mem must be longword (4 bytes) aligned */ 49 #define MTD_DMA_ALIGN 4 50 51 52 /* Descriptor structure */ 53 struct mtd_desc { 54 u_int32_t stat; /* Status field */ 55 u_int32_t conf; /* Config field */ 56 u_int32_t data; /* Data buffer start address */ 57 u_int32_t next; /* Next descriptor address */ 58 }; 59 60 /* Softc struct */ 61 struct mtd_softc { 62 device_t dev; 63 struct mii_data mii; 64 struct ethercom ethercom; 65 bus_space_tag_t bus_tag; 66 bus_space_handle_t bus_handle; 67 void * sd_hook; 68 u_int8_t eaddr[ETHER_ADDR_LEN]; 69 volatile unsigned int cur_tx; 70 volatile unsigned int cur_rx; 71 72 bus_dma_tag_t dma_tag; 73 struct mtd_desc * desc; 74 bus_dmamap_t desc_dma_map; 75 void * buf; 76 bus_dmamap_t buf_dma_map; 77 78 krndsource_t rnd_src; 79 }; 80 81 82 /* Transmit descriptor layout */ 83 /* Status register */ 84 #define MTD_TXD_OWNER 0x80000000 /* Owner bit */ 85 #define MTD_TXD_RSRVD0 0x7fffc000 /* Bits [30:14] are reserved */ 86 #define MTD_TXD_ABORT 0x00002000 /* Transmit aborted */ 87 #define MTD_TXD_CSL 0x00001000 /* Carrier Sense Loss */ 88 #define MTD_TXD_LCOL 0x00000800 /* Late collision */ 89 #define MTD_TXD_EXCOL 0x00000400 /* Excessive collisions */ 90 #define MTD_TXD_DFD 0x00000200 /* Deferred */ 91 #define MTD_TXD_HBFAIL 0x00000100 /* Heart-beat failure */ 92 #define MTD_TXD_NRC 0x000000ff /* Collision Retry Count */ 93 /* Configuration register */ 94 #define MTD_TXD_CONF_IRQC 0x80000000 /* Interrupt control */ 95 #define MTD_TXD_CONF_EIRQC 0x40000000 /* Early interrupt control */ 96 #define MTD_TXD_CONF_LSD 0x20000000 /* Last descriptor */ 97 #define MTD_TXD_CONF_FSD 0x10000000 /* First descriptor */ 98 #define MTD_TXD_CONF_CRC 0x08000000 /* CRC append */ 99 #define MTD_TXD_CONF_PAD 0x04000000 /* Pad control */ 100 #define MTD_TXD_CONF_RLCOL 0x02000000 /* Retry Late Collision */ 101 #define MTD_TXD_CONF_RSRVD0 0x01c00000 /* Bits [24:22] are reserved */ 102 #define MTD_TXD_CONF_PKTS 0x003ff800 /* Packet size */ 103 #define MTD_TXD_CONF_BUFS 0x000007ff /* Transmit buffer size */ 104 105 #define MTD_TXD_PKTS_SHIFT 11 106 107 /* Receive descriptor layout */ 108 /* Status register */ 109 #define MTD_RXD_OWNER 0x80000000 /* Owner bit */ 110 #define MTD_RXD_RSRVD3 0x70000000 /* Bits [30:28] are reserved */ 111 #define MTD_RXD_FLEN 0x0fff0000 /* Frame length */ 112 #define MTD_RXD_RSRVD2 0x00008000 /* Bit 15 is reserved */ 113 #define MTD_RXD_MAR 0x00004000 /* Multicast Address Received */ 114 #define MTD_RXD_BAR 0x00002000 /* Broadcast Address Received */ 115 #define MTD_RXD_PAR 0x00001000 /* Physical Address Received */ 116 #define MTD_RXD_FSD 0x00000800 /* First Descriptor */ 117 #define MTD_RXD_LSD 0x00000400 /* Last Descriptor */ 118 #define MTD_RXD_RSRVD1 0x00000300 /* Bits [9:8] are reserved */ 119 #define MTD_RXD_ERRSUM 0x00000080 /* Error summary */ 120 #define MTD_RXD_RUNT 0x00000040 /* Runt packet received */ 121 #define MTD_RXD_LONG 0x00000020 /* Long packet received */ 122 #define MTD_RXD_FALERR 0x00000010 /* Frame alignment error */ 123 #define MTD_RXD_CRC 0x00000008 /* CRC error. See manual :) */ 124 #define MTD_RXD_RXERR 0x00000004 /* Receive error */ 125 #define MTD_RXD_RSRVD0 0x00000003 /* Bits [1:0] are reserved */ 126 /* Configuration register */ 127 #define MTD_RXD_CONF_RSRVD0 0xfffff800 /* Bits [31:11] are reserved */ 128 #define MTD_RXD_CONF_BUFS 0x000007ff /* Receive buffer size */ 129 130 #define MTD_RXD_FLEN_SHIFT 16 131 132 extern int mtd_config(struct mtd_softc *); 133 extern int mtd_irq_h(void *); 134