1 /* $NetBSD: mpc105reg.h,v 1.3 2008/04/28 20:23:50 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Klaus J. Klein. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_IC_MPC105REG_H_ 33 #define _DEV_IC_MPC105REG_H_ 34 35 /* 36 * Register definitions for the Motorola MPC105 PCI Bridge/Memory 37 * Controller (PCIB/MC), as found in: 38 * 39 * MPC105 PCI Bridge/Memory Controller User's Manual, 40 * Motorola Publication Number MPC105UM/AD. 41 */ 42 43 #define MPC105_PMCR 0x70 /* Power Management configuration */ 44 #define MPC105_MEMSTARTADDR1 0x80 /* Memory starting address 1 */ 45 #define MPC105_MEMSTARTADDR2 0x84 /* Memory starting address 2 */ 46 #define MPC105_EXTMEMSTARTADDR1 0x88 /* Extd. memory starting address 1 */ 47 #define MPC105_EXTMEMSTARTADDR2 0x8c /* Extd. memory starting address 2 */ 48 #define MPC105_MEMENDADDR1 0x90 /* Memory ending address 1 */ 49 #define MPC105_MEMENDADDR2 0x94 /* Memory ending address 2 */ 50 #define MPC105_EXTMEMENDADDR1 0x98 /* Extd. memory ending address 1 */ 51 #define MPC105_EXTMEMENDADDR2 0x9c /* Extd. memory ending address 2 */ 52 #define MPC105_MEMEN 0xa0 /* Memory enable */ 53 #define MPC105_PICR1 0xa8 /* Processor Interface Config 1 */ 54 #define MPC105_PICR1_CBA_MASK 0xff000000 /* Copy-back addr mask */ 55 #define MPC105_PICR1_BREAD_WS 0x00c00000 /* Burst read wait states: */ 56 #define MPC105_PICR1_BREAD_WS0 0x00000000 /* 0 wait states */ 57 #define MPC105_PICR1_BREAD_WS1 0x00400000 /* 1 wait state */ 58 #define MPC105_PICR1_BREAD_WS2 0x00800000 /* 2 wait states */ 59 #define MPC105_PICR1_BREAD_WS3 0x00c00000 /* 3 wait states */ 60 #define MPC105_PICR1_CACHE_1G 0x00200000 /* Cache 0-1G only */ 61 #define MPC105_PICR1_RCS0 0x00100000 /* ROM on 0:PCI, 1:60x bus */ 62 #define MPC105_PICR1_XIO_MODE 0x00080000 /* 0:Contig, 1:Discontig mode */ 63 #define MPC105_PICR1_PROC_TYPE 0x00060000 /* Processor type */ 64 #define MPC105_PICR1_PROC_TYPE_601 0x00000000 65 # 66 #define MPC105_PICR1_PROC_TYPE_RSVD 0x00020000 67 #define MPC105_PICR1_PROC_TYPE_603 0x00040000 68 #define MPC105_PICR1_PROC_TYPE_604 0x00060000 69 #define MPC105_PICR1_XATS 0x00010000 /* Address map 0:B, 1:A */ 70 #define MPC105_PICR1_MP_ID 0x00008000 /* Multiprocessor identifier */ 71 #define MPC105_PICR1_RSVD0 0x00004000 72 #define MPC105_PICR1_LBA_EN 0x00002000 /* Local bus slave enable */ 73 #define MPC105_PICR1_FLASHWR_EN 0x00001000 /* Flash writes enable */ 74 #define MPC105_PICR1_MCP_EN 0x00000800 /* Machine check enable */ 75 #define MPC105_PICR1_TEA_EN 0x00000400 /* Transfer error enable */ 76 #define MPC105_PICR1_DPARK 0x00000200 /* Data bus park */ 77 #define MPC105_PICR1_RSVD1 0x00000100 78 #define MPC105_PICR1_NO_PORT_REGS 0x00000080 /* Implement ext. conf regs */ 79 #define MPC105_PICR1_ST_GATH_EN 0x00000040 /* Store gathering enable */ 80 #define MPC105_PICR1_LE_MODE 0x00000020 /* 0:Big, 1:Little endian */ 81 #define MPC105_PICR1_LOOP_SNOOP 0x00000010 /* Snoop looping enable */ 82 #define MPC105_PICR1_APARK 0x00000008 /* Address bus park */ 83 #define MPC105_PICR1_SPECREADS 0x00000004 /* Speculative read enable */ 84 #define MPC105_PICR1_L2_MP 0x00000003 /* L2/multiproc config: */ 85 #define MPC105_PICR1_L2_MP_NONE 0x00000000 /* Uniprocessor/none */ 86 #define MPC105_PICR1_L2_MP_WT 0x00000001 /* Write-through */ 87 #define MPC105_PICR1_L2_MP_WB 0x00000002 /* Write-back */ 88 #define MPC105_PICR1_L2_MP_MP 0x00000003 /* Multiprocessor */ 89 #define MPC105_PICR2 0xac /* Processor Interface Config 2 */ 90 #define MPC105_PICR2_L2_UPD_EN 0x80000000 /* Service L2 cache misses */ 91 #define MPC105_PICR2_L2_EN 0x40000000 /* L2 cache enable */ 92 #define MPC105_PICR2_RSVD0 0x20000000 93 #define MPC105_PICR2_FLUSH_L2 0x10000000 /* 0->1: flush L2 cache */ 94 #define MPC105_PICR2_RSVD1 0x0c000000 95 #define MPC105_PICR2_BYTE_DEC 0x02000000 /* Do L2 byte-write decode */ 96 #define MPC105_PICR2_FAST_L2_MODE 0x01000000 /* Fast L2 mode timing */ 97 #define MPC105_PICR2_DATA_RAM_TYPE 0x00c00000 /* L2 data RAM type */ 98 #define MPC105_PICR2_DATA_RAM_TYPE_SYNCBRST 0x00000000 99 #define MPC105_PICR2_DATA_RAM_TYPE_RSVD0 0x00400000 100 #define MPC105_PICR2_DATA_RAM_TYPE_ASYNC 0x00800000 101 #define MPC105_PICR2_DATA_RAM_TYPE_RSVD1 0x00c00000 102 #define MPC105_PICR2_WMODE 0x00300000 /* SRAM write timing */ 103 #define MPC105_PICR2_WMODE_RSVD 0x00000000 104 #define MPC105_PICR2_WMODE_NORMAL 0x00100000 105 #define MPC105_PICR2_WMODE_DELAYED 0x00200000 106 #define MPC105_PICR2_WMODE_EARLY 0x00300000 107 #define MPC105_PICR2_SNOOP_WS 0x000c0000 /* Snoop wait states: */ 108 #define MPC105_PICR2_SNOOP_WS0 0x00000000 /* 0 clock cycles */ 109 #define MPC105_PICR2_SNOOP_WS1 0x00040000 /* 1 clock cycle */ 110 #define MPC105_PICR2_SNOOP_WS2 0x00080000 /* 2 clock cycles */ 111 #define MPC105_PICR2_SNOOP_WS3 0x000c0000 /* 3 clock cycles */ 112 #define MPC105_PICR2_MOD_HIGH 0x00020000 /* Cache modified polarity */ 113 #define MPC105_PICR2_HIT_HIGH 0x00010000 /* Cache hit polarity */ 114 #define MPC105_PICR2_RSVD2 0x00008000 115 #define MPC105_PICR2_ADDR_ONLY_DISABLE 0x00004000 /* L2 ignores CLEAN/ 116 FLUSH/KILL ops */ 117 #define MPC105_PICR2_HOLD 0x00002000 /* L2 tag address hold */ 118 #define MPC105_PICR2_INV_MODE 0x00001000 /* L2 invalidate mode enable */ 119 #define MPC105_PICR2_RSVD3 0x00000800 120 #define MPC105_PICR2_L2_HIT_DELAY 0x0000600 /* L2 hit delay */ 121 #define MPC105_PICR2_L2_HIT_DELAYRSVD 0x0000000 /* reserved */ 122 #define MPC105_PICR2_L2_HIT_DELAY1 0x0000200 /* 1 clock cycle */ 123 #define MPC105_PICR2_L2_HIT_DELAY2 0x0000400 /* 2 clock cycles */ 124 #define MPC105_PICR2_L2_HIT_DELAY3 0x0000600 /* 3 clock cycles */ 125 #define MPC105_PICR2_BURST_RATE 0x00000100 /* L2: 0:1, 1:2 clocks */ 126 #define MPC105_PICR2_FAST_CASTOUT 0x00000080 /* L2 Fast castout timing */ 127 #define MPC105_PICR2_TOE_WIDTH 0x00000040 /* TOE 0:2, 1:3 clock cycles */ 128 #define MPC105_PICR2_L2_SIZE 0x00000030 /* L2 cache size */ 129 #define MPC105_PICR2_L2_SIZE_256K 0x00000000 130 #define MPC105_PICR2_L2_SIZE_512K 0x00000010 131 #define MPC105_PICR2_L2_SIZE_1M 0x00000020 132 #define MPC105_PICR2_L2_SIZE_RSVD 0x00000030 133 #define MPC105_PICR2_APHASE_WS 0x0000000c /* Addr. phase wait states: */ 134 #define MPC105_PICR2_APHASE_WS0 0x00000000 /* 0 clock cycles */ 135 #define MPC105_PICR2_APHASE_WS1 0x00000004 /* 1 clock cycle */ 136 #define MPC105_PICR2_APHASE_WS2 0x00000008 /* 2 clock cycles */ 137 #define MPC105_PICR2_APHASE_WS3 0x0000000c /* 3 clock cycles */ 138 #define MPC105_PICR2_DOE 0x00000002 /* L2 first data read timing */ 139 #define MPC105_PICR2_WDATA 0x00000001 /* L2 first data write timing*/ 140 #define MPC105_AOVPR1 0xba /* Alt. OS-visible parameters 1 */ 141 #define MPC105_AOVPR2 0xbb /* Alt. OS-visible parameters 2 */ 142 #define MPC105_ERRENR1 0xc0 /* Error Enabling ter 1 */ 143 #define MPC105_ERRDR1 0xc1 /* Error Detection Register 1 */ 144 #define MPC105_60xBUSERRSTATR 0xc3 /* 60x Bus Error Status Register */ 145 #define MPC105_ERRENR2 0xc4 /* Error Enabling Register 2 */ 146 #define MPC105_ERRDR2 0xc5 /* Error Detection Register 2 */ 147 #define MPC105_PCIBUSERRSTATR 0xc7 /* PCI Bus Error Status Register */ 148 #define MPC105_ERRADDRR 0xc8 /* 60x/PCI Error Address Register */ 149 #define MPC105_MEMCTRLCR1 0xf0 /* Memory control configuration 1 */ 150 #define MPC105_MEMCTRLCR2 0xf4 /* Memory control configuration 2 */ 151 #define MPC105_MEMCTRLCR3 0xf8 /* Memory control configuration 3 */ 152 #define MPC105_MEMCTRLCR4 0xfc /* Memory control configuration 4 */ 153 154 #endif /* !_DEV_IC_MPC105REG_H_ */ 155